Introduction to Digital

Signal Controller

TMS320F2812

SUDHIR CHOPADE

What is TMS320F2812 ?

In computing, we frequently use words like

“Microprocessor”, “Microcomputer” or “Microcontroller” to

specify a given sort of electronic device.

When it comes to digital signal processing, the preferred

name is “Digital Signal Processors (DSP)”.

The TMS320F2812 belongs to a group of devices DSPs that

are called “Digital Signal Controller (DSC)”

To begin with,

let’s have a brief comparison of

Microprocessor (µP)

Micro Computer

Microcontroller (µC)

Digital Signal Processor (DSP)

Digital Signal Controller (DSC)

Microprocessor (µP):

Microprocessors are based on a simple sequential procedural

approach: such as…..

Read next machine code instruction from code memory,

Decode instruction,

Read optional operands from data memory,

Execute instruction and write back result.

This series of events runs in an endless manner.

To use a µP one has to add memory and additional external

devices to the Microprocessor.

• Inside MICRO processor four units take care of the

sequence of states.

• The bus-unit is responsible for addressing the

external memory resources using a group of

unidirectional digital address signals, bi-directional

data lines and control and status signals.

• Its purpose is to fill a first pipeline, called the

“instruction queue” with the next machine

instructions to be processed.

• It is controlled by the Execution unit and the

Address-Unit.

The Instruction unit reads the next instruction out of the Instruction queue, decodes it and fills

a second queue, the “Operation queue” with the next internal operations that must

be performed by the Execution Unit.

The Execution Unit does the ‘real’ work; it executes operations or calls the Bus Unit to read an

optional operand from memory. Once an instruction is completed, the Execution Unit forces

the Address Unit to generate the address of the next instruction

BASIC BLOCKS OF MICRO PROCESSOR

Architecture of Microprocessor (µP):

Two basic architectures:

Von Neumann- Architecture

Harvard – Architecture

Von Neumann - Architecture:

Shared memory space between code and data

Shared memory busses between code and data

Example: Intel‘s x86 Pentium Processor family

Harvard – Architecture:

Two independent memory spaces for code and data

Two memory bus systems for code and data

A µP to operate needs additional devices

The Desktop PC: a Micro Computer

When we add external devices to a Microprocessor, we

end up with the set up for a computer system.

We need to add external memory both for instructions

(“code”) and data to be computed.

We also have to use some sort of connections to the

outside world to our system. In general, they are

grouped into digital input/outputs and analogue

input/outputs.

These Peripherals include:

Digital Input / Output Lines

Analogue to Digital Converter (ADC)

Digital to Analogue Converter (DAC)

Timer / Counter units

Pulse Width Modulation ( PWM)

Output Lines, Digital Capture Input Lines

Network Interface Units

Serial Communication Interface (SCI) – UART

Serial Peripheral Interface ( SPI)

Inter Integrated Circuit ( I2C) – Bus

Controller Area Network (CAN)

Local Interconnect Network (LIN)

Universal Serial Bus (USB),Local / Wide Area Networks (LAN, WAN),Graphical

Output Devices and more …

A Micro Computer

Microcontroller (µC)

Nothing more than a Micro Computer as a single silicon

chip!

All computing power AND input/output channels that are

required to design a real time control system are “on

chip“

Guarantee cost efficient and powerful solutions for

embedded control applications

Backbone for almost every type of modern product

Over 200 independent families of µC available for

different applications

Both µP – Architectures („Von Neumann“ and „Harvard“)

are used inside Microcontrollers

The Microcontroller vs Microcomputers

As technology advances, we want the silicon industry to build

everything that is necessary for a microcomputer into a single

piece of silicon, and we end up with a microcontroller (“µC”).

Of course nobody will try to include every single peripheral that

is available or thinkable into a single chip – because nobody can

afford to buy this “monster”-chip.

No customer will ask for a microcontroller with an internal code

memory size of 16Mbytes, if the application fits easily into

64Kbytes.

Engineers demand a microcontroller that suits their applications

best and – for (almost) nothing.

This leads to a huge number of dedicated microcontroller families

with totally different internal units, different instruction sets,

different number of peripherals and internal memory spaces.

Digital Signal Processor A Digital Signal Processor is a specific device that is designed

around the typical mathematical operations to manipulate digital

data that are measured by signal sensors.

The objective is to process the data as quickly as possible to be

able to generate an output stream of ‘new’ data in

“real time”.

We can say that we have a real-time application if : Waiting Time

is greater than 0

What are the typical DSP algorithms? The Sum of Products (SOP) is the key element in most DSP algorithms:

Algorithm Equation

Finite Impulse Response Filter

M

k

k knxany

0

)()(

Infinite Impulse Response Filter

N

k

k

M

k

k knybknxany

10

)()()(

Convolution

N

k

knhkxny

0

)()()(

Discrete Fourier Transform

1

0

])/2(exp[)()(

N

n

nkNjnxkX

Discrete Cosine Transform

1

0

122

cos).().(

N

x

xuN

xfucuF

Why do we need DSP processors?

DSP processor when the following are required:

Cost saving.

Smaller size.

Low power consumption.

Processing of many “high” frequency signals in real-

time.

Use a GPP processor when the following are required:

Large memory.

Advanced operating systems.

Digital Signal Controller (DSC)

A Digital Signal Controller(DSC) is a single chip Microcomputer

with a Digital Signal Processor(DSP) as core unit.

By combining the computing power of a DSP with memory and

peripherals in one single device we derive the most effective

solution for embedded real time control solutions that require

lots of math operations.

DSC –Example: Texas Instruments C2000 family.

Broad C28x™ Application Base

Salient features of DSP TMS 320F2812 High-Performance 32-Bit CPU

16 x 16 and 32 x 32 MAC Operations

16 x 16 Dual MAC

On-Chip Memory

Flash Devices: Up to 128K x 16 Flash

ROM Devices: Up to 128K x 16 ROM

1K x 16 OTP ROM

L0 and L1: 2 Blocks of 4K x 16 Each SARAM.

External Interface

Up to 1M Total Memory

Three Individual Chip Selects

Three External Interrupts

Three 32-Bit CPU-Timers

150 MHz operating frequency.

12 bit ADC module.

Up to 56 general purpose input output pins.

Motor Control Peripherals

Two Event Managers

Architecture of TMS 320 F2812

Since a Digital Signal Processor is capable of executing six

basic operations in a single instruction cycle, the architecture

of the TMS320F2812 must reflect this feature in some way.

Doing six basic math’s operations is not a magic; we will find

all the hardware modules that are required to do so in this

chapter.

Among other things, we will discuss the following parts of the

architecture:

Internal bus structure

CPU

Hardware Multiplier, Arithmetic-Logic-Unit, Hardware-Shifter

Register Structure

Memory Map

TMS320F2812 Block Diagram

The TMS320F2812 Block Diagram can be divided into 4

functional blocks:

Internal & External Bus System

Central Processing Unit (CPU)

Memory

Peripherals

C281x Block Diagram

Interface

to connect

external

devices

The event manager (EV)

modules provide a broad

range of functions and

features that are

particularly useful in

power electronics

converters and motor

control applications.

The event-manager

modules include

general-purpose (GP)

timers, full compare/

PWM units, capture

units, and quadrature-

encoder pulse (QEP)

circuits.

To be able to fetch two operands from memory into the central

processing unit in a single clock cycle, the F2812 is equipped

with two independent bus systems – Program Bus and Data Bus.

This type of machine is called a “Harvard Architecture”.

Due to the ability of the F2812 to read operands not only from

data memory but also from program memory, it is called as

“modified Harvard Architecture”. The “bypass”-arrow in the

bottom left corner of slide 1-2 indicates this additional

feature.

The F2812 CPU

Three 32-bit timers can be used for general

timing purposes or to generate hardware driven

time periods for real time operating systems

The Peripheral Interrupt Expansion Manager (PIE) allows

fast interrupt response to the various sources of external

and internal signals and events. The F2812 CPU

A 32 by 32 bit hardware multiplier and a

32-bit arithmetic logic unit (ALU) can be

used in parallel to execute a multiply and

an add operation simultaneously. The

auxiliary register bank is equipped with its

own arithmetic logic unit (ARAU)– also used

in parallel to perform pointer arithmetic.

The JTAG-interface is a very powerful tool

to support real-time data exchange

between the DSC and a host during the

debug phase of project development.

It is possible to watch variables while

the code is running in real time, without

any delay to the control code

Features of C28x CPU The C28x is as efficient in DSP math tasks as it is in system control tasks that typically are

handled by microcontroller devices. This efficiency removes the need for a second processor in

many systems.

The 32 x 32-bit MAC capabilities of the C28x and its 64-bit processing capabilities, enable the

C28x to efficiently handle higher numerical resolution problems that would otherwise demand

a more expensive floating-point processor solution.

Add to this the fast interrupt response with automatic context save of critical registers,

resulting in a device that is capable of servicing many asynchronous events with minimal

latency.

The C28x has an 8-level-deep protected pipeline with pipelined memory accesses. This

pipelining enables the C28x to execute at high speeds without resorting to expensive high-

speed memories. Special branch-look-ahead hardware minimizes the latency for conditional

discontinuities. Special store conditional operations further improve performance.

The two EV modules, EVA and EVB, are identical peripherals, intended for multi-axis/motion-

control applications. The pulse-width modulation (PWM) circuits associated with compare units

make it possible to generate six PWM output channels (per EV) with programmable dead-band

and with desired output polarity.

Features of F2812 CPU

Real-Time JTAG and Analysis

The F281x and C281x implement the standard IEEE 1149.1

JTAG interface.

It support real-time mode of operation whereby the contents

of memory, peripheral, and register locations can be

modified while the processor is running and executing code

and servicing interrupts.

This is a unique feature to the F281x and C281x, no software

monitor is required.

Internal Bus Structure

As with many DSP type devices, multiple busses are used to move data between memory

locations, peripheral units and the CPU. The F2812 memory bus architecture contains:

• A program read bus (22 bit address line and

32 bit data line)

• A data read bus (32 bit address line and 32

bit data line)

• A data write bus (32 bit address line and 32

bit data line)

The 32-bit-wide data busses enable single

cycle 32-bit operations. This multiple bus

architecture, known as a Harvard Bus

Architecture enables the C28x to fetch an

instruction, read a data value and write a data

value in a single cycle. All peripherals and

memories are attached to the memory bus and

will prioritise memory accesses.

Data Memory Access Two basic methods are available to access data memory locations:

Direct Addressing Mode :

Direct addressing mode generates the 22-bit address for a memory access

from two sources – a 16-bit register “Data Page (DP)” for the highest 16 bits

plus another 6 bits taken from the instruction.

Advantage: Once DP is set, we can access any location of the selected page,

in any order.

Disadvantage: If the code needs to access another page, DP must be adjusted

first.

Indirect Addressing Mode:

Indirect addressing mode uses one of eight 32-bit XARn registers to hold the

32-bit address of the operand. Advantage: With the help of the ARAU, pointer

arithmetic is available in the same cycle in which an access to a data memory

location is made. Disadvantage: A random access to data memory needs a new

setup of the pointer register.

Data Memory Access

Direct addressing mode generates the 22-

bit address for a memory access from two

sources – a 16-bit register “Data Page

(DP)” for the highest 16 bits plus another 6

bits taken from the instruction.

Indirect addressing mode uses one of eight

32-bit XARn registers to hold the 32-bit

address of the operand.

Atomic Arithmetic Logic Unit ( ALU)

Atomics are small common instructions

that are non-interruptible. The atomic

ALU capability supports instructions and

code that manages tasks and processes.

These instructions usually execute

several cycles faster than traditional

coding.

F2812 Math Units The 32 x 32-bit Multiply and Accumulate (MAC) enable

this DSC to efficiently handle higher numerical resolution

problems. Along with this is the capability to perform

two 16 x 16-bit multiply and accumulate instructions

simultaneously or Dual MAC's (DMAC).

Multiplication uses the XT register to hold the first

operand and multiply it by a second operand

that is loaded from memory.

If XT is loaded from a data memory location and the

second operand is fetched from a program memory

location, a single-cycle multiply operation can be

performed.

The result of a multiplication is loaded into register P

(product) or directly into the accumulator (ACC).

The arithmetic logic unit (ALU) is doing the ‘rest’ of the math’s. The first operand is always the

content of the Accumulator (ACC) or a part of it. The second operand for an operation is loaded

from data memory, from program memory, from the P register or directly from the multiply unit.

32-Bit CPU-Timers (0, 1, 2)

CPU-Timers 0, 1, and 2 are identical 32-bit timers with pre-settable

periods and with 16-bit clock pre-scaling.

The timers have a 32-bit count-down register, which generates an

interrupt when the counter reaches zero.

The counter is decremented at the CPU clock speed divided by the

pre-scale value setting.

When the counter reaches zero, it is automatically reloaded with a

32-bit period value.

CPU-Timer 2 is reserved for the DSP/BIOS Real-Time OS, and is

connected to INT14 of the CPU. If DSP/BIOS is not being used, CPU-

Timer 2 is available for general use.

CPU-Timer 1 is for general use and can be connected to INT13 of the

CPU. CPU-Timer 0 is also for general use and is connected to the PIE

block.

General-Purpose Input / Output (GPIO) Multiplexer

Most of the peripheral signals are multiplexed with general-

purpose I/O (GPIO) signals.

This multiplexing enables use of a pin as GPIO if the peripheral

signal or function is not used.

On reset, all GPIO pins are configured as inputs.

The user can then individually program each pin for GPIO mode or

peripheral signal mode.

Control Peripherals

The F281x and C281x support the following peripherals that are

used for embedded control and communication:

EV: The event manager module includes general-purpose

timers, full-compare/PWM units, capture inputs (CAP) and

quadrature-encoder pulse (QEP) circuits. Two such event

managers are provided which enable two three-phase motors to

be driven or four two phase motors.

ADC: The ADC block is a 12-bit converter, single ended, 16-

channels. It contains two sample and-hold units for

simultaneous sampling.

Serial Port Peripherals

The F281x and C281x support the following serial communication

peripherals:

eCAN: This is the enhanced version of the CAN peripheral. It

supports 32 mailboxes, time stamping of messages, and is CAN

2.0B-compliant.

McBSP: The multichannel buffered serial port (McBSP) connects to

E1/T1 lines, phone-quality codecs for modem applications or

high-quality stereo audio DAC devices. The McBSP receive and

transmit registers are supported by a 16-level FIFO that

significantly reduces the overhead for servicing this peripheral.

Serial Port Peripherals

SPI: The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of programmed length (one to sixteen bits) to be shifted into and out of the device at a programmable bit-transfer rate.

Normally, the SPI is used for communications between the DSP controller and external peripherals or another processor.

Typical applications include external I/O or peripheral expansion through devices such as shift registers, display drivers, and ADCs.

Multi-device communications are supported by the master/slave operation of the SPI.

SCI: The serial communications interface is a two-wire asynchronous serial port, commonly known as UART.

Peripheral Interrupt Expansion (PIE) Block

The PIE block serves to multiplex numerous interrupt sources into a smaller

set of interrupt inputs.

The 96 interrupts are grouped into blocks of 8 and each group is fed into 1

of 12 CPU interrupt lines (INT1 to INT12).

Each of the 96 interrupts is supported by its own vector stored in a

dedicated RAM block that can be overwritten by the user.

The vector is automatically fetched by the CPU on servicing the interrupt. It

takes 8 CPU clock cycles to fetch the vector and save critical CPU registers.

Hence the CPU can quickly respond to interrupt events.

Prioritization of interrupts is controlled in hardware and software. Each

individual interrupt can be enabled/disabled within the PIE block

Oscillator and PLL The F281x and C281x can be clocked by an external

oscillator or by a crystal attached to the on-chip oscillator

circuit.

A PLL is provided supporting up to 10-input clock-scaling

ratios.

The PLL ratios can be changed on-the-fly in software,

enabling the user to scale back on operating frequency if

lower power operation is desired.

The PLL block can be set in bypass mode.

Watchdog

The F281x and C281x support a watchdog timer.

The user software must regularly reset the watchdog

counter within a certain time frame; otherwise, the

watchdog will generate a reset to the processor.

The watchdog can be disabled if necessary.

Peripheral Clocking

The clocks to each individual peripheral can be enabled/disabled

to reduce power consumption when a peripheral is not in use.

Additionally, the system clock to the serial ports (except eCAN)

and the event managers, CAP and QEP blocks can be scaled

relative to the CPU clock.

This enables the timing of peripherals to be decoupled from

increasing CPU clock speeds.

Low-Power Modes The F281x and C281x devices are fully static CMOS devices. Three low-power

modes are provided:

IDLE: Place CPU in low-power mode. Peripheral clocks may be turned off

selectively and only those peripherals that must function during IDLE are left

operating. An enabled interrupt from an active peripheral will wake the

processor from IDLE mode.

STANDBY: Turns off clock to CPU and peripherals. This mode leaves the

oscillator and PLL functional. An external interrupt event will wake the

processor and the peripherals. Execution begins on the next valid cycle after

detection of the interrupt event.

HALT: Turns off the internal oscillator. This mode basically shuts down the

device and places it in the lowest possible power consumption mode. Only a

reset or XNMI can wake the device from this mode.

A view of TMS 320 F2812

Connection points for TMS 320 F2812

Features of DSP TMS320C2812

Features of DSP TMS320C2812

Thank you!