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Sub- Nyquist Sampling Algorithm Implementation on Flex Rio. High Speed Digital Systems Lab. By : Genady Paikin , Ariel Tsror . Supervisors : Inna Rivkin , Rolf Hilgendorf. Agenda :. Project overview Goals Learning Process Hardware Sampling stage CTF module DSP module Gantt Chart. - PowerPoint PPT Presentation
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Sub-Nyquist Sampling Algorithm Implementation on Flex Rio
By: Genady Paikin, Ariel Tsror.Supervisors :
Inna Rivkin, Rolf Hilgendorf.
High Speed Digital Systems Lab
Agenda: Project overviewGoalsLearning ProcessHardwareSampling stageCTF moduleDSP moduleGantt Chart
Project OverviewThe project is part of the Sub-
Nyquist sampling and reconstruction card.
Our goal is to implement 2 units – CTF & DSP, on FlexRio FPGA cards under NI LabView environment.
The unit also includes the Xampling sampling card And the Expand unit.
Goals: Main goal – implementing CTF &
DSP on FPGA’s under NI LabView environment using VHDL, Full integration, running full system at real time.
Optimization :◦Latency.◦Resources.◦Minimize reconstruction errors.
Hardware: NI chassis with 4* FlexRio FPGA modules
◦FlexRio : Model : NI PXIe 7965R Bus : PXI Express FPGA : Virtex-5 SX95T (Xilinx) FPGA memory : 8,784 Kbits Onboard Memory : 512MB FPGA Slices : 14,720 FPGA DSP Slices : 640
A/D.Xampling sampling card.
* Expand, DSP, CTF, Reconstruction
Learning Process: Learning process composed of 2
independent processes :◦Algorithm :
System main concept. Sampling stage (Xampling and Expand). CTF module. DSP module (inc. SCD).
◦LabView : LabView main concepts. FPGA under LabView. Integration. Implementing Basic unit as training.
Reading matrix from file to memory on FlexRio FPGA using LabView environment.
High Level Architecture:
Xampling
Sampling stage: The sampling stage contain two
units ◦Xampling sampling card.◦Expand.
Expand
1:3
Analog in
4X62.5 Mhzdigital
12X20.8 Mhzdigital
A/D62.5 Mhz(250 1:4 decim.)
Xampling
CTF module: Task : Detects the Support of x(t)
and forward it to DSP unit.Triggered at :
◦Initiation.◦SCD interrupt.
The unit based on OMP (Orthogonal Matching Pursuit) algoritm.
Block Diagram:
A
Qframe
calculation
MPy[n]
A
Supp
0
fNH
Qn
n n
Q y y AU
DSP module: Task: Reconstructs the signal from the
samples. The unit receives the samples from the
memory (latency fifo), matrix A from the memory, and signal support from the CTF unit.
The support and samples are coordinated by the latency fifo.
The unit performs pseudo-inverse of matrix A (calculates As) using the signal support, that is received from the CTF.
Finally the unit multiply the delayed signal with matrix As.
DSP module: DSP
Pseudo Inverse
Multiplication
Signal’s sample (from
memory)
Matrix A (from memory)
Signal support(from CTF)
Reconstructedsignal
As+
SCD module: Task: Detects if there is a change
of the signal support.The unit uses the signal energy
to decide if the CTF needs to recalculate the signal support.
Support Change Detector
Signal’s sample (from
expand)
Recalculate support (to CTF)
Gantt:
WBS TasksTaskLead Start End
Duration (Day
s)
%Compl
ete
Working Day
s
Days
Complete
Days
Remaining
7 Marc
h 2011
14 Marc
h 2011
21 Marc
h 2011
28 Marc
h 2011
4 April 2011
11 April 2011
18 April 2011
25 April 2011
2 May 2011
9 May 2011
16 May 2011
23 May 2011
30 May 2011
1 Learning the algoritm 9/3/11 7/4/11 30 86% 22 25 5
1.1 Learnig the algoritm in general 9/3/11 22/3/11 14 100% 10 14 0
1.2 Learning xampling card 9/3/11 22/3/11 14 100% 10 14 0
1.3 Learning expand unit 18/3/11 7/4/11 21 80% 15 16 5
1.4 Learning CTF unit 18/3/11 7/4/11 21 80% 15 16 5
1.5 Learning DSP unit 18/3/11 7/4/11 21 80% 15 16 5
1.6 Learning SCD unit 18/3/11 7/4/11 21 80% 15 16 5
2 Learning LabView 23/3/11 29/5/11 68 1% 48 0 68
2.1 Basic level 23/3/11 12/4/11 21 10% 15 1 20
2.2 VHDL in LabView 7/4/11 6/5/11 30 0% 22 0 30
2.3 Advance LabView and Building the training unit 30/4/11 29/5/11 30 0% 20 0 30
