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STT-RAM Circuit Design. Column Circuitry Simulation (IBM 65nm) Fengbo. Design Constraints. MTJ Char. (From Jianping’s group) R P ≈ 744 Ω TMR ≈ 136% Max writing current 1.5 mA for P->AP 630 uA for AP->P Min writing current Reading - PowerPoint PPT Presentation
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STT-RAM Circuit Design
Column Circuitry Simulation(IBM 65nm)
Fengbo
Design Constraints
MTJ Char. (From Jianping’s group)– RP ≈ 744Ω
– TMR ≈ 136% Max writing current
– 1.5 mA for P->AP – 630 uA for AP->P
Min writing current
Reading– [220 uA,1 ns] current has 1% probability of disturbance. – Short pulse read (<300 ps) is needed
2
0 2 4 6 8 10
0
20
40
60
80
100
V=0.39 V V=0.49 V V=0.58 V V=0.68 V V=0.78 V
Sw
itch
ing
Pro
bab
ility
(%
)
Pulse Width (ns)
(Breakdown voltage =
1.1V)
Switching time (ns)
Min Current for 100% Switching Probability (uA)
AP-P P-AP
5 330 6603 387 774
MTJ Sub-array
64x512, 32 kb sub-array– 64 WL
– 4 128-bit words on each WL
– 4 columns share 1 sense amp& write driver through 4-1 mux
– 40F2 cell size used.
3
Column Circuitry
4
Write
P->AP– Vgs_P = VWL - Vdrop ≈ VDDW
– Vds_P = VDDW – Vdrop – Vmtj_P
AP->P– Vgs_AP = VWL – Vdrop – Vmtj_AP
– Vds_AP = VDDW - Vdrop – Vmtj_AP
Boosting VWL
– Limited by Vgs_P (0.1 V margin)
Boosting VDDW
– Limited by Vds_AP (0.5-0.6 V margin)
– Have to use thicker oxide devices in the write driver circuit (in red) 5
Write Current Comparison
6
Compare 3 cases of boosting voltage
Constraints – VDDW < VDD
max
– Vgs, Vds < VDDmax
● For all devices
Rp = 744 Ω Ref Case 1 Case 2 Case 3
FET in arrayThin Oxide
LvtThin Oxide
LvtThin Oxide Lvt Thin Oxide Lvt
FET in write driver
Thin Oxide Rvt
Thin Oxide Rvt
Medium Oxide 1.5V high-speed
IO
Thick Oxide 1.8V regular IO
VDDmax (V) 1.1 1.1 1.65 1.98
VDDW (V) 1 1.1 1.65 ABAPVWL (V) 1 ABAP ABAP ABAP
Write Current Comparison Result
7
Boost up VDDW to 1.1V, VWL to max - 21-22% gain
Boost up VDDW to 1.5V, VWL to max - 30-33% gain– Medium oxide device used, 2.2x bigger write driver
Boost up VDDW to 1.9V, VWL to max - 35-37% gain– Thick oxide device used, 7.6x bigger write driver
Rp = 744 Ω Ref Case 1 Case 2 Case 3
VWL (V) 1 1.17 1.23 1.3
VDDW (V) 1 1.1 1.65 1.9
Vds (V)P->AP 0.42 0.38 0.66 0.78
AP->P 0.57 0.55 0.95 1.1
Vgs (V)P->AP 0.93 1.09 1.09 1.1
AP->P 0.6 0.66 0.63 0.63
Iw (uA)P->AP 585 739 868 925
AP->P 210 270 301 325
Area Overhead 1x 2.2x 7.6x
I Gain v.s. Ref
P->AP 21% 33% 37%
AP->P 22% 30% 35%
Read
Short pulse reading
8
Read simulation result
270 ps only read current pulse– 150 ps pulse of control signal– 270 ps pulse current through MTJ– Read time:157 ps for Rp,167 ps for Rap
9
