© 2008 Grandis Corporation 110/15/2008

Current Status and Future Outlook of STT-RAM Technology

Eugene Chen and Co-workers

Grandis, Inc., Silicon Valley, U.S.A.

University of Alabama, MINT STT-RAM Workshop

October 15, 2008

© 2008 Grandis Corporation 210/15/2008

Grandis develops and licenses STT-RAM proprietary NVM solutions. Grandis’

STT-RAM enables a wide variety of low-cost and high-performance memory products

at the 65 nm technology node and beyond.

Grandis corporate snapshot

• World leader in Spin-Transfer Torque RAM (STT-RAMTM)

• Incorporated in Delaware in 2002

• Top-tier VC Funded– Sevin Rosen, Applied Ventures, Matrix Partners,

Incubic, Concept Ventures

• Headquarters: Silicon Valley, California

• R & D Offices: California, Japan, South Korea

• Strong & broad STT-RAMpatent portfolio and know-how

– 38 Granted U.S. Patents – > 50 U.S. Patents Pending– > 30 Invited Talks/Papers at International Conferences

• www.GrandisInc.com

© 2008 Grandis Corporation 310/15/2008

“0”

Barrier

Reference layer (pinned)(spin filter)

Storage layer (free)

SelectionTransistor

Current

“1”

MTJ

Source LineSource LineW

ord L

ine

Word

Lin

e

Bit Line

Source Line

Bit Line

Word

Lin

e

Word

Lin

e

Switching magnetization of storage layerusing a spin-polarized currentinstead of a magnetic field

Grandis pioneered exploration of STT in MTJs and developed STT-RAM technology

STT-RAM offers a potential scalable “universal” memory solution (small, low power, fast, and non-volatile)

STT writing scheme – a breakthrough

0

1

2

3

4

5

6

7

8

C u r r e n t

Resis

tan

ce (

k O

hm

)

H ig h r e s is t a n c e

1

L o w r e s is t a n c e

0

(µµµµA)

© 2008 Grandis Corporation 410/15/2008

Theoretical Prediction (1996)

- J. Slonczewski, J. Magn. Mater. 159, 1 (1996)- L. Berger, Phys. Rev. B 54, 9353 (1996)

Early Convincing Experiments

In bi-stable CPP-GMR- J. A. Katine, et al., Phys. Rev. Lett. 84, 3149 (2000)- J. Grollier, et al., Appl. Phys. Lett. 78, 3663 (2001)- J. Z. Sun, et al., Appl. Phys. Lett. 81, 2202 (2002)- K. Yagami, et al., Appl. Phys. Lett. 85, 5634 (2004)

STT Switching In MTJs

-Y. Huai, et al., Appl. Phys. Lett. 84, 3118 (2004)- G. Fuchs, et al., Appl. Phys. Lett. 85, 1205 (2004)- Y. Higo, et al., Appl. Phys. Lett. 87, 082502 (2005)- Y. Huai, et al., Appl. Phys. Lett. 87, 222510 (2005)

MgO MTJs

- Z. Diao, et al., Appl. Phys. Lett. 87, 232502 (2005)- H. Kubota, et al., JJAP, 44, L1237 (2005)- M. Hosomi, et al., IEDM 2005 Digest, 05-473 (2005)

Room Temperature

116.0

118.0

120.0

122.0

124.0

126.0

128.0

-2.5 -1.5 -0.5 0.5 1.5 2.5

I (mA)

R ( )

121.0

123.0

125.0

127.0

129.0

-100 -80 -60 -40 -20 0 20 40

H (Oe)

R ( )

ΔΔΔΔR/R = 5.0%

Ha = - 50 Oe

Ic+(p->ap)=1.7mA

Ic-(ap->p)=2.0mA

RA = 2.6 ΩμΩμΩμΩμm2ΔΔΔΔR/R=5.0%

Hoff= - 51 Oe

Hc=30 Oe

1000

2000

3000

4000

5000

6000

7000

-0.4 -0.2 0 0.2 0.4

I (mA)

R (

Ω)

1000

2000

3000

4000

5000

6000

7000

-50 0 50 100 150

H (Oe)

R (

Ω)

1000

2000

3000

4000

5000

6000

7000

-0.4 -0.2 0 0.2 0.4

I (mA)

R (

Ω)

1000

2000

3000

4000

5000

6000

7000

-50 0 50 100 150

H (Oe)

R (

Ω)

A short history of STT switching

© 2008 Grandis Corporation 510/15/2008

Key Advantages over conventional MRAM:

• Excellent write selectivity <— Localized spin-injection within cell• High scalability <— Write current scales down with cell size • Low power consumption <— Low write current (<100 µA)• Simpler architecture <— No write line, no by-pass line and no cladding• Faster operation <— Multibit (parallel) writing compatible

Conventional MRAM Cell

Write Current: Write Current: IIswsw ~ 1 / Volume ~ 1 / Volume

STT-RAM Cell

IIswsw ~ Volume~ Volume

STT-RAM versus conventional MRAM

© 2008 Grandis Corporation 610/15/2008

STT-RAM cell

STT-RAM retains all the good features of

previous MRAM technologies

STT writing scheme removes the hurdles

of MRAM: high writing current and

poor scalability

Multibit storage capable

TMR~200 %

Free layer 2

Free layer 1

Barrier 2

Barrier 1

Pinned layer 2

Pinned layer 1

Antiferromagnet

Free layer 2

Free layer 1

Barrier 2

Barrier 1

Pinned layer 2

Pinned layer 1

Antiferromagnet

(1T-1MTJ)

Advantages of STT-RAM writing scheme

MgO MTJ paves the way for STT-RAM to be competitive

© 2008 Grandis Corporation 710/15/2008

Challenge of reducing Jc0 while maintaining ∆∆∆∆

• Switching current:

• Thermal stability:

• To maintain ∆ with the high Ms, the switching current increases.

• For reliable memory application, we need small Ic0 with high ∆ – very challenging task

Tk

AtM

Tk

AtM

B

FS

B

FS

22

K

2

H∝=∆

Assuming intrinsic anisotropy is much smaller than shape anisotropy.

...,2

20 ++=

+= shapeIntrisicK

dK

FSc HHH

HH

etAMI

hη

α

© 2008 Grandis Corporation 810/15/2008

Technical exploration

• Innovative spin engineering, materials & structures with optimized process & design (cell architecture and circuits)

( )

+±=

±

±

extd

KFS

c HH

HetM

J mh 2

2)(

0η

α

Jc0 (1 ns) ≤ 1.0 MA/cm2

TMR>100%∆∆∆∆>60…

Dual MTJs

Low Ms

Perpendicular MTJ

…

Synthetic free layer

© 2008 Grandis Corporation 910/15/2008

4000

5000

6000

7000

8000

9000

-0.4 -0.2 0 0.2 0.4

I (mA)

R (

Ω)

4000

5000

6000

7000

8000

9000

-200 -150 -100 -50 0

H (Oe)

R (

Ω)

(b) (a)

<Ic>=0.13 mA

Ha = -110 Oe

TMR : 70%

Hc= 50 Oe; Hoff = -110 Oe

120 nm x 240 nm

Jc (at 30 ms)~ 0.52 MA/cm2

- (Grandis) Diao, et al., Appl. Phys. Lett. 90, 132508 (2007)

Current reduction in dual MgO MTJ

-1.0

-0.5

0.0

0.5

1.0

Pulse Width (s)

Jc (

MA

/cm

2)

Jc0 AP-P

= - 1.01 MA/cm2

Jc0 P-AP

= 0. 94 MA/cm2

10-3

10-2

10-1

100 10

1

Grandis US patent: 7,057,921

FL

PL

PL

2 MTJ barriers

Improvement in dual MTJ structure:

• ST torque experienced by FL on two surfaces• Smaller damping due to decreased spin pumping effect

• Results in 2-3x decrease in switching current as compared to single MTJ

Jc0 (at 1 ns)~1.0 MA/cm2

© 2008 Grandis Corporation 1010/15/2008

STT-RAM schematic

MTJ

Cell Tr.

WL

BL SLBL SLSL BL

WL

WL

WL

© 2008 Grandis Corporation 1110/15/2008

Typical MTJ I-V and R-V curves

© 2008 Grandis Corporation 1210/15/2008

0

0.5

1

1.5

2

2.5

-9 -8 -7 -6 -5 -4 -3 -2 -1 0

Pulse Width (log(t))

VB

D

Dynamic breakdown voltage (>1.5V)

Breakdown voltage versus pulse width

For 10 ns pulses, the breakdown voltage (~1.8 V) is more than3 times greater than typical STT switching voltages.

© 2008 Grandis Corporation 1310/15/2008

Endurance stress test

The pulse width is 10 ns and the stress voltage is 1.0 V.The test was suspended due to test time.

0.0

0.5

1.0

1.5

1E+1 1E+3 1E+5 1E+7 1E+9 1E+11 1E+13

log(N pulses)

TM

R (norm

aliz

ed)

Write cycling endurance ~1013

© 2008 Grandis Corporation 1410/15/2008

Excellent scalability of STT-RAM

Scalability of STT-RAM technology

STT switching current (normalized to level for 90 nm technology node) reduces linearly with cell area

0.0

0.2

0.4

0.6

0.8

1.0

0.0E+00 5.0E-03 1.0E-02 1.5E-02MTJ cell area (µm2)STT switching current (normalized) 90 nm

50 nm 64 nm 78 nmNovel MTJ structures/FL anisotropy enhancement to maintain high ∆

© 2008 Grandis Corporation 1510/15/2008

Memory technology comparison

Overall, STT-RAM is superior to other memory technologies

SRAM DRAMFlash (NOR)

Flash (NAND)

FeRAM MRAM PRAM STT-RAM

Non-volatile No No Yes Yes Yes Yes Yes Yes

Cell size (F2) 50–120 6–10 10 5 15–34 16–40 6–12 6–20

Read time (ns) 1–100 30 10 50 20–80 3–20 20–50 2–20

Write / Erase time (ns)

1–100 50 / 501 µs /

10 ms1 ms /0.1 ms

50 / 50 3–20 50 / 120 2–20

Endurance 1016 1016 105 105 1012 >1015 1010 >1015

Write power Low Low Very high Very high Low High Low Low

Other power consumption

Current leakage

Refresh current

None None None None None None

High voltage required

No 2 V 6–8 V 16–20 V 2–3 V 3 V 1.5–3 V <1.5 V

Existing products Prototype

© 2008 Grandis Corporation 1610/15/2008

STT-RAM: A Challengingand High-Reward Opportunity

Huge, Fast-Growing Memory Markets

Grandis STT-RAM:- Universal memory solution:

• SRAM read/write speed, ns

• DRAM and Flash Density• Non-volatility of Flash• Unlimited Endurance • Highly Scalable

Increasing Demands:- Perfect memory:

• Data always available• Never lost• Instantly retrieved• At lowest cost• …

2005 ( iSuppli)

Total Semiconductor Memory Market

0

20

40

60

80

100

120

140

160

2007

2008

2009

2010

2011

2012

2013

$ B

illions Total Discrete

Memory Market

Total EmbeddedMemory Market

© 2008 Grandis Corporation 1710/15/2008

Summary

• STT-RAM is a disruptive technology for semiconductor memory applications. It provides all the attributes of a universal memory:

• SRAM read/write speed, ns• DRAM and Flash Density• Unlimited Endurance • Non-volatility of Flash• Highly Scalable

• Fast read/write speeds (~2 ns), endurance over 1012 and low switching current (<200 µµµµA at 90nm with ∆∆∆∆>60) and its narrow distribution (1σ σ σ σ ≤3%) have been demonstrated in our prototype chips.

• STT-RAM has a huge potential market for replacing eSRAM, eFlash, DRAM … at 45 nm and beyond.

© 2008 Grandis Corporation 1810/15/2008

Please visit www.GrandisInc.com for more information