Technical Stealth Dicing

Informationfor MEMS

2

3

"Stealth dicing features" that will completely rewrite conventional dicing concepts

Processing method

Water (cooling / cleaning)

Chipping

Debris generation

T-shape and round shape dicing

High-speed ultra-thin wafer dicing

Chip yield

Processing speed

Thermal effect on device

Grinding cutting and process

Required

Occurs

Generates

Not possible

Might be possible in certain cases

Not so good

Not so good

Affected (including residual stress)

* HAZ: Heat Affective Zone

Surface absorption laser process

(melting, evaporation)

Required

Occurs

Generates

Possible in certain cases

Possible in certain cases

Not so good

Not so good

Affected (HAZ*)

Internal absorption laser process

(locally selective)

Not required

Does not occur

Does not generate

Possible

Possible

Good

Good

Not affected

Stealth dicing

Laser dicing

Wafer dicing

Laser ablation dicing

Blade dicing

1. Introduction

2. Problems with dicing in MEMS fabrication processes2.1 Grinding wheel type blade dicing

2.2 Making dicing a completely dry process

3. Stealth dicing technology3.1 Basic principle of stealth dicing

3.2 Internal-process laser dicing versus surface-process laser processing

3.3 Range of thermal effects on MEMS devices during internal laser process

3.4 Checking thermal effects on device characteristics

3.5 Limitations when using stealth dicing

4. Stealth dicing boosts profits4.1 Benefits from a 10 µm kerf width

4.2 Benefits when dicing irregular chip shapes

5. Dicing materials other than silicon5.1 Glass wafers

5.2 Roadmap to future stealth dicing technology

6. How green-friendly stealth dicing improves our environment

7. Conclusion

Table of Contents

4

Various different kinds of technologies such as mechanical engi-neering, quantum mechanics, electrical engineering, chemistry, and optics that were thought of as different fields until recently were merged on a semiconductor fabrication process as micromachining technology. This new technology offers tremendous possibilities that are starting to gather much attention. This technology has gradually grown along with the spread of etching technology since it could freely form thin film structures, girders and hollow struc-tures with fine accuracy to the micro level on wafers. These capa-bilities appealed to the imaginations of MEMS (micro electro me-chanical system) designers who are now starting to create totally new functional devices. Stealth dicing is a completely new laser dicing technology. Stealth dicing offers amazing advantages since it is a "completely dry process" yet generates "no debris" and has "zero kerf loss". This technology was especially developed for the purpose of high-speed yet high-quality dicing of ultra-thin semiconductor wafers and its features are equally effective in dicing processes for MEMS devi-ces. Stealth dicing is already being used for mass producing MEMS devices and is on its way to becoming an industry standard for MEMS device production.This technical material covers problems encountered in MEMS dicing as well as principles and processes involved in stealth dicing technology. It also offers a brief look at trends in developing new types of stealth dicing for use on materials other than silicon.

2.1 Grinding wheel type blade dicingMajor problems that must be avoided during dicing of MEMS de-vices with fragile structures include contamination and stress loads on the functional elements. The following are inevitable problems with the dicing process used in typical blade dicing processes.1Problem with wet processes

· Fluid pressure applies stress loads on the structure due to use of cooling water and rinse water during dicing.

· Functional elements are re-contaminated by foul cutting fluid· Requires adding a protective film for protecting device struc-

tures from water and foul water as well as a process to re-move that film

2Problems with contact type processes· Contact type cutting processes apply a vibrating load to the

structureFigure 1 shows problems that occur when an MEMS device having a membrane structure is cut by blade dicing. Photo 1 shows dam-age to membrane structures due to fluid pressure during blade dic-ing.

TLASC0022EA

Structural damage

Membrane crack

Diamond grinding wheelCooling / rinse water

Debris adhesionKerf loss

Debrisgeneration

Chipping

Figure 1: Problems with blade dicing

Photo 1: Membrane damage due to fluid pressure

2. Problems with dicing in MEMS fabrication processes

1. Introduction

5

2.2 Making dicing a completely dry processWhen dicing an MEMS device, dicing technology is needed that applies minimal stress to the delicate structures inside the MEMS device. At the same time, some measures are also needed to pre-vent the device structures from particle recontamination. These problems can be eliminated by switching to a dicing process with the following features: 1Fully dry processing: Prevents defects caused by wet process

and reduces man-hours needed for production/inspection2Non-contact dicing process: Eliminates stress applied to the

device structures due to vibration accompanying the cutting process

Stealth dicing offers both these features 1 and 2 described above. In dicing technology using lasers, the ablation method has long been studied as a laser process method 1) 2). Laser ablation, howev-er, produces debris contaminants during processing so pre-process-ing is needed to coat a protective film for protecting the device structures from these contaminants, and post-processing such as wet washing is also required.The next section briefly describes how stealth dicing is performed in a completely dry process.

3.1 Basic principle of stealth dicingIn stealth dicing, a laser beam at a light wavelength semitranspar-ent to the material is focused on a point inside that material to form a cleaving start point (transformed area: hereafter called SD layer), and external pressure then applied to the wafer to separate it into multiple chips 3) 4).This technology therefore includes two processes. One is a "laser process" to form a cleaving start point (SD layer) on the interior of the wafer for separating it into chips; and the other is a "separation process" to divide the wafer into small chips. Figure 2 above shows an overview of the laser process.

1Step 1 - Laser processA laser beam is focused on points inside the wafer to form an SD layer for cutting the wafer. Cracks are also formed on this SD layer

in the interior of the wafer, which extend towards both surfaces of the wafer. These cracks are an indispensable element for dividing the wafer into chips and should not twist broadly around the chip or be prevented from developing towards both surfaces. When cut-ting a thick silicon wafer device such as MEMS devices, it is the most important step to form SD layers and joint them vertically while making multiple scans depth-wise in the wafer, so that an op-timal SD layer for cutting is formed.How these cracks relate to the SD layer is shown in Figure 3, along with the three states that we should understand for deciding the processing conditions.SD layers can be made into the three states according to the pur-pose and application. These states can be combined to form an ide-al combination. Optimal processing conditions can be found via the device state such as the wafer thickness, chip shape, and whether a metallic film is used, etc. Once these conditions are found they can be systematized in a database for use according to the particular user and device.

Figure 3: Interrelation of SD layer and cracks formed in laser processTLASC0025EA

3. Stealth dicing technology

Cracks

SD layer

Cracks have not reached top or bottom surfaces (internal crack state)

a) ST: Stealth

Cracks

SD layer

Cracks have reached laser irradiation bottom surface (surface crack state)

c) BHC: Bottom side half-cut

Cracks

SD layer

Cracks have reached laser irradiation surface (surface crack state)

b) HC: Half-cut

Figure 2: Step 1 - Laser processTLASC0023EA

Scan direction

Laser beam SD layer and cracks

Wafer

Tape

6

TLASC0026EA

Figure 5: Crack extension principle Photo 2: Photograph of chip cut by stealth dicing

Figure 4: Step 2 - Separation processTLASC0024EA

An overview of the "separation process" is next shown in Figure 4.

2Step 2 - Separation processExpanding a tape-mounted wafer already formed with an SD layer towards the periphery of the wafer applies a tensile stress to the in-ternal cracks in the wafer. This stress causes the internal cracks to develop towards both surfaces of the wafer and separates the wafer into small chip shapes.Figure 5 shows a schematic view of the process up to separating the wafer into chips by extending the SD layer cracks formed in-side the wafer. Forming an HC (half-cut) or a BHC (bottom side half-cut) during forming of the SD layer will make it easier to separate the wafer in-to chips. When the tape is then expanded towards the periphery of the wafer while in this state, the HC or BHC surface is pulled to-

wards the wafer periphery, so that a pulling or tensile stress propa-gates along the wafer and the stress concentrates at the tip of the crack. This concentrated stress causes the crack to instantaneously reach the wafer surface, and the wafer then splits into small chips. 4)

Photo 2 shows a cross section of an MEMS chip having a mem-brane structure that was cut by stealth dicing. Both the front and back surfaces of the chip have sharp and clean dicing lines with no chipping. The membrane structure in the chip center section also shows good quality dicing with no traces of damage or debris that known to cause defects. The tape expansion process effectively ap-plies stress to the crack tips without causing mutual interference with chips adjacent to each other.

Tap expansion

Tape expansion

Separated chip

Tensile stress

Compression stress

Tape expansion

Crack extensionWafer

Tensile stress

TapeBHC

Tape expansion

Crack extensionWafer

Tensile stress

Tape

Tape expansion

Tape expansion

Tape expansion

Tape expansion

Crack has reached upper surface

Wafer Tensile stress

Tape

7

TLASC0035EA

3.2 Internal-process laser dicing versus surface-proc-ess laser processing

The difference between stealth dicing and ordinary laser surface process is briefly described next.Photo 3 shows processing results when using different laser focus positions. This photograph allows comparing results from surface process by focusing the laser beam on the surface of a wafer with results from focusing the laser beam on an internal point of the wa-fer.5)

A unique feature of stealth dicing is that the laser beam first irradi-ates an internal point in the material and starts cutting from that

point. This cutting principle is clearly different from the surface ablation method that carves a groove on the wafer by making the laser beam be absorbed in the surface of the material.Stealth dicing is a clean cutting technology that emits no molten particles such as silicon dust onto the wafer surface during laser process. The range of thermal effects from laser process in terms of heat distribution on the internal and front surface reportedly differs greatly according to the laser beam depth.6) Directing the laser beam on the interior of the wafer during laser process was found more effective in keeping a small heat distribution area than the conventional surface-focused laser process.

Photo 3: Comparing stealth dicing (internally focused laser dicing) with laser surface process

10 µm

Modified layer (SD layer)(Laser internal process)

Molten silicon

10 µm

Si SiSurface

Cross section

Surface

Cross section

Stealth dicing(Internally focused laser process)

Surface ablation process(Surface focused laser process)

Laser beam

Silicon wafer

SD layer

Laser beam

Debris

Silicon wafer

10 µm

10 µm

8

TLASB0012EA

TLASC0027EA

Figure 6: Temperature distribution range within the silicon wafer per laser pulse

Figure 7: Thermally affected area when forming SD layer

3.3 Range of thermal effects on MEMS devices during internal laser process

The first area of concern during laser dicing process is what ther-mal effects the laser process will have on the active area. Making a localized measurement of the actual temperature during laser proc-ess is not an easy task. Here we briefly discuss the internal temper-ature distribution in silicon during stealth dicing by using a report 7) from a simulation made to analyze thermal effects in silicon mate-rial based on temperature dependence of the laser light absorption coefficient in monocrystalline silicon material.Figure 6 shows results derived from a thermal simulation analyzing the heat distribution within silicon material at each pulse near the focused beam point during laser process to form an SD layer. This was performed by focusing the laser beam at a position whose depth is 60 µm from the surface of a 100 µm thick silicon wafer. Examining the maximum temperature distribution range in Figure 6 shows that the range where the temperature in the silicon rises 200 °C or higher during laser process is confined within ±7 µm centered laterally around the laser beam point.

Figure 7 shows these results applied to an actual device wafer. On a typical device wafer, the width of the so-called dicing street is about 50 µm to 70 µm. A look at Figure 7, however, shows that the thermally affected area remains small during stealth dicing com-pared to a typical dicing street. This shows that stealth dicing tech-nology is capable of narrower dicing streets which in turn will al-low a greater chip yield per wafer.

-25 -2065

60

55

50

45

40

35

30

25

-15 -10 -5 0

RADIUS (µm)

5 10 15 20 25

DE

PT

H (

µm)

Under 200200 to 500500 to 10001000 to 1500Over 1500

Temperature (°C)

Device area

Dicing street

Focal depth60 µm

Thermally affected area 15 µm

9

3.4 Checking thermal effects on device characteristicsEffects on characteristics of an actual device wafer were next veri-fied. A photosensor (photodiode) was used to verify device charac-teristics. In this verification method, two types of samples were fabricated with respective distances "d" of 10 µm and 150 µm from the device active area to the cut edge of the chip. The extent of thermal effects from the laser process during stealth dicing were then investigated. The photodiode’s dark current characteristics were investigated by blocking the photosensitive area, applying a reverse bias and meas-uring the leakage current.�THB (Temperature Humidity Bias) test

Humidity and temperature were set to 85 % / 85 °C for a 500 hour period.

�Temperature cycle (TC test)Performed for 100 cycles from -55 °C to 125 °C.

�PhotodiodePlastic package typeChip size: 2 mm × 2 mm, chip thickness: 100 µm

Figure 8 shows the THB test results. The dark current is about 0.1 nA at a Vr of 10 V or less. At a Vr higher than 10 V, the dark cur-rent rapidly increases and reaches a breakdown threshold. The dark currents were each 0.1 nA and 0.2 nA at d (distances) of 150 µm and 10 µm. The dark current only increased a mere 0.1 nA even if the distance from the chip cut edge to the active area was changed to 10 µm from 150 µm. The figure also shows there was virtually no change in the test results after 500 hours compared to the initial state.Figure 9 shows results from the TC test. Here also there was almost no change in the dark current value after 100 cycles of TC testing even compared to the initial state.These results prove that stealth dicing laser process is a technology that exerts no large effects on device service life and durability. This verifies the heat analysis simulation results in Figure 6 where the area heated to 200 °C or higher was limited to ±7 µm in radius, and also bears out the fact that there are no effects on device char-acteristics due to heat when the device is diced at a position 10 µm away from the active area. However, these tests do greatly affect the device structure, so the actual effects should be verified on each device that will be actually used.

TLASB0013EA

0.0110-13

10-12

10-11

10-10

10-9

10-8

10-7

10-6

0.1 1

BIAS VOLTAGE VR (V)

10 100

DA

RK

CU

RR

EN

T I D

(A

)

0.0110-13

10-12

10-11

10-10

10-9

10-8

10-7

10-6

0.1 1

BIAS VOLTAGE VR (V)

10 100

DA

RK

CU

RR

EN

T I D

(A

)

d=10 (µm)0 (H)500 (H)

d=150 (µm)0 (H)500 (H)

d=10 (µm)0 (cycle)100 (cycle)

d=150 (µm)0 (cycle)100 (cycle)

Figure 9: TC test results

Figure 8: THB test results

10

(a) Backside irradiation through tape (b) Tape expansion after removing the wafer from suction plate

Suction plate

Porous sheet

Silicon wafer Laser incident surface

Transparent tape

Lens

Laser incident surface

SiSi

Transparent tape

Expander

SD layer

3.5 Limitations when using stealth dicingDue to its operating principle, stealth dicing is subject to the fol-lowing limitations. The laser beam is usually irradiated from the device surface to machine it internally (front-side irradiation meth-od). However, it is difficult to guide the laser beam onto the front

surface of wafers when a light-blocking metallic film is formed there. In this case, the interior of those wafers is machined by irra-diating the laser beam from the back surface (backside irradiation method). Table 1 summarizes laser irradiation method according to the state of the device wafer.

When dicing an MEMS device wafer, some method is also needed to clamp the wafer if using the backside irradiation method. When clamping the device surface of a wafer containing this type of deli-cate structures to a vacuum chuck table (suction plate), porous sheets with good cushioning should be used to hold both sides of the device on the suction plate. Using a special dicing tape that al-lows the SD laser wavelength to easily transmit through will allow forming an SD layer inside the silicon through the tape while the

wafer backside is held by the tape.The remainder of the process is extremely simple. The wafer is re-moved from the suction plate while still mounted with the tape, and then tape is expanded to separate the wafer into chips in a simple and easy step. Figure 10 shows a concept view of this backside ir-radiation method.New advances being made in peripheral technologies will make stealth dicing the ideal solution for all types of devices.

Table 1: Laser irradiation methods per device structureLimitations when using front-side irradiation method

TEG/metallic film on dicing street

Protective film on dicing street

Street width

SOI wafers

These should not be present.

No problem with SiO2.

The SiN film thickness affects AF characteristics and processing. Consultation is required.

Since the SD laser beam has an incident angle, non-light-shielded area is required to guide the beam

according to wafer thickness.

BOX layer attenuates the laser beam power which causes a drop in the throughput time. Removing

the BOX layer may improve the throughput time.

Limitations when using backside irradiation method

Wafer clamping method

Backside grinding roughness

SOI wafer

Special SD dicing tape is attached to the wafer backside and stealth dicing performed through the

tape. However, if this is not possible, then the wafer can be clamped on a suction table and stealth

dicing performed from the wafer backside, and tape can be attached to the wafer on the suction plate.

#2000 or more

BOX layer attenuates the laser beam power which causes a drop in the processing time. Removing

this BOX layer may improve the throughput time.

TLASC0028EA

Figure 10: Concept view of backside irradiation through tape

11

Table 2: Calculated profit from a 10 µm street widthBlade dicing

Work size

Dicing street width

Chip size

Effective number of chips

Increased number of chips / wafer

Improved yield

Boosted profits

(24,000 pcs per year)

(calculated at 30 yen per chip)

0.08

3732

—

—

—

152

2 × 2

Stealth dicing Units

0.01

3996

264

107.1

190,080,000

mm

mm

mm

pcs

pcs

%

yen

Besides making MEMS devices more reliable, stealth dicing offers technology advantages with new added values that make business more profitable.

4.1 Benefits from a 10 µm kerf widthOne important technical advantage is the chip yield obtained from one wafer. Stealth dicing is a cleaving technology and therefore of-fers the overwhelming advantage of having absolutely no cutting area. Even if we consider the chip edge straightness during wafer separation, which is usually 2 µm to 3 µm, the dicing street width required by this technology is a maximum of ±5 µm. This means that the chip yield from a single wafer can be drastically increased. Table 2 shows the chip profit calculated by using a 10 µm wide

dicing street made possible by stealth dicing. Preconditions for this calculation are a wafer diameter of 152 mm, a chip size of 2 mm × 2 mm and a conventional blade dicing street width of 80 µm. The increased chip yield per wafer from shrinking the dicing street width was first found, and the profit then calculated assuming a cost of 30 yen per chip. Based on a monthly production of 2000 wafers and so an annual production of 24,000 wafers, an extra chip yield equivalent to 190 million yen can be obtained. In more realis-tic terms, the target production figure can be reached while using fewer wafers because of the increased chip yield per wafer. Con-verting using the above figures yields a figure of 1585 wafers an-nually. If irradiating the wafer with laser from the backside, then the laser beam spread should be taken into account. It is therefore necessary to find an area larger than 10 µm, where there is no metallic film that blocks the laser beam.

4. Stealth dicing boosts profits

4.2 Benefits when dicing irregular chip shapesStealth dicing is also effective on chips containing T sections or curves. Stealth dicing also allows improving the chip yield per wa-fer by arranging chips in zigzag layouts. It also proves effective, for example, on wafers such as TEG wafers where one mask is used to form as many different chip patterns as possible. Besides linear process, stealth dicing can also be used for dicing round shapes. Figure 11 shows forming of dicing patterns for different chip sizes. Because of the different 2 mm and 10 mm square chip sizes, the dicing lines on the edges of 10 mm square chips do not intersect and form a T shape. No SD layers are formed by turning off the laser beam at the tim-ing when the laser beam reaches each T section, allowing selective-ly the wafer in 2-dimensions. Controlling the laser beam to turn on and off in this way makes it possible to dice even non-consecutive device patterns. The on/off positions can be controlled with high precision, allowing accurate dicing within ±25 µm even at stage speeds up to 300 mm per second.

CH1

CH1-1 2 3 4

CH2

TLASC0034EA

Figure 11: Mixed pattern containing both 2 mm and 10 mm square chips

12

Photo 4 shows results from stealth dicing on a wafer with different chip sizes in Figure 11. Only 3 locations of the T section are shown because of the limited space available here. Photo 5 shows stealth dicing of free sizes on a silicon wafer. As can be seen here, stealth dicing can cut both curves and triangular shapes and the machined quality of the sliced cross section is the same as normal stealth dicing.

Stealth dicing also works on other materials besides silicon. Here are some example of dicing other materials which are currently un-der development.

5.1 Glass wafersGlass materials currently being used include quartz glass, borosili-cate glass (such as BK7), pyrex, and non-alkali glass, etc. Dicing of soft and hard glass materials is also under study. Glass wafers often be diced while laminated over a silicon wafer, so one method pro-posed for those cases forms an SD layer on each material by irradi-ating laser light for silicon material from the silicon substrate side, and laser light for glass material from the glass substrate side while simultaneously applying stress to separate the wafer into small chips. Photo 6 shows samples cut from an actual glass wafer by stealth dicing.These samples still have problems with the cutting quality. Name-ly, the edge straightness on the front surface where the chip edges were cut tends to weave back and forth about ±15 µm. Compared to silicon wafers where the cutting accuracy is about ±2 µm on both front and back surfaces, glass wafers still need improvements to increase their precision.

Photo 4: T-shape dicing example

Photo 5: Free size dicing

Photo 6 (a): Surface of glass chip cut from glass wafer

Photo 6 (b): Cross section of glass chip cut from glass wafer

5. Dicing materials other than silicon

CH1-1 CH1-2 CH1-3

50 µm

100 µm

13

5.2 Roadmap to future stealth dicing technologyWork on developing products from materials other than silicon is in progress according to the schedule below. MEMS devices made from wafers other than silicon are already under evaluation. De-mands are rising for products requiring stealth dicing of wafers made from glass and other compounds. Many problems still remain

unsolved for using stealth dicing with glass materials, so develop-ment work will require significant time. However, the pace of de-velopment work aimed at commercial products is accelerating. Ta-ble 3 shows a current developmental roadmap for new type SD en-gines.

Table 3: Developmental roadmap for SD engines

TLASC0029ED

* We plan to develop a new engine comprehensively improves your COO (Cost of Ownership) by reducing cycle time and cost.

~2012 2013 2014 2015 2016 2017 2018

Glass

Chemical strengthening glass

Crystalline

We plan to develop an engine compatible withnew materials and multiple materials.

Material

Cycle time is cut in half Cycle time is reduce toone third

Si

Sapphire

GaAs

SiC

Performance

GaN

LiTaO3

LiNbO3

Si + GlassProcessing with asingle engine unit

Si + GlassProcessing withtwo engine units

Ga2O3

Compact engine

Material

Performance

Cycle time is cut in half Cycle time is reduce toone third

Compact engine

Si + GlassProcessing with asingle engine unit

Si + GlassProcessing withtwo engine units

Ga2O3

Crystalline

GaN

GaAs

LiNbO3

LiTaO3

SiC

Chemical strengthening glass

Sapphire

Glass

Si

14

Figure 12: Scale showing how stealth dicing helps our environment

Mounting stealth dicing engines in equipment cuts their power con-sumption by 68 % (under fixed processing conditions). A main fea-ture of stealth dicing is that it is a completely dry process and so needs no pure water. Figuring in the savings from eliminating pure water production and waste water processing gives a drop in power consumption of 77 %. This helped earn stealth dicing the "Superior Energy-Saving Machines" award from the Japan Machinery Feder-ation (JMF) in February 2007. (Awarded to Tokyo Seimitsu Co., Ltd.).The graph in Figure 12 shows the degree of environmental or

green-friendly contribution rendered by stealth dicing.Let’s assume that 1000 blade dicing units were replaced with stealth dicing units, the reduction in carbon dioxide (CO2) would be equivalent to 17,000 tons or equivalent to the natural cleansing effect of 1 million 270,000 trees (cedar trees). Trial calculations al-so show the quantity of required ultrapure water could be slashed by 6 million tons.The tremendous impact in positive environmental effects from in-stalling stealth dicing engines in equipment is one marker that a semiconductor manufacturer is truly "Aware of energy and the en-vironment". So using stealth dicing in the wafer dicing process is a huge status mark for semiconductor manufacturers because it shows they are doing their share to cut harmful loads on the envi-ronment and stay green-friendly.

6. How green-friendly stealth dicing improves our environment

TLASC0036EA

Cuts CO2emissions by

Cuts ultrapure waterquantities by

25,000t

Estimated expanded useof stealth dicing units

�In one year using one stealth dicing unit

�So in 10 years using stealth dicing units

Cuts CO2emissions

by17.7t

Converting this to natural (cedar tree) cleansing

7.6 cars!�Hybrid cars *1

*1 Switching over an ordinary passenger car (gaso-line) to a hybrid car is estimated as reducing 2.34 tons of carbon dioxide emissions per year (at a driving distance of 19,500 kilometers annually, and fuel consumption of 60 % in 10.15 mode).

*2 Figure obtained by calculating the water usage by a single average household at 300 tons per year

Same savings obtained from 21 homes!

Same quantity used by

6,307t

Reducesultrapure

waterquantity by

�Ordinary home *2

CO2

Reductionin

UltrapureWaterFrom one

stealth dicing unit

9 million t

100 Units 300 Units 500 Units 1000 Units 1500 Units

5,000

0

10,000

15,000

20,000

25,000

0

6 million

4 million

2 million

10 million

8 million

Red

uctio

n in

CO

2 qu

antit

ies

(t)

Redu

ctio

n in

ultr

apur

e wat

er q

uant

ities

(t)

2019201920172017201420142009 20122009 2012

130,000130,000Equal toEqual to

treestrees

380,000380,000Equal toEqual to

treestrees

630,000Equal to

trees

1.27 million millionEqual toEqual to

treestrees

1.9 millionEqual to

trees

130,000Equal to

trees

380,000Equal to

trees

630,000Equal to

trees

1.27 millionEqual to

trees

1.9 millionEqual to

trees

7. Conclusion

15

MEMS devices such as microactuators, silicon microphones, RF MEMS, and optical MEMS devices are already being actively used in diverse fields. As the markets for these devices steadily expand, more technical innovations will be needed from a management per-spective to boost productivity and production efficiency as well as giving MEMS devices more functions and higher value. Stealth dicing was originally developed to solve the serious problems faced when trying to dice ultra-thin silicon devices such as semi-conductor memories with conventional technology. So when dicing comparatively thick silicon products such as MEMS devices, stealth dicing must form multiple SD layers along the wafer depth. However, forming these multiple SD (stealth dicing) layers takes time and reduces the product throughput. Future work will there-fore concentrate on developing machining processes and hardware for improving the throughput of thick silicon wafers as well as ex-panding the range of devices where stealth dicing can be used.

�USA: USP 6992026, 7396742, etc. (a total of 48 patents), and 62 patents pending�Japan: Patent Nos. 3408805, 3626442, 3761565, 3761567, 3761566, 3624909, 3670267, 3790254, 3822626, 3762409, 3867003, 3867107, 3867109,

3867110, 3867101, 3867102, 3867103, 3867100, 3867104, 3867105, 3869850, 3751970, 3867108, 3935187, 3935188, 3990710, 3935186, 3935189, 3990711, 4050534 (a total of 120 patents), and 70 patents pending

�Taiwan: Patent Nos. I250060, I270431, I289890, I278027, etc. (a total of 32 patents), and 54 patents pending�Europe (EC): Patent No. 1632997, etc. (a total of 28 patents), and 63 patents pending�Republic of Korea: Patent Nos. KR10-0667460, KR10-0715576, KR10-0749972, KR10-0766727, KR10-0781845, etc. (a total of 37 patents), and 49 patents

pending�China: A total of 62 patents, and 36 patents pending�Other Countries: Including patents pending in Thailand, Malaysia, India, Philippines, Singapore, and Israel etc.

�Patents (as of April 1, 2013)

Naoki Uchiyama, "Chapter 2: Fabrication of MEMS", Latest technologies in MEMS materials, Nov. 2007, CMC Publishing Co., Ltd. (published in Japanese)Naoki Uchiyama, "Chapter 9, section 7", 2008 MEMS technology outlook, separate volume of Electronic Journal, Electronic Journal, Inc. (published in Japanese)1) B. Richerzhagen, D. Perrottet, and Y. Kozuki, "Dicing of wafers by patented water-jet-guided laser: the total damage-free cut", Proc. of the 65th The Laser

Materials Processing Conference, 197-200 (2006)2) P. Chall, "ALSI's Low Power Multiple Beam Technology for High Throughput and Low Damage Wafer Dicing", Proc. of the 65th The Laser Materials Processing

Conference, 211-215 (2006)3) F. Fukuyo, K. Fukumitsu, N. Uchiyama, "Stealth Dicing Technology and Applications", Proc. 6th Int. Symp. on Laser Precision Microfabrication (2005)4) K. Fukumitsu, M. Kumagai, E. Ohmura, H. Morita, K. Atsumi, N. Uchiyama, "The Mechanism of Semiconductor Wafer Dicing by Stealth Dicing Technology",

Proc. 4th International Congress on Laser Advanced Materials Processing (2006)5) E. Ohmura, F. Fukuyo, K. Fukumitsu, and H. Morita, "Internal modified-layer formation mechanism into silicon with nano second laser", J. Achievement in Materials

and Manufacturing Engineering, 17, 381-384 (July-August 2006)6) Etsuji Ohmura, Masayoshi Kumagai, Kenshi Fukumitsu, Koji Kuno, Makoto Nakano, and Hideki Morita, "Internal Modification of Ultra Thin Sillicon Wafer by

Permeable Pulse Laser", Proceeding of the 8th International Symposium on Laser Precision Microfabrication (2007)7) Masayoshi Kumagai, Naoki Uchiyama, Etsuji Ohmura, Ryuji Sugiura, Kazuhiro Atsumi, Kenshi Fukumitsu, Advanced Dicing Technology for Semiconductor

Wafer-Stealth Dicing, Proc. 15th International Symposium on Semiconductor Manufacturing (2006)

�References

* The contents of this document are current as of MAR, 2014. The contents are subject to change without prior notice due to improvement.

SDE (Stealth Dicing) is a registered trademark of Hamamatsu Photonics.

TLAS9005E04MAR. 2014 IP

HAMAMATSU PHOTONICS K.K.HAMAMATSU PHOTONICS K.K., Electron Tube Division 314-5, Shimokanzo, Iwata City, Shizuoka Pref., 438-0193, Japan, Telephone: (81)539/62-5248, Fax: (81)539/62-2205