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Sayantan Sur, Intel State of HPC Middleware on Open Fabric Interfaces

State of HPC Middleware on Open Fabric Interfacesmug.mvapich.cse.ohio-state.edu/static/media/mug/... · 2017-08-17 · Netmod/CH4 Open MPI MTL/BTL Charm++ Sandia SHMEM GASNet Clang

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Page 1: State of HPC Middleware on Open Fabric Interfacesmug.mvapich.cse.ohio-state.edu/static/media/mug/... · 2017-08-17 · Netmod/CH4 Open MPI MTL/BTL Charm++ Sandia SHMEM GASNet Clang

Sayantan Sur, Intel

State of HPC Middleware on Open Fabric Interfaces

Page 2: State of HPC Middleware on Open Fabric Interfacesmug.mvapich.cse.ohio-state.edu/static/media/mug/... · 2017-08-17 · Netmod/CH4 Open MPI MTL/BTL Charm++ Sandia SHMEM GASNet Clang

Intel® Omni-Path Architecture

2

Legal Notices and DisclaimersINFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND/OR USE OF INTEL PRODUCTS, INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT, OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life-saving, life-sustaining, critical control or safety systems, or in nuclear facility applications.

Intel products may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.

Intel may make changes to dates, specifications, product descriptions, and plans referenced in this document at any time, without notice.

This document may contain information on products in the design phase of development. The information herein is subject to change without notice. Do not finalize a design with this information.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

Intel Corporation or its subsidiaries in the United States and other countries may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.

Wireless connectivity and some features may require you to purchase additional software, services or external hardware.

Performance tests and ratings are measured using specific computer systems and/or components and reflect the approximate performance of Intel products as measured by those tests. Any difference in system hardware or software design or configuration may affect actual performance. Buyers should consult other sources of information to evaluate the performance of systems or components they are considering purchasing. For more information on performance tests and on the performance of Intel products, visit Intel Performance Benchmark Limitations

Intel, the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.

Other names and brands may be claimed as the property of others.

Copyright © 2017 Intel Corporation. All rights reserved.

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Intel® Omni-Path Architecture

3

Legal Disclaimer & Optimization Notice

INFORMATION IN THIS DOCUMENT IS PROVIDED “AS IS”. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO THIS INFORMATION INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

Software and workloads used in performance tests may have been optimized for performance only on Intel microprocessors. Performance tests, such as SYSmark and MobileMark, are measured using specific computer systems, components, software, operations and functions. Any change to any of those factors may cause the results to vary. You should consult other information and performance tests to assist you in fully evaluating your contemplated purchases, including the performance of that product when combined with other products.

Copyright© 2017, Intel Corporation. All rights reserved. Intel, the Intel logo, Atom, Xeon, Xeon Phi, Core, VTune, and Cilk are trademarks of Intel Corporation in the U.S. and other countries.

Optimization NoticeIntel’s compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804

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Intel® Omni-Path Architecture

Open Fabric Interfaces

4

OptimizedSWpathtoHW•Minimizecacheandmemoryfootprint•Reduceinstructioncount•Minimizememoryaccesses

ScalableImplementation

Agnostic

Softwareinterfacesalignedwithuserrequirements•Carefulrequirementanalysis

Inclusivedevelopmenteffort•AppandHWdevelopers

Goodimpedancematchwithmultiplefabrichardware•InfiniBand,iWarp,RoCE,rawEthernet,UDPoffload,Omni-Path,GNI,BGQ,…

OpenSource User-Centric

Open Fabric Interfaces

User-centric interfaces lead to innovation and adoption

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Intel® Omni-Path Architecture

OFI HPC Community

5

libfabric

Intel®MPILibrary

MPICHNetmod/CH4

OpenMPIMTL/BTL Charm++ Sandia

SHMEMGASNet ClangUPC

GlobalArrays

libfabric EnabledMiddleware

ControlServices CommunicationServices

CompletionServices

DataTransferServices

Discovery

fi_info

ConnectionManagement

AddressVectors

EventQueues

EventCounters

MessageQueue

TagMatching

RMA

Atomics

SocketsTCP,UDP Verbs Cisco

usNICIntel

OPAPSMCrayGNI Mellanox IBMBlue

GeneA3CubeRONNIE

* **

* *®

*

experimental

Sampling of HPC Middleware already targeting OFI

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Intel® Omni-Path Architecture

OFI Software development strategies

6

FabricServices

User

OFI

Provider

User

OFI

ProviderProvideroptimizesfor

OFIfeatures

Commonoptimizationforallapps/providers

ClientusesOFIfeatures

User

OFI

Provider

Clientoptimizesbasedonsupportedfeatures

Providersupportslow-levelfeaturesonly

Linux, FreeBSD, OS X, Windows

TCP and UDP development support

One size does not fit all

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Intel® Omni-Path Architecture

Libfabric on Intel® OPA

7

• Libfabric PSM2 provider uses the public PSM2 API

• Semantics matches with that of compute middleware such as MPI

• PSM2 EP maps to HW context, Each EP associated with matched queue

• Regular Endpoints share a single HW context

• Scalable Endpoints provide independent HW contexts

• PSM2 library uses PIO/Eager for small message andDMA/Expected for Bandwidth for large messages

• Current focus is full OFI functionality

• Performance optimizations are possible to reduce call overheads, and provide better semantic mapping of OFI directly to HFI

Libfabric Framework

PSM2 Provider

Fabric Interfaces

Kernel Interfaces

HFI

PSM2 Library

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Intel® Omni-Path Architecture

Intel® OPA/PSM Provider Performance

8

Performance is comparable for most messages• 6.7% overhead for 64B latency, and 6.1% overhead for 16B bandwidth• Optimizations are ongoing

Intel Xeon E5-2697 (Ivy Bridge) 2.6GHz; Intel Omni-Path; RHEL 7.3; libfabric 1.5.0 alpha; IFS 10.5.0.0.115

0

0.2

0.4

0.6

0.8

1

1.21 2 4 8 16 32 64 128

256

512

1K 2K 4K 8K 16K

32K

64K

128K

256K

512K 1M 2M 4M

Ratio

Message Size (Bytes)

Relative Latency (Netpipe)OFI/PSM2 PSM2

0

0.2

0.4

0.6

0.8

1

1.2

1 2 4 8 16 32 64 128

256

512

1K 2K 4K 8K 16K

32K

64K

128K

256K

512K 1M 2M 4M

Ratio

Message Size (Bytes)

Relative Bandwidth (Netpipe)OFI/PSM2 PSM2

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Intel® Omni-Path Architecture

MPI/OFI Design Principles

9

Directly map MPI constructs to OFI features as much as possibleFocus on optimizing communication calls

• Avoid branch, function calls, cache misses, memory allocation

MPI OFI

MPI_Send, MPI_Recv, etc. fi_tsend, fi_trecv

Window Memory region (fi_mr(3))

Comm. calls(MPI_Put, MPI_Get, etc…)

fi_write, fi_read, … (fi_rma(3))

Atomic comm. calls(MPI_Accumulate, etc…)

fi_atomic, … (fi_atomic(3))

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Intel® Omni-Path Architecture

MPICH-OFI

10

Open-source implementation based on MPICH• Uses the new CH4 infrastructure

• Co-designed with MPICH community

• Targets existing and new fabrics via Open Fabrics Interface (OFI)• Ethernet/sockets, Intel® Omni-Path, Cray Aries*, IBM BG/Q*,

InfiniBand*• OFI is intended as the default communication interface for future

versions MPICH

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Intel® Omni-Path Architecture

Improving on MPICH/CH3 Overheads

11

CH4 significantly reduces MPI instructions

MPICH/CH4: - 35 instructions with static build- 85 instructions with dynamic build- Data collected using GCC v5.2.1on Xeon E5-2697 (Haswell)

0 500 1000 1500

MPICH/CH4/OFI/PSM2

MPICH/CH3/OFI/PSM2

MPI_Send Instruction Counts (dynamic link)

MPI OFI/PSM2

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Intel® Omni-Path Architecture

MPICH Performance Comparison (KNL + OPA)

12

Around 20% reduction in latency, gains in bandwidth for small messages

Intel Xeon Phi 7250 (Knights Landing) 1.4GHz; Intel Omni-Path; RHEL 7.3; GCC v5.3.1; OSU Micro-benchmarks 5.3

0

0.2

0.4

0.6

0.8

1

1.2

0 1 2 4 8 16 32 64

Ratio

MessageSize(Bytes)

RelativeLatency(OSUMicrobenchmarks)CH4/OFI/PSM2 CH3/OFI/PSM2

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1 2 4 8 16 32 64 128

Ratio

MessageSize(Bytes)

RelativeBandwidth(OSUMicrobenchmarks)CH4/OFI/PSM2 CH3/OFI/PSM2

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Intel® Omni-Path Architecture

OpenSHMEM mapping on OFI

13

ScalableEndpoint

Reliableconnectionlessendpointswithlogicaladdressing

Scalable,memoryusagemodel

ReuseLocalBuffer

Immediatelocalcompletion:“fi_inject”

Acceleratedsmallmessagepathway PGASImplementation

HardwareFabric

MinimizeInstructions

FabricDirect NodeA NodeBsync

EfficientRemoteCompletionforPut/Get

countersforlightweightremotecompletion

VAcommunicationstyle,exposefullVArange

NodeA NodeB

RichAtomicSet

FullSHMEMconvergewithfineAPIgranularity

Design and implementation presented at OpenSHMEMworkshop 2016

https://rd.springer.com/chapter/10.1007/978-3-319-50995-2_7

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Intel® Omni-Path Architecture

SHMEM/OFI Test Environment

14

§ All tests run on CORI at NERSC§ Cray* SHMEM

• Cray* Aries, Dragonfly* topology• CLE (Cray* Linux*), SLURM*• DMAPP•Designed for PGAS•Optimized for small messages

§Sandia* OpenSHMEM / libfabric• uGNI

• Designed for MPI and PGAS• Optimized for large messages

DMAPP

CraySHMEM

AriesInterconnect

uGNI

libfabric

OpenSHMEM

OFI

vs

1630nodesonCray*XC40(Cori)

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Intel® Omni-Path Architecture

SHMEM Performance on Cray* XC40

15

Put – up to 61% improvement

Get – within 2%

Blocking Get/Put B/W

Testsdocumentperformanceofcomponentsonaparticulartest,inspecificsystems.Differencesinhardware,software,orconfigurationwillaffectactualperformance.Consultothersourcesofinformationtoevaluateperformanceasyouconsideryourpurchase. Formorecompleteinformationabout performanceandbenchmarkresults,visithttp://www.intel.com/performance.Configuration:CORI@NERSC

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Intel® Omni-Path Architecture

State of GASNet Support

16

Currently GASNet/OFI supports Intel® True Scale Architecture, Intel® Omni-Path Architecture, and TCP/IP.§ Experimental support for Cray* XC systems via GNI provider.

§ Blue Gene/Q provider supports the implementations requirements, but has not been tested yet.

Provider Requirements to support GASNet§ FI_EP_RDM

§ (Preferred) FI_MR_SCALABLE, FI_MR_BASIC

§ FI_MSG, FI_RMA

§ FI_MULTI_RECV

Support on platforms like verbs may be easily achieved through utility providers

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Intel® Omni-Path Architecture

GASNet Performance Comparisons

17

1248

163264

128256512

1024204840968192

16384

64 128 256 512 1K 2K 4K 8K 16K 32K 64K 128K256K512K 1M 2M

Ban

dwid

th (M

B/S

)

Payload Size (bytes)

ofi-conduit vs psm-conduit blocking put bandwidth

GASNet/OFI/PSM2

GASNET/PSM2

1

2

4

8

16

32

64

128

256

64 128 256 512 1K 2K 4K 8K 16K 32K 64K 128K256K512K 1M 2M

Late

ncy

(us)

Payload size (bytes)

ofi-conduit vs psm-conduit put latency

GASNET/OFI/PSM2

GASNET/PSM2

Testsdocumentperformanceofcomponentsonaparticulartest,inspecificsystems.Differencesinhardware,software,orconfigurationwillaffectactualperformance.Consultothersourcesofinformationtoevaluateperformanceasyouconsideryourpurchase. Formorecompleteinformationabout performanceandbenchmarkresults,visithttp://www.intel.com/performance.Configuration:Intel(R)Xeon(TM)[email protected],RHEL7.3,libfabric1.4.0,GASNet1.28.2,libpsm2-10.2.58-1

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Intel® Omni-Path Architecture

GASNet Performance Discussion

18

At large message sizes, performance is more or less the sameFor small message sizes there is a disparityReason: native psm-conduit is using different completion mechanism

Callback function executed when remote completion is finished§ Pros: Better latency, reduces overhead related to completion queue processing

§ Cons: Does not return error/success information

Native OPA provider could map better, as opposed to through PSM2

psm2_error_tpsm2_am_request_short(psm2_epaddr_t epaddr, psm2_handler_t handler,

psm2_amarg_t *args, int nargs, void *src,size_t len, int flags,psm2_am_completion_fn_t completion_fn,void *completion_ctxt);

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Intel® Omni-Path Architecture

Charm++ on Intel® OPA

19

libfabric

Charm++

OFILRTS

OPAInterconnect

PSM2

Charm++

MPILRTS

IntelMPI

vs

§ New OFI LRTS implementation• Removes MPI overhead• Uses FI_TAGGED and FI_RMA APIs with

FI_EP_RDM endpoint• Two data transfer modes

• Small/medium messages: uses pre-posted buffers on receiver’s side to avoid usage of unexpected path

• Large messages: use RMA Read• Future work: multi-threaded use cases can

benefit from scalable endpoints

OFINetmod

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Intel® Omni-Path Architecture

Charm++ Performance Comparisons

20

Around 30% reduction in latency for small messagesIntel(R) Xeon(R) CPU E5-2695 v3 @ 2.30GHz; data from PSC Bridges, reported by Nitin Bhat of UIUC

Performance increased by 22% at 96 nodes

Intel(R) Xeon Phi(R) 7250F (Knights Landing); IFS 10.2; libfabric 1.4.2; Intel MPI 2017.3.196

0

0.2

0.4

0.6

0.8

1

1.2

Ratio

Message Size (Bytes)

Relative Latency (pingpong)Charm++/OFI/PSM2 Charm++/MPI/PSM2

0

0.2

0.4

0.6

0.8

1

1.2

1.4

8 16 32 48 96

Ratio

Number of Nodes

Relative speedup for NAMD APOA1 Charm++/OFI/PSM2 Charm++/MPI/PSM2

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Intel® Omni-Path Architecture

Global Arrays

21

Global Arrays

Communication runtime for exascale (ComEx)

Scalable Protocol Layer

OFI MPI others

§ New OFI ComEx implementation• Removes MPI overhead• Uses FI_TAGGED and FI_RMA with

FI_EP_RDM endpoint, FI_MR_SCALABLE• Put/Get uses the RMA APIs• Lock/Unlock uses the tagged and atomics• Accumulate/RMW use the atomics• If provider doesn’t support atomics, then

implement atomics over messages• OPA provider emulates atomics internally

Currently GA is single-threaded. There is effort from Jeff Hammond to add multi-threading support. So there will be the same plans/issues as for Charm++/OFI:• utilize scalable endpoints API• improve intra-node communications

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Intel® Omni-Path Architecture

ComEx performance over OFI – Put and Get

22

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

Ratio

Message Size (Bytes)

Relative Put Latency

ComEx/OFI/PSM2 ComEx/MPI

0

0.2

0.4

0.6

0.8

1

1.2

16 32 64 128 256 512 1K 2K 4K 8K 16K 32K 64K 128K256K512K 1M

Ratio

Message Size (Bytes)

Relative Get Latency

ComEx/OFI/PSM2 ComEx/MPI

Significant improvements in both Get and Put latencySome tuning needed for a few data points (work in early stages)

Intel(R) Xeon Phi(R) 7250F@ 1.4GHz; Global Arrays 5.6.2; libfabric 1.5.0; Intel MPI 2017.3.196

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Intel® Omni-Path Architecture

ComEx performance over OFI – AMO and NWCHEM

23

0

0.2

0.4

0.6

0.8

1

1.2

Rmw-Fetch and Add Long Test

Rmw-Fetch and Add Test Rmw-Swap Long Test Rmw-Swap Test

Ratio

Message Size (Bytes)

Relative AMO Latency

ComEx/OFI/PSM2 ComEx/MPI

0

20

40

60

80

100

120

Total times Task times

Tim

e (s

econ

ds)

Total Time spent for NWChem Cytosine

ComEx/OFI ComEx/MPI

More than 50% improvement in AMO opsMore than 10% improvement at NWChem level with Cytosine

Intel(R) Xeon Phi(R) 7250F@ 1.4GHz; Global Arrays 5.6.2; libfabric 1.5.0; Intel MPI 2017.3.196

8 nodes, 68 ranks per nodeTotal 4352 ranks

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Intel® Omni-Path Architecture Intel ConfidentialIntel Confidential

Summary

Open Fabrics Interface (OFI) provides a rich set of APIs that are suited for applications and drawn from semantic requirements, not underlying hardware

• Allows portability to different fabrics without needing extensive rework

• Allows developers to focus on architecture of middleware, which can lead to benefits (like with MPICH/CH4, SHMEM)

Several prominent HPC middleware like MPI, PGAS, Charm++, GA are already working well on OFI, with application level gainsNew semantics like NVM and persistence support are being added to OFI

Never been a better time to get involved: http://libfabric.org/

24

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