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ECM2118 Lecture 6

Latches

Introduction

There are two types of latches, the S-R latch and the D-latch. We discuss these two

latches in this chapter.

The S-R latch

The S-R latch has two input terminals, S (for set) and R (for reset), and two output

terminals Q and Q . Q is always he complement of Q .

The symbol for an S-R latch is shown below:

Q

Q R

S

Figure 1: Symbol for an S-R latch

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And the truth table for the S-R latch is as shown:

Table 1: Truth Table for the S-R latch

Latch Inputs Present Latch

Output

Next Latch

output

Latch Behaviour

S R nQ 1+nQ

0 0 0 0

No change in State 0 0 1 1

1 0 0 1

Set Operation 1 0 1 1

0 1 0 0

Reset operation 0 1 1 0

1 1 0 X

Indeterminate operation 1 1 1 X

Explanation of the Truth Table

In the table nQ represents the present state of the Q output and 1+nQ represents the next

state of the Q output after the input terminals have been taken HIGH or LOW.

1. When both S and R are LOW the logical states of the output terminal do not

change. This is shown by nn QQ =+1 .

2. When S=1 and R=0 the logical state of the output Q will become 1 no matter

what its value was before. This is known as the set operation.

3. If S=0 and R=1 the logical state of the output Q will become 0 no matter what its

value was before. This is known as the reset operation.

4. If both S and R are 1 the operation of the latch is unpredictable. This

combination of input states should not be allowed to occur.

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Implementation of the S-R latch using NOR gates:

The operation has to be analyzed with the 4 possible input combinations together with

the 2 possible previous states.

No Change Condition: Inputs S = 0 and R = 0:

A: Assuming the Initial Condition Q = 1 and Q = 0:

The output Q after input is applied would be: Q = (R + Q )' = 1 and Q = (S + Q)' = 0. B: Assuming the Initial Condition Q = 0 and Q = 1:

The output Q after the input applied would be:

Q = (R + Q )' = 0 and Q = (S + Q)' = 1.

Conclusion: Therefore it is clear that when both S and R inputs are LOW, the output

is retained as before the application of inputs. (i.e. there is no state change).

S

R

Q

Q

Figure 2: Nor gate implementation of the S-R latch

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Set Operation: S = 1 and R = 0:

A: Assuming the Initial Condition Q = 1 and Q = 0:

The output Q after input is applied would be:

Q = (R + Q )' = 1 and Q = (S + Q)' = 0.

B:Assuming the Initial Condition Q = 0 and Q = 1:

The output Q after the input applied would be:

Q = (R + Q )' = 1 and Q = (S + Q)' = 0.

So in simple words when S is HIGH and R is LOW, output Q is HIGH.

S = 1

R = 0

1=Q

0=Q

Figure 3: Set Operation: S =1 and R = 0

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Reset Operation: S = 0 and R = 1:

A: Assuming the Initial Condition Q = 1 and Q = 0:

The output Q after input is applied would be:

Q = (R + Q )' = 0 and Q = (S + Q)' = 1.

B:Assuming the Initial Condition Q = 0 and Q = 1:

The output Q after the input applied would be:

Q = (R + Q )' = 0 and Q = (S + Q)' = 1.

So in simple words when S is LOW and R is HIGH, output Q is LOW.

S = 0

R = 1

0=Q

1=Q

Figure 4: Reset Operation: S =0 and R = 1

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Indeterminate operation: S = 1 and R = 1:

A: Assuming the Initial Condition Q = 1 and Q = 0:

The output Q after input is applied would be:

Q = (R + Q )' = 0 and Q = (S + Q)' = 0.

B:Assuming the Initial Condition Q = 0 and Q = 1:

The output Q after the input applied would be:

Q = (R + Q )' = 0 and Q = (S + Q)' = 0.

No matter what state Q and Q are in, application of 1 at input of NOR gate always

results in 0 at output of NOR gate, which results in both Q and Q set to LOW (i.e. Q

= Q ). LOW in both the outputs basically is wrong, so this case is invalid.

S = 1

R = 1

?=Q

?=Q

Figure 5: Indeterminate Operation: S =1 and R = 1

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Implementation of the S-R latch using NAND gates:

This circuit is a basic NAND latch. The inputs are generally designated S and R for

"Set" and "Reset" respectively. This is because the NAND inputs must normally be

logic 1 to avoid affecting the latching action, the inputs are considered to be inverted

in this circuit.

Table 2: NAND S-R Latch Truth Table

Latch Inputs

Present Latch Output

Next Latch output

Latch Behaviour

S R nQ 1+nQ

0 0 0 X Indeterminate operation

0 0 1 X

0 1 0 1 Set Operation

0 1 1 1

1 0 0 0 Reset operation

1 0 1 0

1 1 0 0 No change in State (Keep State)

1 1 1 1

Q

Q

R

S

Figure 6: Nand gate implementation of the S-R latch

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Clocked S-R latches The simple S-R latches above respond to changes as soon as they occur. This may cause the

latch to respond to unwanted signal changes or noise, thereby giving rise to glitches in the

circuit.

To avoid this we introduce a control signal which is called the clock signal. This is a

repetitive square wave signal. When the clock signal is HIGH, the latch can be allowed to

accept inputs, and when the clock signal is LOW the latch does not accept any signal changes.

The clocked S-R NOR latch

Control signal C is used to gate the input S and R to the RS Latch. When C is HIGH,

both the AND gates act as buffers and thus R and S appears at the RS latch input and

it functions like a normal RS latch. When C is LOW, it drives LOW to both inputs of

RS latch. As we saw in previous page, when both inputs of a NOR latch are low,

values are retained (i.e. the output does not change).

S

R

Q

Q

C

Figure 7: Clocked S-R NOR latch

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The clocked S-R NAND latch

By adding a pair of NAND gates to the input circuits of the RS latch, we accomplish

two goals: normal rather than inverted inputs, and a third input common to both gates

which we can use to synchronize this circuit with others of its kind.

The clocked RS latch circuit is very similar in operation to the basic latch. The S and

R inputs are normally at logic 0, and must be changed to logic 1 to change the state of

the latch. The NAND gates ensure that the output can only change state while the

clock signal C is logic 1. When C is logic 0, the S and R inputs will have no effect.

Q

Q

NAND Gate

S

R

C

Figure 8: Clocked S-R NAND latch

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The D Latch

A D latch has one input, labelled D, one enable or clock input, and one output Q. The

logical state of the D input is transferred to the output whenever the clock input is

HIGH. The Q output will follow any changes in the logical state of the D input as

long as the clock input remains HIGH. When the clock input goes LOW the logical

state of the D input at that moment will be retained at the Q output no matter what

changes occur at the D input. When the clock input goes HIGH again the Q output

will once again follow any changes in the logical state of the D input. A D latch is

therefore said to be transparent when the clock is HIGH.

The symbol for a D latch is shown below:

and the truth table is as shown:

Table 3: D Latch Truth Table

D 1+nQ

0 0

1 1

Q

Q

D

Clk

Figure 9: Symbol for a D latch

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Construction of D-Latches

A D latch can be constructed from a clocked S-R flip flop by adding an inverter as shown:

For a clocked S-R NOR latch the D latch is obtained as shown:

S

R

Q

Q

Clk

D

Figure 11: Adding an inverter to a NOR S-R latch to get a D latch

Q

Q

Clk

D

R

S

Figure 10: Adding an inverter to an S-R latch to get a D latch