Spring04

13 COVER STORY —ELIMINATING BURIED YIELD KILLERS

23 TAKING CONTROL OF THE COPPER

PROCESS AT 65 NM

32 THE CRYSTAL GROWTHAND RETICLE

DEGRADATION EXPOSÉ

13 COVER STORY —ELIMINATING BURIED YIELD KILLERS

23 TAKING CONTROL OF THE COPPER

PROCESS AT 65 NM

32 THE CRYSTAL GROWTH AND RETICLE

DEGRADATION EXPOSÉ

Yield ManagementYield ManagementYield Acceleration Strategies for the Semiconductor Industry

S O L U T I O N SYield Acceleration Strategies for the Semiconductor Industry

VOLUME 6 ISSUE 1 SPRING 2004 $5.00 US

S O L U T I O N S

90 nm: How to SecureYour Future90 nm: How to SecureYour Future

Spring 2004 Yield Management Solutions2

C O N T E N T S

C o v e r S t o r y

13 Eliminating Buried Yield Killers

It’s here. A new weapon to monitor and eliminate buried electrical defects. From development through volume production, electrical line monitoring shows great results.

Cover image by Terry Rieckhoff, KLA-Tencor

6 Taking Sides to Optimize Wafer SurfaceUniformity

Identify yield relevant defects on the waferbackside without having to sacrifice wafers.

23 Control of the Copper Process

You thought the challenges at 130 nm werehard? 65 nm changes all the rules.

32 The Crystal Growth and Reticle DegradationExposé

Molecular contaminants on reticles can resultin catastrophic yield loss.

39 Implementation of High Resolution ReticleInspection in Wafer Fabs

Streamline reticle qualification and improve the feedback loop with your mask shop.

45 Techniques for Evaluating Reticle InspectionEquipment for 130 nm Lithography and Beyond

Questions everyone should ask in selecting reticle defect inspection equipment for waferlithography applications.

50 Seeing Through the Haze

Evaluate process performance with new surface information.

55 Simulating the Impact of Reticle Defects

Don’t wait till it’s too late. Take advantage of aquick and accurate solution to ensure betterphotomask quality.

Spring 2004 www.kla-tencor.com/magazine 3

S P R I N G 2 0 0 4

S e c t i o n s

4 Editorial: New Solutions for NewChallenges: Going Beyond 90 nm

11 Spotlight on Lithography

22 Got a Litho Question? Ask the Experts

44 Yield Management Seminar Series

61 Product Awards

P r o d u c t N e w s

62 PROLITH v8.0 Advanced Lithography Simulation Software

63 MetriX 100High Precision Metal Film Metrology

MX 4.0New Haze Analysis Software on Surfscan SP1

Yield Management Solutions is published by KLA-Tencor Corporation.

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©2004 KLA-Tencor Corporation. All rights reserved. Material may not be

reproduced without permission from KLA-Tencor Corporation.

Products in this document are identified by trademarks of their respective

companies or organizations.

34 538

The Fine Line Between Design RuleViolations and reticle Defects

Identifying process window marginalitiesof reticle designs.

Novel, At-design-rule, Via-to-metalOverlay Metrology

New grating-style technology demonstratessuperior perormance over conventionalbox-in-box targets.

WEB Exclusives

www.kla-tencor.com/magazine


EditorialS E C T I O N S

A recent article in the Financial Times on the growthof cellular phone usage in Japan featured a photographof hundreds of Japanese teenagers flashing their cellularphones to capture an image of their prime ministerdelivering an impassioned speech. For these youngfans, the latest in digital technology offered the chanceto hoard their own slice of history, instantly.

Take a look around you, and it quickly becomes evi-dent that digital consumer electronics have become anintegral part of our everyday lives. From digital cam-eras and cellular phones to personal digital assistants(PDAs) and high-definition televisions (HDTVs), digi-tal consumer products are making the world morewireless and connected.

New applications for digital consumer electronics arisenearly every day to address new needs. Whoever wouldhave thought the need or desire to use their cellularphone as a camera to take, transmit and receive pic-tures, like the Japanese teenagers mentioned above?Yet, markets for such applications are emerging, andwith digital consumer electronics becoming increasing-ly indispensable, you need not stretch your imaginationtoo far to see a future where color displays are embed-ded in appliances and furniture; where freeways arecontrolled by vast electronic networks to ensuresmooth traffic flow and minimize accidents; wherefuture generations of cars will probably have drive-by-wire systems not unlike Boeing 777s; and, where an

entire forensic laboratory can be built onto amicrochip. In the more immediate future, Intel envi-sions a seamless, wireless home network that can han-dle music, photos, and video content available anytime,anywhere and on any device in the home.

In this increasingly digitized world, having an elec-tronic device that is anything less than 100 percentreliable is not an option. The financial and personalloss caused by the widespread occurrence of devicesthat are unreliable or fail altogether in the field wouldbe truly grim. However, while the reality of a fullyconnected world is still years away, the prospects ofpoor device reliability and product failure in the fieldare here today. As the semiconductor industry rampsto 90-nm production and engages in process develop-ment at the 65-nm node, reliability-related problemssuch as micro voids, electro-migration, stress migra-tion, de-lamination and cracking, can no longer becontained in development, and are arising at randomduring production. The introduction of dozens of newand exotic materials at these design rules to augmentdevice performance and speed, such as silicon-on-insu-lator (SOI), strained silicon, atomic layer deposition(ALD) barriers and new metal compounds, presenttheir own unique process integration issues that ulti-mately can further impair reliability. And while theseissues will not cause flying commuter vehicles to crashinto the Earth today, they present very real obstacles torealizing the dream of a truly interconnected world.

New Solutions for New Challenges:

S O L U T I O N SYield Management

CORPORATE HEADQUARTERSKLA-Tencor Corporation160 Rio RoblesSan Jose, California 95134408.875.3000

INTERNATIONAL OFFICESKLA-Tencor France SARLEvry Cedex, France33 16 936 6969

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EDITOR-IN-CHIEFUma Subramaniam

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PRODUCTION MANAGERCarlos Hueso

DESIGN CONSULTANTTerry Rieckhoff Mike Garnica

CIRCULATION EDITORNancy Williams

KLA-Tencor Worldwide

Yield ManagementS O L U T I O N S

This latest issue of Yield Management Solutions, explores several radically newprocess control methodologies that are being implemented to help chipmakersaddress these reliability issues. Our cover story, Eliminating Buried Yield Killers(page 13), presents a compelling argument for implementing e-beam inspection indevelopment, ramp, and production to mitigate new sources of reliability problems.Taking Control of the Copper Process (page 23) explores new metrology techniques—including inline copper interconnect metrology—to minimize the impact of processvariations on long-term device reliability and short-term yields.

So, while the technology visionaries out there are dreaming up a new world order,your fortune cookie indicates that there are new process control solutions you can takeadvantage of to bring the latest generation gizmos and gadgets to market in time tomeet the demands of tech-hungry consumers.

Happy New Year!

Uma SubramaniamEditor-in-chief


Going beyond 90 nm


IntroductionIn contrast to bare wafer inspection strategies,semiconductor manufacturers are still in theearly learning stages of implementing back-side inspections of silicon wafers. Backsidedefects in the form of particles or topographyare highly relevant to photolithography pro-cessing. Particularly in 300 mm photolitho-graphy, where double-sided polished wafersare used, such defects reduce surface unifor-mity and cause undesired effects on theexposure chuck. The two most commoneffects are focus spots and vacuum failures.For critical lithography layers with smallprocess windows, focus spots have a directimpact on yield. Vacuum failures result intool downtime, which impairs manufacturingefficiency. Moreover, backside contaminationoften results in time-consuming cleaning

procedures of the exposure tool chuck. Experience indi-cates that 200 mm and 300 mm manufacturing sharelargely the same backside issues.

The effects that backside defects can have on the devicesbuilt on the frontside of the wafer are largely known,but have not been systematically characterized. This ismainly because traditional backside inspection methodsrequire wafers to be manually turned upside down witha vacuum wand to conduct a thorough inspection,which damages the devices on the frontside and couldcontaminate the inspection tool.

Working with KLA-Tencor, Infineon Semiconductorinvestigated the effectiveness of a new inspectionmethodology for identifying yield-relevant defects onthe wafer backside in an automated and non-destructiveway at its 200 mm and 300 mm fabs in Dresden.

Taking Sides to Optimize Wafer Surface Uniformity

Backside Inspection Applications In Lithography

Kay Lederer, Matthias Scholze, Ulrich Strohbach, Infineon Technologies Andreas Wocko, Thomas Reuter, Angela Schoenauer, KLA-Tencor Corporation

As the semiconductor industry ramps to sub-130 nm production capacity,1 the need for optimal uniformity across the wafersurface becomes a very important topic in lithography. Due to the tightening of depth of focus requirements the process windowrequired to be able to print the required structure leaves little or no room for any localized deviation in the wafer uniformity.For 300 mm semiconductor device manufacturing, this resulted in the use of double-side polished, sometimes called “superflat” wafers.

This paper will discuss methods to identify yield relevant defects on the wafer backside without having to sacrifice wafers.It is based on recent studies carried out at both Infineon Semiconductor 200 and 300 mm fabs in Dresden to characterizethe need and the effectiveness of wafer backside defect inspection using the backside inspection module (BSIM) on theSurfscan SP1DLS.

LithographyD E F E C T I N S P E C T I O N


MethodologyThe first step in implementing backside inspection isto analyze the surface quality of the wafer backside anddetermine the sensitivity required for capturing defectsof interest (process tool fingerprints). We did this bydepositing polystyrene latex spheres onto the backsideof a test wafer and adjusting the recipe parameters toachieve at least a 3:1 signal-to-noise ratio.1

For our first experiment, we investigated the backsidequality of 300 mm double-sided polished process wafersbefore and after lithography. The backsides were inspectedusing a KLA-Tencor Surfscan SP1 unpatterned inspec-tion system with a new backside inspection module(BSIM) option. BSIM employs edge-only automatedwafer handling throughout the measurement process,so it enables product wafers to be flipped and measuredwithout destroying the un-scanned side. Double-sidedpolished wafers can be treated the same as bare siliconwafers, with the exception that they have a higher defectthreshold value. This value is dependent upon the desiredresolution for detecting tool fingerprints (Figure 1) anddata management limitations. For this study, the opti-cal configuration used on the SP1 included the obliqueincidence mode and P-U-U polarizations. Defectthresholds were between 0.5 µm and 1.0 µm.

The goal of our second study was to identify the rootcause of systematic focus spots detected on 200 mmpatterned wafers at various stages in the front end of themanufacturing process. The frontsides of the productwafers were measured inline on a KLA-Tencor AIT IIdouble darkfield illumination system. Defect reviewand characterization were carried out on a CRS confocalmicroscope. Offline data analysis, including correlationbetween front- and backside defects, was done usingKlarity Defect software. The backsides were measuredon an SP1DLS inspection system with BSIM capability.The SP1DLS has the same functionality as the SP1 fordarkfield measurements, but provides increased overallsensitivity. For rough 200 mm wafer backsides, thebest results were obtained using S polarization for boththe incident light and dual (wide and narrow) collec-tion channels. To further suppress background scatterand enhance the signal-to-noise ratio, a 20 or 40 degreeaperture was employed. The defect threshold was setbetween 0.2 µm and 0.3 µm.

Next, we created a database of tool fingerprints fromall of the process tools. This is usually done during toolqualification. Using the BSIM option reduces the num-ber of test wafers needed, since the same wafers can beused for front (PwP) and backside contamination tests.

Results and DiscussionStudy 1: Characterization of backside properties on 300 mm wafersFor this study, we created one recipe for pre- and post-lithography inspections maintaining its sensitivity totypical signatures. Three lots were flagged for inspec-tion at critical lithography steps. All wafers were mea-sured before and after lithography on the SP1 BSIMusing the same recipe. The lot results were mirrored onthe tool and sent to the fab-wide defect database inKLA-Results Format (KLARF).

Data analysis revealed that the number of backsidedefects added to the wafers between adjacent lithographysteps (Figure 2) were considerably higher than thenumber added during the lithography process (Figure 3).Furthermore, we observed that the backside defectcount steadily increased throughout the manufacturingprocess on all lots.

D E F E C T I N S P E C T I O N

Figure 1. Effect of defect threshold on the resolution of a wafer handler

fingerprint.

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Figure 2. Pre-lithography backside defect counts — defects that were

present before the lithography step are shown in light red.

0.5 µm 0.7 µm 1.0 µm


We also found that defect density was affected by thewafer’s position in the lot. The first wafers tended tohave the most backside defects, followed by wafers thatwere handled more frequently during the process flow.This tendency (Figure 4) was seen on all lots at eachinspection point. We interpreted this to be the resultof the “cleaning effects” that the first wafers in a lotcan exert on production tools.

Overlaying the backside defect maps of all measuredwafers (Figure 5, left) showed a considerably higherbackside defect count than the stacked defect maps ofwafers that were not handled as often (Figure 5, right).

This step allowed us to establish the baseline defectivi-ty so that process excursions could subsequently bereadily detected.

Study 2: Finding the source of focus spotsSystematic focus spots were previously identified throughpatterned wafer inspection and manual classification.Since the focus spots were visible at multiple layers, theactual source was not immediately obvious. However,backside contamination was considered a possibility,since the defect signature appeared in the same positionon each layer. A tool commonality study was first con-ducted to determine the source, but did not reveal a clearcandidate. Finally, a systematic investigation of backsidedefects (using the SP1 with BSIM) and their correlationto the front side revealed the root cause of the problem.

In this investigation, the wafers with systematic focusspots were measured on the SP1 with BSIM in highsensitivity mode. The defect result files were then“mirrored” using software on the SP1 and transferredto the defect database for analysis. The backside wafermaps all showed distinct wafer handler signatures, whichcould be compared to the fab’s previously establisheddatabase of process tool fingerprints (in the form ofpatterned wafer maps). The patterned wafer maps werethen overlaid with the mirrored SP1 wafer maps. Defectscommon to both maps were flagged for further reviewto determine their size, height and type (Figure 6).These defects — most of which were several microns insize and depth — were identified as holes caused bydamage to the silicon on the backside of the wafers, asshown in Figure 7.

We concluded that this damage was the cause of thefocus spots. A comparison of the inspection wafer mapswith the process tool fingerprint catalogue identifiedthe wafer handler type responsible for causing thedefects. Several handlers of this particular type werelater found to be damaging the wafers, which explainedwhy the tool commonality study was not successful. By

M E T R O L O G Y

Figure 3. Defect added in lithography.

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Nsno200

Add Map Pre-PostLitho M0 (745 defects)

Figure 5. Typical handling wafer at left. “Normal” wafer at right.

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Figure 4. Defect count by wafer position in lot.

Figure 6. a) SP1 map (chuck signatures, coordinates mirrored); b) front--

side, patterned-wafer inspection; c) overlay results of common defects.

a) b) c)


studying the defect mechanism, we determined thatthe defects were also being enlarged through subse-quent process steps, thereby increasing their impact onthe devices on the frontside of the wafer.

Once the source was identified and the defect mecha-nism understood, a simple modification to the waferhandler solved the problem. The yield impact of thisdefect mechanism was determined to be one to twopercent for each affected wafer over a ten-week perioduntil the root cause was fixed.

Going forward Preventing backside contamination from creating prob-lems in the first place is ideal. Although backside cont-amination is present at all layers, it is not always rele-vant to yield. Adding a clean to remove backside cont-aminants can become costly, and does not remove alldefects. 2,3 In addition, scratches and pitting can some-times be made larger by the cleaning process. Thus, itis important to know when corrective action should betaken.

A good place to begin is at the most critical lithogra-phy step, or at the step that has the most focus spots.As with traditional pattern wafer monitoring, only asample of wafers is inspected. A monitoring strategyshould also include excursion control and baselinedefectivity reduction programs.4

Prevention of focus spotsPre-lithography — Backside Inspection: The goal hereis to determine whether large random backside defectsexist on the wafers that could cause a problem duringthe lithography process, and, if so, trigger corrective

action before the wafers reach the exposure tool. A sampleof five to ten wafers can be taken per lot depending ondefectivity level and variability. Random defectivityshould be separated from tool fingerprint signatures, andlarge particles should be separated from small particles.Thus, a backside clean will only be triggered whenlarge, random defectivity occurs in order to avoid toolaborts and random focus spots. The collected data issent to the defect database for further analysis, sincesystematic focus spots cannot be removed by a clean ifthey are caused by damage (Figure 8).

Post-lithography — Frontside/Backside Inspection:Here, the goal is to identify whether focus spots aregenerated during lithography, and, if so, trigger appro-priate corrective action, such as a chuck clean on expo-sure tools and rework of the affected wafers. Inspectionis carried out on macro-defect or micro-defect inspec-tion tools using the same wafers as above to conductpre- and post-comparisons. Focus spots are separatedfrom other defect types, and will trigger a backsideinspection based on the number of identified focusspots. The data is sent to the defect database to beoverlaid with the mirrored backside wafer maps fromthe pre-lithography inspection step (Figure 9).

Wafer backside signature analysisIt is clear that the particle or defect signatures on thewafer backside are key to identifying the root causes of

M E T R O L O G Y

Figure 7. Optical (CRS) images of the backside holes responsible for

the frontside focus problem.

Figure 8. Decision flow to initiate pre-lithography backside cleaning.

SPC by Defect TypeOut of Control

Defect Type

> 0.8

> 0.5

> 0.3

In Control

Backside Scrub

Lithography Process

Data Analysis

Pre LithoBackside Inspection


a particular issue. The next logical step is to automatecurrent manual steps. The difficulty in achieving thislies in being able to separate and automatically classifythe individual signatures without treating them asclustered defects.6 Investigations are currently under wayto determine the best methodologies in implementingspatial signal analysis in a production environment.

However, the signatures alone are not conclusive evi-dence of yield loss. It is the combination of knowledgegained from inline pattern wafer inspection, yieldanalysis and the identification of the tool signaturesthat determines when to take corrective action.

Automating the spatial signature analysis, frontside tobackside correlation, and signature to tool correlationare the next important steps towards implementingbackside inspection into a production environment.

ConclusionsTight depth of focus requirements in high-end semi-conductor manufacturing photolithography leaves littleor no room for any localized deviation in the wafer uni-formity. At feature sizes of 110 nm and below, any con-tamination or topography variation on a wafer backside

causes process difficulties or even yield loss. This isparticularly relevant to the “super flat” 300 mm waferswhich have challenging specifications for wafer surfaceuniformity.

Focusing on 300 mm “super-flat” wafer photolithogra-phy, we identified that the backside defect countsteadily increases throughout the manufacturingprocess. There are two major sources of backsidedefects: defect generation by deposition or furnaceprocesses, and backside contamination by wafer hand-ling. A non-destructive analysis of tool or handlerdefect signatures on the wafer backsides was facilitatedusing the BSIM on the Surfscan SP1DLS. A correlationof backside defect data to front side patterned waferinspection revealed that not all defect issues on a waferbackside are relevant to the photolithographic process.The effect of backside defects is dependent on theirposition on the wafer, as well as their size, shape andorientation.

The most powerful outcome of backside defect inspec-tion is the identification of spatial defect signatures andtheir correlation to tool or process fingerprints. Thenext step is to automate the identification, analysis andcorrelation of such backside defect signatures to toolsand processes.

AcknowledgementsThe authors wish to thank their colleagues at InfineonTechnologies in Dresden and F. Rogers at KLA-TencorCorporation for their input.

A version of this article was also presented at the 2003ASMC Conference, March 31 – April 1, 2003, Munich,Germany.

References1. Surfscan SP1 Online Publications, User Edition Book-on-

Board for SW. Version 3.8.2. G. Vereeke, et al., “The Influence of Hardware and Chem-

istry on the Removal of Nanoparticles in a MegasonicCleaning Tank,” UCPSSS 2002, Ostende, Belgium.

3. M. Lester, “New Single Wafer Processes Offer AlternativeBackside Cleans,” Semiconductor International, January2001.

4. L. Milor, Y. Peng and J. Segal, “Reducing Baseline DefectDensity Through Modeling Random Defect Limited Yield,”January 2000.

M E T R O L O G Y

Figure 9. Decision flow to initiate corrective actions based on number

of focus spots.

After DevelopInspection

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Out of Control

SPC by Defect Type

BacksideInspection

Data Analysis

SPC by Defect Type

Multi Wafers Hit

RandomDefect

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BacksideScrub

Rework

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Pre Litho DefectIn Control

Etch

S P O T L I G H T O N L I T H O G R A P H Y


Chris Mack ReceivesPrestigious SEMI Award

This past December, Semiconductor Equipment andMaterials International (SEMI) honored KLA-Tencor’svery own Chris Mack for his significant contributionsto the advancement of semiconductor manufacturingtechnology at the 24th Annual SEMI Dinner andAward Ceremony, held at the Marriott Hotel in SantaClara, California.Specifically, Mack was rec-ognized for his developmentof software programs thathave enabled process engi-neers to increase productivityof the lithography process.His work over the years hasdriven many changes in thedevelopment, production andoptimization of photomasks,lithography systems, photo-resists and lithographymetrology.

The SEMI Award for NorthAmerica honors individualswho have made significanttechnical contributions to the semiconductor industry.Past award recipients includeWalter Benzing and Mike McNealy for epitaxial silicondeposition; Dan Maydan, Sass Somekh and David Wangfor plasma etch; and KLA-Tencor’s own Kenneth Levyfor automated photomask inspection.

In addition to his long list of academic credentials, Mackhas had a noteworthy career in the microelectronicsindustry. In 1983, he joined the U.S. Department ofDefense, where he began his work in optical lithographyresearch at the DOD’s Microelectronics ResearchLaboratory. From 1990 to 1991, Mack was on assignment

at SEMATECH working inthe areas of deep ultraviolet(UV) photoresist characteri-zation and phase-shiftingmask optimization. Hehelped to found FINLETechnologies in 1990, andjoined full-time as presidentand chief technology officerin 1992. Under his steward-ship, PROLITH — FINLE’sflagship product — becamethe de facto industry standardfor lithography modelingand data analysis software,and it continues to remain so to this day. When FINLEwas acquired by KLA-Tencorin 2000, Mack stayed withthe organization, where

today he heads KLA-Tencor’s advanced lithographyprocess control development efforts as vice presidentof lithography technology.

In our next issue of Yield Management Solutions, we’llsit down with Chris Mack for an exclusive interviewto hear about his early years in the semiconductorindustry; his experiences as president of FINLE; andhow life for him has changed since he transitionedinto his current role at KLA-Tencor.

SEMI president and CEO Stanley Meyers presents ChrisMack with the 2003 SEMI Award for North America.

13Spring 2004 www.kla-tencor.com/magazine

Eliminating Buried Yield Killers

e-Beam Inspection: Best Practicesfor Copper Logic and Foundry Fabs1

David W. Price, Todd Henry, and Robert Fiordalice, KLA-Tencor Corporation

Monitoring and eliminating buried electrical defects has become critical for 130 nm

copper devices and below. As a result, electron-beam inspection is being widely adopted

for development, ramp, and volume production monitoring. In this paper we describe

current implementation of e-beam inspection technology for copper logic and foundry fabs,

including specific case studies which illustrate the benefits of applying e-beam inspection

technology from development through volume production. We also describe methods used

to overcome common implementation hurdles. We then pair best practices with new

advances in e-beam inspection technology to model the optimal implementation for a

hypothetical 20,000 WSPM 300 mm fab.

IntroductionChallenges for production of 130 nm copper (Cu) devices stem from shrinkingprocess windows, complex integration schemes, and the introduction of novelmaterials. A key issue in manufacturing these devices is that many of theyield-relevant defect types are not detectable using conventional opticalinspection tools. Examples include buried Cu via voids, under-etched vias andtrenches, and organic residue at the bottom of high aspect ratio dual dama-scene vias and trenches. E-beam inspection (EBI) can detect these buried electrical defects through the use of voltage contrast (VC) by detecting inter-ruptions in the interconnect path to ground (Figure 1).2 In VC mode EBI isessentially an inline electrical test on product wafers.

EBI has been widely adopted by leading-edge fabs as an engineering analysistool during development and ramp. For example, 30 out of 35 Cu fabs world-wide have at least one EBI tool being used in this manner. EBI engineeringanalysis applications have been documented in the literature by several leadingchipmakers, including Toshiba,3 ST Microelectronics,4 and TSMC.5

SSttoorryyCover


Recently, examples of productionimplementation of e-beam inspec-tion for electrical line monitoring havesurfaced, including papers fromMotorola,6 Texas Instruments,7

Samsung,8 and Altis.9 This trendappears to be driven by the recur-rence of EBI-unique defects in production, particularly at 130 nmdesign rules and below. Further-more, volume production applicationsare expected to accelerate with theintroduction of a new generation ofhigh speed EBI tools. For example,the new KLA-Tencor eS30 is at leasttwo times faster than the previous-generation EBI tool (eS20XP), andcan be as much as 12 times faster forcertain sample plans. Improvementsto production worthiness, defectbinning, and ease-of-use have alsofacilitated implementation in pro-duction implementation.10

In the following sections we willdescribe some of the current bestpractices for EBI implementation inCu logic and foundry fabs; these willinclude a benchmarking survey andrepresentative case studies. Finally,we model the ideal fab EBI imple-mentation and determine the corre-sponding return on investment.

Users typically employ higher sensi-tivity (small pixel) recipes whenbuilding the baseline defect Paretos.In development, when defect densi-ties are high, accurate baselineParetos can be developed by smallarea inspections (<10 percent ofwafer). As systematic problems areresolved and defect densitiesdecrease, more inspection area isneeded to attain a statistically validbaseline Pareto.

It is important to note, however, thatwhile the sampling requirementschange as a function of the defectdensity, in almost every case fabs willstill sample across the entire wafer toobtain wafer-level defect signatures.Such “full wafer signatures” areobtained by inspecting alternate dierows, using run-time swath skipping,or employing area-accelerated (eD0)test structures such as those des-cribed by Weiner et al.11 A typicaleS30 volume production inspectionsample plan is shown in Figure 2.

Table 1 summarizes the productionline monitor utilization of e-beam

These results are predi-cated on the performanceof the KLA-Tencor eS30,an EBI tool which incor-porates KLA-Tencor’slatest technology fordevelopment, ramp andvolume productionapplications.

Best practices for EBI implementationTo assess best practiceswe conducted a surveyof current EBI utiliza-tion within the Cu fabinstalled base. In theback end of line (BEOL),top applications consis-

tently included the minimum pitchVia 1 module. At Via 1 the mostcritical defect types were voids,under-etched, over-etched or miss-ing vias, and residue. Inspections forthis module are most commonly atVia 1 etch (for photo/etch dominat-ed defectivity) and the subsequentCu CMP step (Via 1 CMP or M2CMP for single and dualdamascene processes,respectively). Uppermetal Cu CMP andvia/trench etch inspec-tions are also importantdespite the looser designrule, due to film thick-ness variations and inte-gration problems.

The most common EBIpoint in the front end ofline (FEOL) is contact,whether at etch or attungsten (W) CMP.Driven by shallow junc-tion development, e-beaminspection of the cobaltsilicide (CoSi2) or nickelsilicide (NiSi) modulesare also rapidly becomingcritical applications.

C O V E R S T O R Y

e-e-

e-e-e-

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Contact or Via Etche-e-

e-

e-e-e-

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Figure 1. EBI is the only technology that can detect buried

electrical defects inline on product wafers. Examples of these

defects include buried voids, under-etch, and residue in high-

aspect ratio contacts.

SRAM

Logic

Die Layout

Inspected Area

Figure 2. eS30 throughput is sufficient for volume production

monitoring of 300 mm wafers. Typical production sample

plan: 35 percent of die area (logic portion), full 300 mm

wafer. Total inspection time including overhead is 55 minutes.

Table 1. Percentage of nine surveyed fabs applying EBI line

monitoring at critical layers.

Percentage of Fabs utilizing EBI linemonitoring at keyinspection steps

Cobalt/NickelSilicide

ContactEtch or

CMP

M1CMP

Via 1M2CMP

M3+CMP

33% 67% 44% 56% 100% 67%

inspection for nine Cu fabs. Linemonitor wafer sampling strategiesare dependent upon the size of theyield excursion that is to be detected.Many customers who employ criticalarea models quickly conclude thatlarge-sized chips require more waferinspection area in order to findsmaller excursions. Modeling andempirical fab data indicate that formost volume production monitoringapplications sufficient area can beinspected on the eS30 in a one-hourinspection time.

Faster development and rampEBI enables users to accelerate yieldlearning during development andramp by providing an inline mea-surement of yield-relevant defectivity.In general, the key to successfulinline yield learning cycles is a com-plete understanding of the distribu-tion and frequency of killer defects.Fabs have long used optical inspectiontools to develop such understandingfor physical defects. However, thetransition to damascene Cu structuresfundamentally increased the impor-tance of buried electrical defects, suchas Cu voids and under-etched vias.

To address this need, most Cu fabshave adopted EBI over the last fiveyears. This technology provides rapidquantification of yield-relevant, electricaldefectivity to the engineering teamsconducting process window splitsand integration studies. In addition,EBI provides faster localization ofyield-relevant defect sites. Comparedto end-of-line wafer probe and con-ventional failure analysis, inline EBIcan reduce the average time of alearning cycle from weeks to days.

The benefits of this approach areillustrated by Mizuta and Amai.3

They describe how Toshiba used VCinspection during development andramp of their 90 nm Cu process. Inparticular, the authors implemented

C O V E R S T O R Y

Overcoming post Cu CMP queue time constraintsTable 1 indicates that the some of the most frequent e-beam inspectionpoints are following Cu CMP. However, many Cu CMP processes imposea queue time constraint to minimize the risk of corrosion. Typically, thisconstraint is on the order of four to 12 hours from finishing the final post-polish scrub until beginning the etch stop layer (silicon nitride or siliconoxynitride) deposition. Cu fabs employ several strategies to implementpost Cu CMP EBI monitors within the imposed cycle time restrictions.

The most common strategy is to implement the post Cu CMP EBI monitorafter the nitride cap has been deposited. This is frequently the fab’s pre-ferred approach because it removes the queue time constraint altogether.In some cases, however, this can be a more challenging inspection toperform. Imaging through the nitride cap layer requires a higher thannormal landing energy, e.g. 1800eV for a 400Å cap. Furthermore, thenitride cap makes it more difficult to control surface charging; in manycases, some form of active charge control, such as the e-Control™ capability found on the eS25 and eS30, is required.

Another approach is to simply perform the inspection within the allottedqueue time. Most production EBI monitors take only about one hour perwafer which, in most cases, will leave sufficient time for other inspectionand metrology steps that must also be performed within the queue time.However, the non-steady flow of material through the Cu module mayperiodically result in a queue at the EBI tool. It then becomes necessaryto balance the risk of violating the queue time on some lots against therisk of skipping inspection and missing an excursion.

A third approach is to split inspected wafers from the lot after Cu CMP:the remainder of the lot is capped immediately, while the inspectedwafers queue for inspection before being rejoined. The latter methodusually requires fab automation typical of advanced 300 mm fabs.

Cu

ElectronBeam

M1 CMP post CapLE=1000eVNo contrast

M1 CMP post CapLE=1800eVGood contrast

Nitride cap to protectCu from corrosion

After Cu CMP, a nitride layer is deposited on top to protect Cu from corrosion. A higher landing

energy is needed to penetrate the nitride cap and detect defects of interest. Active charge

control (e.g., e-Control on KLA-Tencor eS30) is also required to control surface potential.

best known methods to overcometwo common EBI implementationchallenges: throughput and defectseparation. First, they optimizedthroughput and sampling by charac-terizing capture rate as a function ofpixel size. They showed that an 86 percent capture rate could beachieved using a large (0.30 µm)pixel size for the primary defects ofinterest (VC lines, islands). As aresult, they were able to implementfull-wafer sampling (eight percentdie area) in a 50-minute inspectionon the eS20XP.

The authors also demonstrate howinline automatic defect classification(iADC) can eliminate the need formanual review by binning severaltypes of VC and physical defectswith greater than 95 percent accu-racy and purity. In total, Toshibareported that EBI enabled them toachieve a faster killer-defect analysiscycle, thereby ramping their 90 nmprocess about 25 percent faster thantheir 130 nm process (Figure 3).3

Baseline yield improvementand excursion control inthe BEOLBuried electrical defects are usuallyfirst found during development, butalso recur in volume production. Thevoltage contrast mode available in EBIprovides a unique capability to detect

C O V E R S T O R Y

Getting to the defect of interestIdentifying a defect of interest requires both the inspection sensitivity todetect the defect, and the ability to separate it from the many other defecttypes in a typical inspection result. The latter is particularly important fore-beam inspection (EBI) which, because of its inherently high sensitivity,is able to detect a wide variety of defect types.

KLA-Tencor uses a sequential defect-segregation approach on the eS30which provides a powerful and flexible combination of imaging configu-rations and algorithms to quickly highlight defects of interest, suppressnuisance defects, and then bin the defects not of interest. This allows anEBI user to efficiently resolve even the tail of the defect Pareto, and tocontrol the line based on the most relevant yield-impacting contributors.

This method consists of three elements: optimized imaging conditions;nuisance filtering and binning algorithms that take place during theinspection; and post-inspection sorting capability that allows the user togenerate the most useful sample plan for high resolution review on the eS30.

Inspection imaging conditionsThe inspection imaging conditions play a critical role in highlightingdefects of interest and suppressing noise sources. EBI imaging of defectsdepends on several variables. For example, the landing energy, beamcurrent, and the field conditions imposed on the wafer surface can turnon and off certain voltage contrast signals by imposing a forward orreverse bias of the structures. Different imaging configurations may beset up as different tests to isolate specific electrical signals.

Landing energy is also important because it affects the relative secondaryelectron yield and, hence, material contrast of the surface. Furthermore,landing energy can affect the depth of penetration and edge contrast. Thisability to tune the material contrast, depth of penetration, and edge con-trast allows the user to preferentially detect certain physical defect types.

Widest Range ofImaging Conditions

WISE-NF

iADC

• Filter nuisance• Bin DOI’s

• Enhance DOI signal• Suppress non-DOI

BMK’sfrom>60sites WW

Rule-based sorting createsthe most relevant reviewsample plan

Real-TimeBinning Algos

Review SortingTools

A complete EBI defect segregation strategy requires optimized imaging conditions, real-time

binning algorithms, and efficient post-inspection review capability.

Defe

ct D

ensi

ty

Time

0.35 um0.25 um0.18 um0.13 um0.09 um

Figure 3. EBI provided Toshiba with the ability

to detect electrical defects in-line, helping them

ramp their 90 nm process about 25 percent

faster than their 130 nm process ramp.3


was introducedinline to monitorfor open vias. Thislog-point enabledTI to reduce themagnitude andfrequency of open-via excursions anddrove a baselineyield improvementof 15 to 20 per-cent (Figure 5).7

these buried defects on product wafersinline — catching excursions thatotherwise would not be found untilfinal test. Many Cu fabs use this e-beam inline electrical inspection toimprove baseline yield and to monitorfor excursions. For example, TexasInstruments’ 300 mm DMOS6 fabused EBI for volume production oftheir 130 nm devices, and for proto-typing runs of 90 nm devices.

During ramp and early into produc-tion, TI DMOS6 noticed yield issuesat final test for a DSP product.Optical inline inspections detecteddefect signatures in the gate loopwhich were unconfirmed by inlineprobe, post Metal 2 CMP. When theflagged wafers were inspected usingEBI in VC mode post Metal 2 CMP,open contacts were verified. Rootcause was determined to be a defecttype called poly pillars (Figure 4a),which occurred at a defect densitybelow that which could be resolvedby inline probe. After the processwas corrected, a lower-cost opticalinspection was introduced at side-wall etch to control excursions.7

During this investigation a secondburied, open-via defect type was dis-covered using EBI on the samewafers. Via contamination (Figure 4b)was found to be blocking the sputteretch prior to barrier metal deposition,resulting in un-landed vias. Thisburied defect could not be detectedoptically, so an EBI inspection point

C O V E R S T O R Y

Detection can also be weighted to preferentially detect VC defects byselecting an appropriate pixel size for the inspection. Increasing pixelsize reduces the capture of small physical defects while still maintaininga high capture rate for most VC defects (and at very fast inspectionspeeds). Finally, effective charge control is also necessary to minimizenuisance defects and to allow aggressive thresholds.

The KLA-Tencor eS30, with the widest range of possible imaging config-urations, provides users with the unique capability to implement thedefect detection scheme most appropriate to the problem at hand.

Run-time algorithmsIn some cases, the optimal imaging conditions may not completely suppressnuisance defects. Therefore, a second level of nuisance filtering has beenadded to the eS30 platform. This filter, known as WISE™ (Wafer InspectionSensitivity Enhancer), allows the user to reject unwanted defects duringinspection.

The remaining defects of interest (i.e., those that are not suppressed bythe imaging and pass through the WISE nuisance filter) can then be separated into different bins through the application of iADC, or inlineautomatic defect classification. iADC operates on the as-detected, multi-pixel image “patches” of the wafer at each defect location. A commoneS30 iADC implementation is to bin defects into dark VC, bright VC,multiple VC, and physical defects.

Review sorting algorithmsThe final binning operation is to sort the defects using a rules-basedapproach for selected manual review on the eS30. The majority of Cufabs perform some manual review on the EBI tool due to the built-in highresolution SEM imaging, state-of-the-art VC imaging capability, and simply the convenience and time savings of not having to move thewafer to a different tool.

The review sorting tools allow the user to apply further granularity to thebins created by iADC. Unlike the run-time algorithms, these are rule-basedand so no previous setup is required. This is useful for cases in which defectsresemble one another, e.g., single dark VC and small dark particle.

Figure 4. Open contacts and via defects were

causing yield problems at TI DMOS6. While the

poly pillar defect (a) can be monitored in pro-

duction using a traditional optical inspection

after sidewall etch, the via contamination defect

requires EBI monitoring in volume production.7

Individual Production Lots

Dar

l VC

D0

Avg. D0 Trend

Figure 5. Texas Instruments DMOS6 improved their baseline yield by 15 to 20 percent by using EBI

monitoring at Metal 2 CMP. This chart shows the open-via (dark VC) defect density trend over time.7


Baseline yield improvementand excursion control inthe FEOLIn addition to the Cu module, non-visual defect detection is also impor-tant in the FEOL — particularly for contacts. Altis Semiconductordescribes implementation of EBImonitoring to detect excursionsinline at contact (W CMP) as part ofa comprehensive methodology thatalso includes EBI monitoring at M1,M2, M3 CMP, CoSi, and Via 1 etch.9

In one case, SRAM contact post WCMP, several excursions went unde-tected until final test. Using thevoltage contrast capability inherentin EBI to flag open contacts, Altiswas able to quickly identify contam-ination and photo/etch issues. Thesewere later traced to inhomogeneousetch chamber cleaning and micromasking on reticles, respectively.Figure 6 shows the EBI defect yieldtrend chart for three contact etchchambers. Numerous excursionsoccurred over the study period. Ineach case, the inline EBI monitorallowed Altis to detect the excursionand take corrective measures sixweeks earlier than if they had reliedon final test.

In another case, EDRAM contactpost W CMP, failure rates were on

average 3.7 times the failure rate of areference SRAM design. By usingEBI monitoring to drive processimprovement activities, the EDRAMfailure rate was driven down to, onaverage, 1.2 times the failure rate ofthe reference SRAM design.

20X return on investment(ROI) for a 20K WSPM,300 mm fabFigure 7 depicts the optimal imple-mentation of EBI technology for a

typical 300 mm, 20,000 WSPM,sub-130 nm design rule Cu logicfab. In this implementation there arethree eS30 EBI tools: one tool forFEOL monitoring (silicide and con-tact), one tool for BEOL monitoring(Cu CMP and via etch steps), andone tool for engineering analysis. Adedicated engineering analysis toolis necessary to drive baseline yieldimprovements throughout the tech-nology life-cycle; this tool alsowould function as a backup for theproduction tools during mainte-nance periods.

The model fab results were derivedfrom the benchmarking surveyresults described in Table 1, casestudies and input from KLA-TencorEBI customers, analysis of excursiondata of over 800 lots of materialfrom EBI monitoring at multiplefabs, and performance data from theeS30 e-beam inspection system.Similar examples of the excursionanalysis methodology are describedin detail by Nurani12 and Soucek.7

The three-year ROI associated withthis optimal implementation is

C O V E R S T O R Y

LeakageShorts

Cobalt/NickelSilicide

Contact Etchor CMP

1 wafer/lot, 33% of lots, ~1 hr/wafer

FEOL LM EA/Backup BEOL LM

Via 1 orMetal 2 CMP Metal 3+ CMP

Under-etched,residue,missing, orpartial contacts

Under-etched,residue,missing, orpartial contacts

Voids; Under-etched, residue,missing, or partialvias; Shorts

Figure 7. Optimal EBI implementation for a 20K WSPM, 300 mm copper fab (sub 130 nm)

includes three eS30 EBI tools.

Toolmaintenance

Defe

ct D

ensi

ty Y

ield

Lot6 Weeks Savings Before Final Wafer Test

T01BT06BT06C

Homogenizationof etch chambercleaningMicro-masking detected

as dark defectsReticle issue

Figure 6. Altis used EBI line monitoring to detect volume production excursions, enabling them to

take corrective action six weeks sooner than if excursions were detected at final test.9


estimated to exceed 20X (Figure 8).Key assumptions used in the analy-sis include the following:

• Leading edge design rule with anaverage selling price (ASP) of$10/die, declining by 10 percentper quarter during yield ramp.

• Nominal time for development(reach 10 percent yield) is 12months at 1000 WSPM.

• Nominal time for ramp (10 per-cent to 60 percent yield) is 18months at 5000 WSPM.

• EBI implementation providesfaster learning cycles (inline versusfinal test) which, in turn, acceleratedevelopment and ramp each by sixweeks. This 10 percent reductionin time to market is conservativerelative to the 25 percent improve-ment reported by Mizuta3 (Toshiba).

• EBI monitoring in volume pro-duction is assumed to detect oneunique excursion every threemonths at each of the four layersshown in Figure 7. These excur-sions are further assumed to affectonly one of eight lots (one of eightchambers, hoods, etc.), in whichthe yield on affected wafers dropsfrom 70 percent to 35 percent.Detecting these electrical defectsinline instead of at final test isestimated to increase yield by 8percent. This is a conservativeestimate relative to the 15 to 20percent yield improvementreported by Soucek7 (TexasInstruments) and other sites thathave implemented EBI monitor-ing in volume production.

The large value for ROI in develop-ment is consistent with the near uni-versal adoption of EBI for Cu devel-opment applications. EBI has beenshown to provide unique capabilityto shorten learning cycles in devel-opment and ramp, leading to fastertime to market and higher ASPs.

This trend will continue to beimportant going forward. The pro-duction ROI illustrates the increas-ing importance of detecting electri-cal defect excursions inline.

SummaryNew technology requirements haveled to adoption of e-beam inspectionin all phases of the technology cycle— development, ramp and produc-tion. A new EBI system (eS30) has

been introduced by KLA-Tencorwhich combines significantlyenhanced throughput and sensitivity,with the defect binning and reliabilityrequired for production.

Modeling of a 20,000 WSPM logicfab indicates that three highthroughput EBI tools provide theoptimum ROI for the fab. Theseresults have been validated by severalleading chipmakers and serve as amodel for new fab space allocation.

C O V E R S T O R Y

E-Beam inspection in memory fabsEBI monitoring in memory fabs is undergoing adoption growth similar tothat seen in Cu fabs. While memory processes do not generally employCu interconnects, the aspect ratios for contact and deep trench memorystructures are typically much higher than those for logic devices. As aresult, EBI is often necessary to monitor for high-aspect-ratio defectivitysuch as under-etch and residue in contacts.

Additionally, memory process flow appears to be more susceptible tosmall physical defects that cannot be detected inline with technologiesother than EBI. As a group, memory fabs therefore tend to monitor morefor physical defects than Cu fabs and, as a result, use smaller pixel sizes.

More detail on e-beam inspection applications in memory fabs can befound in recent papers from Samsung,8 ProMOS Technologies,12 andMacronix13 for stacked-capacitor DRAM, deep-trench DRAM, and flashmemory processes, respectively.

100%

90%

80%

70%

60%

50%

40%

30%

20%

10%

0%

Months0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36

Die

YIie

ld

Faster ramp$84 Million

Excursion Control$206 Million

Faster Development$244 Million

Figure 8. Impact of optimal EBI implementation on yield curve and return on investment.

20 Spring 2004 Yield Management Solutions

References1. This article first appeared in ab-

breviated form as “e-Beam Inspec-tion: Best Practices for CopperLogic and Foundry Fabs,” DavidW. Price, Todd Henry, and RobertFiordalice, Proceedings from the2003 IEEE International Sympo-sium on Semiconductor Manufac-turing, pp. 396-399. San Jose,California, October 1, 2003.

2. R. Cappel and J. Rathert, “The Ad-vantages of Inline electron-BeamInspection,” Yield Management So-lutions Magazine, Vol. 2, Issue 3,Summer, 2000.

3. N. Mizuta and T. Amai, “EffectiveVoltage Contrast Inspection Tech-niques for Ramping 90 nm LogicProcess,” presented at SemiconJapan Yield Management Seminar,Makuhari, Japan, December 5,2002.

4. B. Hinschberger, “Applications of e-beam inspection in a mixed Pro-duction and R&D Environment,” pre-sented at SEMICON Europa YieldManagement Seminar, San Fran-cisco, CA, April 17, 2002.

5. H. Chen. “Appl ica t ions o f aFoundry Fab eS20XP to ImproveFEOL to BEOL Yield,” presented atSEMICON West Yield Manage-ment Seminar, San Francisco, CA,July 18, 2001.

6. J. Fretwell. “Applications of E-BeamWafer Inspection for Inline Moni-toring of Advanced Logic ProcessDevelopment using Inlaid CopperTechno logy.” P resen ted a t SEMICON West Yield Manage-ment Seminar, San Francisco, CA,July, 2000.

7. M. Soucek, J. Anderson, H. Chahal,D.W. Price, K. Boahen, and L.Breaux, “Electrical Line Monitoringin a 300 mm Copper Fab,” Semi-conductor International, Vol. 26,No.8, pp. 80-90. July, 2003.

8. J . Mal i k and M. Gonza lez,“eS20XP Line Monitoring Imple-mentation at Samsung Austin Semi-conductor”. Presented at SemiconTaiwan Yield Management Seminar,Hsin-Chu, Taiwan, August 20, 2002.

9. S. Desmercières, P. Bertin, G. Roy,S. Schön, J.L. Baltzinger, M. Bostel-mann, M. Mercier, J.Y. Nots, and P.Le febv re, “E -Beam Inspec t ionMethodology and Line MonitoringApplications for Copper Technolo-gy,” presented at SEMICON WestYield Management Seminar, SanFrancisco, CA, July 15, 2003.

10. P. Lee, “Production Evaluation ofKLA-Tencor eS30 Ebeam InspectionSystem”. Presented at SEMICONWest Yield Management Seminar,San Francisco, CA, July 15, 2003.

11. K. Weiner, T. Henry, A. Satya, G.Verma, R. Wu, O. Patterson, B.Crevasse, K. Cauffman, and W.Cauffman, “Defect Managementfor 300mm and 130nm Technolo-gies, Part 3: Another Day, AnotherYield Learning Cycle”. Yield Man-agement Solutions. pp 15-27. Win-ter 2002.

12. R. Nurani, et al. Inline Defect Sam-pling Methodology in Yield Man-agement: An Integrated Framework,IEEE Transactions on SemiconductorManufacturing, vol. 9, No. 4, No-vember 1996.

13. W. Wang, D. Chen, C.H. Chien,C.I. Chang, T. Wang, “Implemen-tation of eS20XP E-beam Inspec-tion for Line Monitoring in a 300 mmProduct ion Fab” . Presented at Taiwan Yield Management Seminar,Hsinchu, Taiwan, Nov. 7, 2003.

14. C.H. Hsu, S.T. Ma, Y.M. Wang,“Contact photo/etch process win-dow optimization & yield improve-ment by eS20XP”. Presented atTaiwan Yield Management Seminar,Hsinchu, Taiwan, Nov. 7, 2003.

DAVID W. PRICE has six years’experience as a senior applicationsengineer and regional product man-ager with KLA-Tencor. He hashelped implement e-beam inspectiontechnology at over 15 Cu fabs world-wide. He holds a Ph.D. inMechanical Engineering from theUniversity of Texas at Austin.

TODD HENRY has more than 18years of experience in the product,process, integration and yield areaswith AT&T, Lucent Technology,Agere Systems. He has been a product marketing director withKLA-Tencor for the last two years.He holds a B.S. in ChemicalEngineering from Carnegie MellonUniversity and a MBA from SaintJoseph’s University.

ROBERT FIORDALICE is a seniordirector in KLA Tencor’s YieldTechnology Solutions Division.Prior to joining KLA-Tencor in2000, Bob managed the BEOLdevelopment team at Motorola Inc.’s Research and DevelopmentLaboratory in Austin, Texas. He wasinstrumental in helping Motorolaproductize Cu interconnect and low-k dielectric. Bob has over twentypatents in the area of semiconductorprocessing and integration.

C O V E R S T O R Y

©2003 KLA-Tencor Corporation

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S E C T I O N S

Q Besides airborne base contamination,can anything else cause T-toping in chemi-cally amplifies resists?

A T-topping in positive chemically amplifiedresists is caused by a reduced level of deblocking(the post-exposure bake induced chemical reactionthat enhances resist solubility) at the top of theresist. This reduced deblocking, in turn, is causedby unnaturally low levels of acid, the photochemicalproduct of exposure. So the question is, what cancause acid loss at the top of the resist? Airbornebase contaminants, which land on the resist and dif-fuse into the top portion, can neutralize acid duringthe delay time between exposure and PEB. Theeffects of airborne base contamination can bereduced by reducing the levels of base contami-nants, reducing the delay time between exposureand PEB, and lowering the diffusivity of the conta-minant within the resist. In addition, base addi-tives in the resist can somewhat reduce the magni-tude of T-topping whenever the base additive is astronger base than the contaminant.

Besides airborne contamination, acid evaporationfrom the top of the resist can produce the same typeof T-topping. This occurs when the acid moleculeis too small so that its rate of evaporation is notnegligible. Most modern resists have large enoughacid molecules to avoid this problem. In addition,solvent evaporation during post-apply bake leads toa drier resist film at the top surface. Since solventcontent can affect acid diffusivity and therefore thedeblocking reaction rate, the result can be a reducedlevel of deblocking at the top of the resist. Whilethis effect only rarely leads to T-topping, it canenhance the magnitude of T-topping coming fromanother source.

Q What is Köhler illumination?

A Köhler illumination, developed one hundredand ten years ago for microscope illuminators byAugust Köhler, is the type of illumination used byall modern projection lithography tools (such assteppers and scanners). In technical terms, a Köhlerilluminator is an imaging system where a source (aconventional disk, an annulus of light, or a quadru-pole of four disks, for example) is imaged into theentrance pupil of the main objective lens of thestepper. In addition, the reticle is placed at the exitpupil of the illuminator lens (called the condenserlens). With this arrangement comes some veryadvantageous properties. Any given point on themask is illuminated by the entire source. As aresult, the uniformity of the intensity at the mask isindependent of how uniform the actual source is.In addition, each point on the mask sees the samerange of angles of light illuminating it (i.e., thesame partial coherence). But the most importantproperty of this illumination is that each point onthe mask sees a set of illuminating angles such thatthe diffraction pattern enters the objective lens atthe same place. In other words, every point on themask (every point in the field) will exhibit the samebasic imaging performance.

Got a Litho Question?Ask the Experts

Do you have a lithography question?

Just e-mail [email protected] and have your questions answered by ChrisMack or another of our experts.

Chris A. Mack, KLA-Tencor


of individual layers within the ILD stacks has provenchallenging for some metrology techniques, whichhave difficulty distinguishing between layers of widelyvarying thicknesses made from a variety of materialtypes.1 The presence of under-layer artifacts, especially athigher levels of metallization, also affects the accuracyof film thickness measurements. Simpler optical tech-niques, such as single- or multiple-angle ellipsometry orreflectometry, often do not provide enough informationto separate confusing signals from variations in the mul-tiple layers of interest. Spectroscopic ellipsometry (seesidebar) offers a solution in this case, since ellipsometricinformation (cos delta and tan psi) is collected simulta-neously over 1024 wavelengths. Powerful algorithmsthen interpret this information to yield the best combi-nation of sensitivity to excursions, robustness to normalprocess variation, measurement precision, and long-terminstrument stability and system-to-system matching (thelast two of which are required for production monitoringmetrology). Advances in optics technology, modelingalgorithms and computational processing have enabledfast and routine measurements of thickness and refractiveindex of low-k materials with non-homogenous gradedcompositions, plasma and/or thermal treatment to modifysurface and bulk properties, porous low-k materials andmulti-layer combinations of these films (Figure 1).

More attention is being placed on the mechanical prop-erties of low-k materials, since the ability of low-k filmsto withstand Cu CMP processes and stress migration (SM)

Fims

Taking Control of the Copper Process at 65 nm

Murali Narasimhan, KLA-Tencor Corporation

The move from aluminum to copper (Cu) interconnects has been driven primarily by the desire for better device performance.However, the transition to Cu created a number of unexpected challenges that slowed the rate of Cu adoption at the 130 nm node and stalled efforts to integrate low-k dielectrics into the interconnect. The transition to the 90 and 65 nmnodes has introduced an entirely new set of challenges. This article explores each of these issues in detail and describes thebest-known metrology methods currently available to help IC manufacturers bring the copper process under control at the65 nm node.

M E T R O L O G Y

IntroductionWith several IC manufacturers now com-pleting the development cycle for their second-generation Cu interconnects for the90 nm node, process development engineersare now beginning to look at process issuesthat they are likely to face at 65 nm. Whatthey will find are not incrementally moredifficult process integration problems, butrather an entirely new set of challenges thatwill require the implementation of veryspecific metrology techniques to keep copperinterconnect processing under control. Cuprocess control issues at the 65 nm node canbe broadly classified into five categories: (1)low-k materials; (2) Cu barrier/seed advances;(3) electroplating; (4) Cu chemical mechanicalplanarization (CMP); and (5) interconnectreliability.

Low-k materials and theirprocess control issuesBack-end-of-line (BEOL) inter-layer dielectrics(ILDs) are evolving into a multi-layer stackof passivation dielectric, etch-stop layers,ILD and inter-metal dielectric, and a poten-tial cap layer in the form of harder siliconcarbon nitride (SiCN) to withstand the CuCMP process. Measuring the film thickness


is therefore required in production process equipmentfor 65 nm Cu manufacturing lines. ConventionalMOSCAP CV testing can be used for this application,but requires multiple steps to deposit and pattern metalelectrodes to form the MOS capacitor on the low-k filmbeing measured. The MOS capacitor must then beprobed to obtain the CV curve measurements that must,in turn, be combined with optical film thickness mea-surements to yield the dielectric constant. The two tothree day cycle time involved in making this measure-ment places significant product wafers at risk, especial-ly given the number of possible process steps that canadversely affect the low-k material. Mercury (Hg) probeshave been used to monitor the dielectric constant formany years, but cannot be used inline in an IC fab dueto toxicity and contamination concerns.3

Corona oxide semiconductor measurement techniques(see sidebar) offer a solution for monitoring low-k dam-age by measuring capacitance and trapped charges of alow-k film. A small, precise amount of charge is depositedon the low-k film in the measurement location to form

after processing is key to achieving optimal chip relia-bility. Techniques such as nano-indentation and four-point bridge fracture toughness are currently beingused for materials characterization and early processdevelopment of low-k films. Scientists are also usinganalytical techniques, such as porosimetric ellipsometry,positron annihilation lifetime spectroscopy (PALS) andx-ray scattering to characterize pore size and distribution— both of which indirectly affect mechanical properties.The need for an inline, non-contact technique for pro-duction monitoring of mechanical properties is unclearat this point. However, some early results of applyingthe photo-acoustic metrology technique to measureYoung’s Modulus of low-k films — a key mechanicalproperty parameter — look promising.2

Another emerging process control challenge is the sen-sitivity of the dielectric constant in low-k materials topost-processing. Temperature cycles and environmentswith high mechanical, plasma and chemical stresses inpost-processing steps can modify and degrade thedielectric constant. Monitoring the dielectric constant

Multi-Layer, Multi-Parameter SE Measurement

T N

SiN(500 A)

FSG (4000 A)

SiN(500 A)

FSG(4000 A)

SiN(500 A)

Silicon

503 1.97

1.960

1.96

1.95

1.945

1.937

404.1

475.2

422.2

4.31c+003

414.7

507

4090

401.2

4.18e+003

513

497.5

490.8

488.3

478

1.96

1.943

1.931

Six Layer Low-K Film Stack Repeatability2635.0

2633.0

2631.0

2629.0

2627.0

2625.0

2623.0

2621.0

2619.0

2617.0

2615.0

1.3890

1.3870

1.3850

1.3830

1.3810

1.3790

1.3770

1.37501 5 9 13 17 21 25

Load/Unload

Thic

knes

s (A

)

Low k Top TLow k Top R

SiO2SiC

Low κSiC

Low κSiNCu

§ Measurements using spectroscopicellipsometry with reflectiveoptics on product wafers

§ Simultaneous 16 parameter measurement ofthickness and refractive indices of all six layers

§ Highly robust, precise and sensitive measurements

• Thickness 0.02% - 0.1% repeatability• RI < 0.03% repeatability

Figure 1. Complex BEOL ILD film stacks present a significant metrology challenge, wherein a multi-layer stack has to be measured on a product

wafer without any under-layer artifacts — even at higher levels of metallization.

M E T R O L O G Y


a “virtual electrode.” The surface voltage that is createdfrom this charge is then measured by a Kelvin probethat is positioned at a precise distance above the film.By incrementally depositing more charge and repeatingthe voltage measurements, a Q-V (charge-voltage)curve is constructed and the relevant properties of the

M E T R O L O G Y

low-k material are extracted. Anneal furnaces, high-density plasma chemical vapor deposition (HDP-CVD)reactors, etch reactors, Cu CMP tools, dry/wet cleaningsystems, plasma stripping tools and ashing equipmentcan all be monitored routinely using this technique(Figure 2).

Spectroscopic EllipsometryWith increasing complexity of chip fabrication, spectro-scopic ellipsometry (SE) has established itself as the technique of choice over the last five years for monitoringthin film processes. This technique relies on the measure-ment of the optical properties of materials through analysis of reflected, polarized light across a wide spectral range.

SE relies on measurement of optical properties throughanalysis of polarized light reflected from the sample surface (Figure 1). The incident polarized light is reflectedfrom the sample and passes through an analyzer beforestriking the detector. In the rotating polarizer version ofthis technique used in KLA-Tencor systems, the polarizationstate of the incident light is continuously varied and thedetector measures the integrated intensity of the reflectedpolarized light (for one-eighth of a rotation) at each wave-length. A broadband light source and prism are used toseparate the wavelengths of the light incident on the pixelsforming the detector array. The integrated intensities formthe eight “Sums” corresponding to a complete rotationof the polarizer. The standard ellipsometry parametersTan(psi) and Cos(delta) can be computed from these eight“Sums” at each wavelength. These quantities are relatedto the two components Rp and Rs of the reflected polar-ized light, by the equation:

(1)

where Rp is the electric field reflection coefficient of thecomponent of polarization parallel to the plane of theincident and reflected beams, and Rs is the electric fieldreflection coefficient of the component perpendicular tothat plane. From the above equation, it can then beinferred that Tan(psi) is the amplitude of the ratio of thep- and s- components and cos(delta) is the real part ofthe complex quantity exp(i∆), where ∆ is the phase shiftbetween the p- and s- components.

Theoretical spectra can be generated based on materialmodels defining the substrate and film stack. A mathmaticalregression analysis is performed between the measuredtan(psi)-cos(delta) spectra and theoretical computation.

The theoretical spectra includes optical dispersion models(RI as a function of wavelength) and thickness data forthe film (or film stack) and the substrate. To ensure accu-rate and repeatable results, it is vital to have a robustmathematical model of the dispersion. A simple modelfor the optical dispersion is the harmonic oscillator. Thismodel is based upon the solution for the dipole momentfor a harmonically bound electron acted upon by anelectric field.4 Using this model, the dielectric constant is:

(2)

where (3)

and vk is the local field correction factor. In the equation forHk , Nk is the density of oscillators for the kth oscillator (inunits of nm–3), Ry is the Rydberg constant (=13.6058 eV),r0 is the Bohr radius (=.0529177 nm), Enk is the resonanceenergy of the kth oscillator, Egk is the damping energy ofthe oscillator, Φk is the phase for the kth oscillator and E isthe variable energy. The dielectric function is related tothe optical constants by:

ε = (n – ik)2 (4)

To solve for the parameters in the dispersion model andthe film thickness(t), a regression analysis is performed sothat the difference between the calculated and measuredtan(psi)-cos(delta) spectra is minimized. Mathematicallythe regression is actually performed on the Fourier coeffi-cients (α and β) of the detector intensity as modulated bythe rotating polarizer. The Fourier coefficients are relatedto (tan(Ψ),cos(∆) ) by:

(5)

and (6)

where Α is the fixed analyzer transmission axis mea-sured with respect to the p-direction polarization angle.Both the “analyzer” and the rotating polarizer are linearpolarizers.

tan(Ψ)exp(i∆) = Rp

Rs

.

ΣHkk

1 – ΣvkHkk

ε=1+

Hk=16πNkRy

2r03

(E2nk-E2+iEgkE)

e–iΦk

α= tan2Ψ–tan2Atan2Ψ+tan2A

β= 2tanΨcos∆tanAtan2Ψ+tan2A


Advances in Cu barrier seed While Cu barrier materials at the 130 nm node weregenerally composed of a single layer of tantalumnitride (TaN) or tantalum (Ta), most IC manufacturershave switched to TaN/Ta bi-layer barriers at the 90 nmnode. As a copper barrier material, the Ta/TaN bi-layerbarrier offers a number of benefits, such as TaN’s excel-lent adhesion to silicon dioxide-based ILDs and Ta’sgood adhesion to copper.4 For the 65 nm node, ultra-thin atomic layer deposition (ALD) barriers composedof either TaN or tungsten nitride (WNx) are beingconsidered. The main attraction with ALD is its abilityto deposit highly conformal ultra-thin film layers (downto 10 Å) and provide uniform and conformal step cov-erage on high aspect ratio vias and trenches. Integration

issues, such as adhesion, however, will likely force theindustry to continue to use multi-layer barriers for theforeseeable future.

Monitoring Cu barriers poses significant challenges atthe 90 nm node and below. Conventional techniques,such as four-point probe sheet resistance or photo-acousticmetrology, no longer work effectively because they areunable to separate the individual layers of the bi-layerbarrier. Nor can they measure under Cu seed layers onproduct wafers. Promising new techniques, such as x-ray reflectivity (XRR), require very complex modelingalgorithms and curve fitting. XRR also lacks the smallspot size required for product-wafer monitoring.

M E T R O L O G Y

Corona oxide measurement technologyKLA-Tencor’s Quantox XP dielectric measurement systemimproves processing capabilities by reducing the timerequired to gather information for monitoring criticaldielectric deposition processes. Quantox employsmeasurement principles that are highly analogous toMOS C-V electrical testing with the advantages of fasttime-to-results and non-contact inline measurement.The Corona-Oxide-Silicon (COS) Quantox system isbased on combining three technologies (chargedcorona, vibrating Kelvin probe, and pulsed lightsource) to provide comprehensive, fully automatedanalysis and separation of charge components forcharacterizing dielectric and semiconductor materials.The charged corona ions provide biasing and emulatethe functions of the MOS electrical contact. A graphicaldescription of the components of the Quantox COSsystems is shown in the following figure.

The Quantox corona generator produces ions anddeposits a precise amount of charge on the surface of the dielectric film to form the “virtual electrode” ofa MOS capacitor. The film serves as the dielectric ofthe MOS capacitor and the wafer as the second elec-trode. This structure replaces the capacitor structureformed by depositing and patterning a metal electrodein traditional C-V testing. The ions contact the surfacewith nearly zero kinetic energy, so they do not harm orpenetrate the insulating surface. The vibrating Kelvinprobe provides capacitive-coupled sensing of the wafersurface potential and functions as a non-intrusive voltmeter with virtually infinite input impedance. Thepulsed light source, linked to the Kelvin probe, enablesthe creation of surface photo-voltage (SPV), and

provides measurement of silicon band bending and adirect measurement of Vfb.

The capacitance of the dielectric film, C, is determinedfrom the slope, dQ/dV in the accumulation region ofa Q-V curve collected by Quantox. The capacitance isthen converted to dielectric constant, k, by combining itwith optical thickness, t, measured using spectroscopicellipsometry (k=C*t/ε0). In actual application, somesecond order corrections can be applied to acquiredata to account for semiconductor band bending. Thesystem provides measurement results for productioncontrol (dielectric capacitance and leakage) and plasma process monitoring (density of interface traps,surface voltage, and total oxide charge) as well aselectrical properties of semiconductor materials.

Corona Bias, Kelvin Probe, Surface Photovoltage,Q

+8kV

CoronaSurfaceCO3

-, H3O+

SPV

SPV

Vsurf

Vsurf

1. 2. 3.

4. Repeat

Apply Qcorona BiasMeasure each Q

Measure Vs (= Vox + Ψ)Probe vibration drivesAC current:

I = Vs-Vkp dCdt

Stop vibration, flash light,and measure SPV:

dtI ¯ C d

P SILICON

OXIDE

MechanicalOscillator LIGHT

Kelvin ProbeElectronics

TransientDetection

- + - +

Ψ

Quantox COS measurement theory.


P SILICON

Q-meter

Applysurfacecharge

CoronaSource

Measuresurfacevoltage

S

VOXIDE

KelvinProbe

Applied Q Bias (Q/cm2)

Surf

ace

Volt

age,

Vs

(V)

Accumulation

Inversion

3

1

-1

-3

-5

-7

Leakage

InterfaceStates

Capacitance

Figure 2. Production monitoring of electrical properties of low-k dielectric films is key to ensure parametric yield at 65 nm and below. KLA-Tencor’s

Quantox XP utilizes Corona Oxide Semiconductor measurement technology to monitor dielectric constant and other electrical properties of low-k mate-

rials inline by measuring Q-V (charge capacitance) characteristics of a low-k film.

Barrier composition has also emerged as an importantparameter that must be monitored during production.As the barriers become thinner, their composition playsa larger role in their functionality. Changes in composi-tion can affect diffusion properties, interfacial adhesionand film stress — all of which affect SM and electro-migration (EM) resistance along with time dependentdielectric breakdown (TDDB) in Cu interconnects.Incorrect barrier composition can also result in high viaresistance due to changes in the resistivity and contactresistance of the barrier, thus degrading parametricyield. Conventional metrology techniques do not offera way to measure composition, and, as a result, ICmanufacturers are literally flying blind in production,with respect to controlling the composition of Cu barrier layers. Identifying a method that is capable ofmonitoring Cu barrier composition inline is thereforeessential, as it offers an early warning system forpotentially expensive IC reliability failures in the field.Ultra-thin ALD barriers also lack a reliable productmonitoring solution. Current techniques suffer from anumber of limitations, including a poor signal-to-noiseratio for measurements on sub-50 Å ALD barrier films.Barrier and seed layer step coverage in trenches andvias continues to be an open challenge for inlinemetrology techniques. Scatterometry offers a futurepossibility of monitoring step coverage inline, but thisis an issue that currently has no solution.

A promising new technology in the form of electronstimulated x-ray (ESX) metrology (see sidebar) is nowavailable and can be used to measure thickness and

composition of Cu barrier/seed layers on product wafers.The technique is derived from electron probe micro-analysis (EPMA), a technique that has been widelyused in materials analysis. Advances in electron-beam(e-beam) columns, x-ray detectors and modeling algo-rithms, combined with fab automation, vacuum waferhandling and pattern recognition, have now made thistechnique available for fast inline production monitoringin an IC fab (Figure 3).

Electroplating process controlElectroplating will continue to be the process of choicefor filling trenches and vias at the 65 nm node. Surfacetopography control during the electroplating process isa key issue, since the additives required to ensure fillingoften result in so-called “super-filling,” where thethickness of the overburden of Cu is higher on denselypatterned areas. These super fillings lead to residualmetal due to non-uniform removal during Cu CMP.Voiding of vias and trenches continue to remain an issuedue to aging of the electroplating bath and changes inthe concentration of additives. The latter is caused bydegradation effects of time and temperature on theorganic long-chain polymers. In addition, high platingcurrents can cause edge effects that result in non-uniformthickness at the electrode contact points. These, in turn,can result in residual metal and flaking after CMP.

To adequately characterize Cu thickness inline afterelectroplating requires a non-contact metrology methodthat does not cause edge effects. A small spot size is

M E T R O L O G Y


also needed to achieve the high throughput required forproduction line monitoring. Composition metrology willalso be critical, since tin (Sn) and other alloying elementsare being investigated for use in the interconnect toimprove EM resistance. ESX metrology is capable ofmonitoring both the thickness and composition of

these layers. ESX metrology also has thepotential to detect sub-surface partial voids,which may not have a large voltage contrastsignature — offering an early warning systemfor reliability failures. While high-probabilitysystematic voiding can be effectively detectedwith transmission electron microscopy (TEM)or focused ion beam (FIB) cross-sections withlimited sampling, low-probability randomvoiding of trenches and vias can be effectivelymonitored in production by using e-beaminspection to scan a via chain array in teststructures.5

Cu CMP issues and solutionsCu CMP compatibility has been one of the biggestchallenges for low-k materials, and researchers areworking to reduce the mechanical stresses generatedduring Cu CMP by using low down-force and slurry-lessprocessing. Maintaining topographical flatness is a key

Opaque film thickness and compositionmetrologyThe MetriX 100 opaque film thickness and compositionmetrology system is based on electron beam-stimulatedX-ray (ESX) technology used in materials analysis forover 50 years. An incident electron beam stimulatesx-ray emissions at "characteristic" energies in the filmsbeing measured. Beam electrons interact with atomsin a sample through three main processes: Incomingelectrons knock tightly bound core electrons out of theirshells, and electrons from higher energy levels relax andemit X-rays (source of the ESX signal); freed electronsradiate photons and lose energy (source of the back-ground X-rays); electrons change direction but do notlose energy (source of backscattered electrons).

For high throughput and sensitivity, MetriX 100 useswavelength dispersive spectrometers (WDS) that arefixed in energy and measure X-ray count rate at fixedpoints in the spectrum. X-ray emission, absorption, andinteraction volume in the film stack being measured ismodeled using proprietary algorithms. In order toeliminate instrumental variation and drift, the modelaccepts as input "k-ratios," which are the count ratefrom the wafer divided by the count rate from a knownstandard of the same material stored in the system. Themodel then calculates film thicknesses and stoichiometryof compound films by iteratively converging to withina pre-set measurement error requirement.

• Ionization Depth Model(The number of ionizationsproduced at each depthin the sample.

• Absorption of X-rays ontheir way out of the sample

• Fluorescence effects

ρz

= take off angleI=Ioe-mac

ρz

sin( )ψ ψ

The MetriX 100 algorithm models the following effects:

M E T R O L O G Y

Low-k

Cu

Barrier/Seed Films

Cu Seed

TaNBarrier

Figure 3. KLA-Tencor’s MetriX 100 utilizes ESX technology to provide simultaneous Cu,

TaN thickness and percentage nitrogen measurements on Cu barrier/seed layers.


requirement for Cu CMP and subsequent lithographysteps. Therefore, ensuring uniform polishing and removalrates in order to reduce dishing and erosion — andresultant defectivity — is a significant process controlchallenge. Atomic force microscopy (AFM) and high-resolution profilometry (HRP) offer a good way to charac-terize dishing and erosion during process development.Since these techniques are slow and make quasi-contactwith the wafer, IC manufacturers are looking for a faster,non-contact method to implement for product wafermonitoring. Both photo-acoustic and ESX techniquesoffer a way to measure Cu in wide and narrow lines,which allows for the measurement of dishing and erosion(Figure 4). The ESX technique also offers a way to checkfor residual metal down to 10 Å in thickness in denselypatterned areas, where the polish rate can be significantlydifferent from the average rate across the wafer. In addi-tion, the small spot size of the electron beam has alsoenabled TaN barrier thickness measurement inside widetrenches and power bus line interconnect structures.

Cu reliabilityAlthough Cu has been in use in semiconductor fabrica-

tion for several years, only now are the reliability failuremechanisms of Cu interconnects being discovered andunderstood. While the bulk diffusion rate of Cu withinitself is low, surface and interfacial diffusion rates of Cuare very high, causing void movement at the interfaces,which in turn lead to EM and SM failure. Bi-layer bar-riers, which were created for better adhesion, have theadditional advantage of improving EM lifetime.However, barrier compo-sition can affect Cu diffusionrates, and thus also impact EM and SM lifetime andTDDB. The different coefficients of thermal expansionbetween the dielectrics and Cu metal can also lead tohigher stress gradients, which exacerbate Cu SM. Inaddition, vacancies and micro-voids present in the Cuduring electroplating fill can coalesce during annealsand chip operating conditions, causing line opens andchip failure.

At the 65 nm node, a variety of engineering solutionsare being considered to improve EM and SM lifetimeand TDDB of Cu interconnects. Capping layers grownselectively on the Cu surfaces by electro-less plating isone promising method. In this example, a thin layer ofcobalt tungsten phosphide (CoWP) or cobalt tungsten

CuSiO2

TaN

Si substrate

X-Ray Spectrometersidentify & count emitted X-rays

X-rays emitted:Cu X-Rays, (K line)Ta X-Rays, (L line)N X-Rays, (K line)

Scan Distance (um)

Post-CMP Test by MetriX 100Cu

Thi

ckne

ss (

A)3300

3250

3200

3150

3100

3050

3000

5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90

3300

3250

3200

3150

3100

3050

3000

Scan Distance (um)

Post-CMP Test by MetriX 100

Cu T

hick

ness

(A)

5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90

Scan Distance (um)

Post-CMP Test by MetriX 100

Cu T

hick

ness

(A)

3300

3250

3200

3150

3100

3050

30005 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90

Remaining Cu Thickness

ElectronBeam

Figure 4. Characterizing dishing and erosion during Cu CMP is important to maintain topographical flatness and avoid defectivity issues. Here, the

line scan capability of KLA-Tencor’s MetriX 100 non-contact opaque films metrology system measures remaining Cu metal after CMP and clearly shows

dishing and erosion effects.

M E T R O L O G Y


M E T R O L O G Y S E C T I O N S

boride (CoWB) effectively encapsulates the Cu and pre-vents it from migrating across the dielectric interface andcausing leakage and EM failure (Figure 5). Controlling thethickness and composition of the cap layer is critical,since both parameters impact the diffusivity, interfacialadhesion and film stress of the layer. Conventionalmetrology techniques, such as photo-acoustic or x-rayreflectivity, have difficulty in detecting the interfacebetween the cap layer and the underlying Cu intercon-nect, and thus cannot measure them effectively. TheESX technique, on the other hand, measures the X-rayemissions from the elemental cobalt (Co), tungsten (W)and phosphorus (P) or boron (B), and can quantify thick-ness and composition independently. This capability isinvaluable for optimizing the capping layer process dur-ing process development. It also lends itself in thefuture for line monitoring applications in production.The small spot size of the e-beam allows measurementon different linewidths. This is an important benefit,since chemical loading effects during capping layergrowth can result in variations in thickness and com-position on lines with different feature sizes.

ConclusionThe transition to Cu interconnectshas proven to be much more difficultthan first expected, and numerouschallenges remain for the industryas it ramps up to Cu production at90 nm and begins Cu process devel-opment at the 65 nm node. In addi-tion to the increasing number of filmlayers in ILD stacks that must bemonitored, second-generation low-kmaterials are highly sensitive to post-processing steps, which can degradedielectric constant. Bi-layer Cu bar-riers, ALD barriers and other newfilms introduce new parameters, suchas composition, which must be closelymonitored in production to minimizethe impact of process variations onlong-term device reliability as wellas short-term yields. Some currentlyestablished monitoring methods, aswell as a few emerging metrologytechniques, have demonstrated the

ability to address many of these process control chal-lenges, and show promise in providing the effectivecopper interconnect control needed at the 65 nm node.

References1. Semiconductor Industry Association (SIA), International

Technology Roadmap for Semiconductors, 2001 Edition,Metrology, p. 24.

2. S. Leary, et. al., “Successful use of low-k films requires mea-suring Young’s Modulus,” Solid State Technology, October2003, pp. 32-34.

3. T. Yunogami, et. al., “Development of the damage eval-uation technology of a low-k film by surface photo voltage,”Yield Management Seminar Japan, December 2002.

4. L. Peters, “Making a better copper barrier,” Semiconduc-tor International, March 2003, p. 52.

5. B. Fiordalice and D. W. Price, “Via chain monitoring incopper interconnects,” Semiconductor International, July2002, p. 70.This article has been adapted from an article originally ap-pearing in the 20th Edition of Semiconductor Fabtech.

Cu

Site 1 Site 2

CoWP CuCap Layer

Process A

Process B

Process C

Site 1Site 2Site 1Site 2Site 1Site 2

163172207198163170

CoWPThickness

(?)Co at% W at% P at%

1.6%1.5%1.7%1.7%1.9%1.8%

8.3%8.8%8.5%8.6%8.3%8.9%

90.1%89.7%89.9%89.7%89.8%89.3%

Figure 5. Electro-less capping layers of CoWP require measurements during process development to

optimize process conditions. Chemical loading effects due to changes in feature size can cause

variations in film thickness and composition affecting the functionality of the capping layer through

changes in the interfacial adhesion, mechanical stress and dif fusivity properties of the film. The

small spot size of the electron beam in KLA-Tencor’s MetriX 100 allows the tool to measure thickness

and composition on two dif ferent features with varying linewidths to optimize process conditions

across the die and wafer.

©2003 KLA-Tencor Corporation.

Introducing the only inline, non-contact, advanced films metrology tool that gives you the control you need to avoid product failures in the field.

Independent film composition and thickness measurementsUltra-thin films with high accuracy and precisionMulti-layer film stacks on product wafers90 nm production and 65 nm development

www.kla-tencor.com/metrix

Steer clear of danger down the road.

XInline film composition metrology.



IntroductionSub-pellicle reticle contamination was first reported by Grenon et al.1 as a majorconcern in high volume semiconductorfabs. Bhattacharyya et al.2 identified someof the contaminants as cyanuric acid andammonium sulfate. Since the initial report,many cases of particle or contamination for-mation on both 248 nm and 193 nm reticleshave been reported. While reported cases ofthe problem have beenincreasing as 248 nm lithography becomes more ubiquitous, the introductionof 193 nm lithography inleading-edge fabs has resulted in reports of hazeand contamination forma-tion on reticles at greaternumbers and at a fasterrate.3

As lithographers move to shorter wavelengths, it can beassumed a priori that molecular contaminants in the pathof light will be more reactive and possibly effect trans-mission more radically than at higher wavelengths. Whilereticle surface contamination has been identified as a significant issue at 157 nm, it is rapidly becoming acritical issue at 248 and 193 nm. It should be notedthat the pelliclized reticle structure creates an almostperfect photochemical reaction chamber. Figure 1 showsthe basic structure of a pelliclized production reticle.

The Crystal Growth and ReticleDegradation Exposé

Reticle Surface Contaminants and Their Relationship to Sub-pellicle Particle Formation

Brian J. Grenon, Grenon Consulting, Incorporated William Volk and Kaustuve Bhattacharyya, KLA-Tencor Corporation Andre Poock, AMD Saxony

Crystal growth and haze formation on reticles continues to be a significant source of concern for the semiconductor industry.Possible sources, causes, and formation mechanisms continue to be investigated. Mask making materials, process residues, reticle containers and fab and or stepper environment can contribute to reticle degradation over time. This paper provides acomprehensive evaluation of various molecular contaminants found on the backside surface of a reticle used in high-volumeproduction. Previously, all or most of the photo-induced contaminants were detected under the pellicle. This particular contamination is a white “haze” detected by pre-exposure inspection using KLA-Tencor TeraStar STARlight™ with Un-patterned Reticle Surface Analysis, (URSA). Chemical analysis was done using time-of-flight secondary ion mass spectroscopy (ToF-SIMS) and Raman spectroscopy.

IFW adhesive

Aluminum frame

Frame adhesive

Transparent polymer film(pellicle)

Chrome or MoSipattern

Vent

Film adhesive

Quartz

Figure 1. Pelliclized reticle structure.

LithographyR E T I C L E I N S P E C T I O N


The intra-pellicle space can trap molecular contaminantsand provide an opportunity for them to react and depositon reticle and pellicle surfaces. Note that the inner surfaces of the pellicle have several adhesives: a filmadhesive that is often cyanoacrylate, the inner framewall adhesive (IFW), and the frame adhesive. Thesematerials out-gas and can potentially cause crystal for-mation in the optical path of the reticle. Additionally,surface contaminants on the metal mask and quartzsurfaces can out-gas and be trapped in this space.

Because the reticle user identified this problem, thisinvestigation focused on identifying the chemical com-position and possible cause(s) of the backside quartzhaze. However, it should be noted that identical hazewas detected on the inner surface of the reticle storagebox, as well as in the intra-pellicle surfaces.

Defect detection and identificationDefect Inspection Method — TeraStar STARlight with URSAThe reticle analyzed in this study was inspected usingthe above systems and software options, and was sentfor chemical analysis. The URSA option first detectedthe haze on the backside quartz surface of the reticle.The advantages of this technique are that it providesinspection capability for both surfaces of the pellicleand for the backside surface of the reticle. URSA

employs laser scattering illumination and detectiontechnology to find particles, smudges, fingerprints andother handling defects on unpatterned reticle surfaces.STARlight and URSA combined inspection, providesthe capability to inspect all the surfaces of a reticle(patterned surface, backside quartz, chromium, andinner and outer surfaces of the pellicle). The features ofthis inspection technique are:

1. URSA provides a sensitivity of 4 µm (on PSLS) inabout two minutes/surface.

2. Darkfield defect preview on pellicles and glass whileURSA or STARlight inspections are in progress.

ChromesideDown

UpperLaser

BacksideQuartz

FrontPellicle

BottomLaser

Figure 2. URSA inspection on STAR light reticle inspection system.

R E T I C L E I N S P E C T I O N

Figure 3. Defect map from STARlight URSA inspection — Reticle’s

backside quartz surface.

Figure 4. High magnification image of the haze.


3. Defect review order from largest to smallest.

4. Brightfield, reflected-light review microscope forlive review after completion of inspection.

5. User adjustable sizing box for defect measurement.

6. Defect coordinates referenced to STARlight reference.

7. View reticle pattern under a defect on pellicle or glass.

These capabilities allowed detection of the contaminantson the reticle prior to any potentially catastrophic useof the reticle in production. Figure 2 provides a briefoverview of the basic URSA defect detection system.

Results of Defect InspectionA 6.0 x 6.0 x 0.25 inch pelliclized reticle was inspectedon TeraStar STARlight with URSA following extensiveexposure in the fab. The results of the inspection indi-cated a significant level of haze on the backside quartzsurface of the reticle. Other defects were evident on thefront side of the reticle under the pellicle. For the pur-poses of this investigation we focused on identifying thecomposition and magnitude of the haze contaminationof the backside of the reticle. Figures 3 through 5 pro-vide data generated during the reticle inspection.

Defect IdentificationFollowing defect inspection, the reticle was submittedfor chemical analysis. Both Raman spectroscopy and

Figure 5. Provides high magnification images of the various types of defects detected on the backside of the reticle.


Defect map from STARlight URSA inspection— Reticle backside glass surface


ToF-SIMS analysis were done on several defective areasof the reticle. Figure 6 provides images of the locationsof the analyses.

Raman spectroscopy was accomplished on two of thehaze defects that were small amorphous defects in therange of 1.0 µm. These defects were representative of allof the other haze-type defects on the reticle. The Ramanspectra were collected using a Renishaw Model Ramanspectrometer equipped with a 633 nm laser. The beamsize was approximately 1.0 µm in diameter. Backgroundspectra were collected on the quartz surface in order tocancel out the possibility of contamination due to trans-port and handling during the analysis. The results showthe haze to be one compound, ammonium sulfate.4

Figures 7 and 8 show the spectra for the defects analyzed.These spectra are consistent with the spectra previousreported for ammonium sulfate. The possible sourcesand mechanism of the formation of this contaminantwill be discussed later.

In order to verify the elemental composition of the hazedefects, we conducted ToF-SIMS analysis on the quartz

surface of the backside of the reticle. The instrumentused in this work was an ION-TOF, TOF-SIMS IV™secondary ion mass spectrometer. In this technique, dueto the low primary ion fluence, only outer surfacemonolayers are probed (i.e. a few angstroms). The actualdamage to the sample is very low, and thus the methodis ‘quasi non-destructive’ or static in nature. This tech-nique provides not only elemental information aboutthe surface, but chemical information as well, in theform of fragmentation patterns of molecular species.

A 15 kV, pulsed 69Ga+ primary ion beam was used foranalysis, by impinging upon the sample surface and creating secondary ions in a process known as sput-tering. The primary gallium beam was rastered over a500x500 µm2 area in positive secondary ion mode, and300x300 µm2 in negative secondary ion mode. Bothpositive and negative secondary ions were collected andmass separated via the time-of-flight (TOF) analyser. Atraditional first order mass spectrum was then producedby plotting the ion intensity at a particular mass (morespecifically, mass to charge ratio, m/e; however, the vastmajority of species of interest are singly charged). The

Figure 6. Locations on the reticle (center) where the haze analysis was done. The image on the left is the TeraStar STARlight with URSA image, and

on the right is the image through the Raman microscope.


4600

4400

4200

4000

3800

3600

3400

3200

3000

Coun

ts

Raman Spectrum of Backside Quartz “Haze”

Energy (CM-1)700 750 800 850 900 950 1000 1050 1100

975cm-1

(NH4)2SO4 Coun

ts

Energy (CM-1)700 750 800 850 900 950 1000 1050 1100

1000

950

900

850

800

750

700

650

600

Raman Spectrum of Backside Quartz “Haze” Defects

Figure 7. Raman spectrum of ammonium sulfate defect on quartz side of reticle. Figure 8. Raman spectrum of ammonium sulfate defect on quartz side of reticle.


mass range for this work was 0 - 1000 AMU with a maximum of 10,000 possible; however, acquisition timeincreases with increasing mass range. The nominal resolution approached 10,000 above 200 AMU. Thetechnique has a detection limit approaching PPM levels,depending on the species of interest. As the secondaryion yields are matrix dependent, the technique is notquantitative on an absolute scale, although this may beovercome via the use of appropriate standards.

Figure 9 provides the results of the ToF-SIMS analysis.The intensity scale indicates the relative concentrationsof the various ions detected on the surface. The brighterthe ToF-SIMS image, the greater the relative concentra-tion of that ion. The figure shows the ions of interest. Itis important to note that other significant contaminantswere found on the surface and are not shown here. Theleft side of the figure provides a ToF-SIMS image of theammonium ions that compose the haze. The remainingimages show both the positive ammonium ions and thesulfate ions on the surface.

It is clear from both the Raman spectroscopy and theToF-SIMS analysis that the hazeon the reticle is ammoniumsulfate.

DISCUSSIONChemical MechanismThe most common method forreticle cleaning in the photo-mask industry is the use of sulfuric acid and hydrogen per-oxide at elevated temperatures,

often followed by a dilute ammonium hydroxide rinse.While the chemistries are similar from mask facility tomask facility, the process recipes can change significant-ly. The recipes can even vary within a mask facility.This is probably because not all reticles behave in thesame manner when exposed. These chemistries can leaveresidues on all surfaces of the reticle if improperlyrinsed; they also react with the quartz surfaces. Some ofthe more common reactions that can occur are the for-mation of silicic acid or hydrated silicon dioxide. Theammonium rinse can form ammonium silicate. Figure10 provides the possible mechanism for the formationof the haze on this reticle. While this may be the mostlikely cause, it does not obviate other potential causes ormechanisms for haze formation on reticles.

While surface absorbed ammonium ions are the mostprobable source of the ammonium ions; other environ-mental sources of ammonium ions could cause the for-mation of the ammonium sulfate. However, in mostfabs where chemically amplified resists are used, activatedcharcoal filters are used to filter out ammonia andammonium ions; therefore, environmentally deposited

Figure 9. ToF-SIMS images of backside haze contamination.

SiO2 HO Si

OH

OH

OHH2O2 NH4OH

RinseH2SO4

HO Si

OH

OH

OHNH4O Si

NH4O

NH4O

ONH4

-4 NH4+

hγ (248 or 193 nm)

Silicic Acid Ammonium Silicate Silicic Acid

Residual sulfate ions react with ammonium ions to form: (SO4-2) + 2(NH4+) (NH4)2SO4

HAZE

Figure 10. Possible mechanism for the formation of ammonium sulfate haze.


Increasing intensity or concentration

NH4+ Haze NH4

+ NH- SO4-2 S

Background Quartz


ammonium ions are an unlikely source. Sulfate ions arenot labile (likely to easily undergo chemical change),therefore it is mostly probable that these ions were onthe reticle as a cleaning process residue. Other possiblesources of sulfate ions could be environmental, howeverunlikely this is. Unpublished results have shown highconcentrations of sulfate ions on all mask surfaces fol-lowing mask cleaning.

Exposure Conditions for Haze FormationWhile exposure conditions for particle and haze formationcan vary significantly from fab to fab and from reticle toreticle, exposure conditions under which the haze formedon the reticles in this paper are well understood. Figure 11provides data for several reticles that have shown hazeformation on both the backside, as well as the chromiumside of the reticles.

The above chart indicates that the formation of contam-ination defects is linear for 248 nm exposure and almostexponential with dose for 193 nm. For this reason reticlesexposed at 193 nm provide a greater risk for catastrophicfailure in the fab; hence, they should be inspected at agreater frequency.

ConclusionsCrystal growth and haze formation on reticles continuesto be a significant source of concern for the semiconduc-tor industry. Possible sources, causes and formationmechanisms continue to be investigated. Mask makingmaterials, process residues, reticle containers and faband or stepper environment can contribute to reticledegradation over time. In the case of this study, we feelthat the most probable source of the haze formation wasresidues left on the reticle during the fabrication process.

Backside glass haze can effect overall masktransmission and thus can cause a dose shifton the wafer. A dose shift can be seriousbecause most low k1 processes run with avery small process window and therefore asmall dose shift can create a serious yieldissue. The backside haze can be easily andreliably detected by Starlight URSA inspec-tion. An ideal quality control approach isto detect any possible reticle degradationprior to any catastrophic failure in the fab.This can best be accomplished by re-inspecting reticles prior to exposure. It isrecommended that a carefully-developedreticle inspection strategy be implementedto minimize mean-time to detect defectgrowth. This is best done by understanding

the cumulative dose seen by the reticle and correlatingit with the first detection of reticle degradation. Thesevalues will vary as a function of wavelength and exposuredose in the fab. As a result, each fab should developspecific inspection and re-qualification plans for reticle.

The rate of contamination formation on these reticles wassignificantly faster at 193 nm exposure than at 248 nm,hence a greater inspection or re-qualification frequencywould be recommended for 193 nm lithography.

Reference1. B. J. Grenon, Peters, C., Battacharyya, K. and Volk, W.,

Formation and Detection of Sub-pellicle Defects by Exposureto DUV System Illumination, 19th Annual BACUS Symposiumon Photomask Technology, Proceedings of SPIE, Vol. 3873,pp. 162-76, September 1999.

2. K. Battacharyya, Volk, W., Brown, D., Ayala, J. andGrenon, B.J., Investigation of Reticle Defect Formation atDUV Lithography, 22nd Annual BACUS Symposium onPhotomask Technology, Proceedings of SPIE, Vol. 4889,pp.478-87, October 2002.

3. E.V. Johnstone, L. Dieu, C. Chovino, J. Reyes, D. Hong, P.Krishnan, D. Coburn and C. Capella, 193nm Haze Con-tamination: A close Relationship between Mask and its En-vironment, 23rd Annual BACUS Symposium on PhotomaskTechnology, Vol. 5256, (this volume), September 2003.

4. Y-H. Zhang and C.K. Chan, Understanding the Hygro-scopic Properties of Supersaturated Droplets of Metal andAmmonium Sulfate Solutions Using Raman Spectroscopy, J.Phys. Chem. A, 106, pp.285-292, 2002.

A version of this article was presented at the 23rd Annu-al BACUS Symposium on Photomask Technology, Sep-tember 2003, Monterey, California, USA. Published in the2003 BACUS Symposium proceedings Vol. 5256, pp.1103-1110.

# U

RSA

Defe

cts

Energy kJ0 25 50 75 100 125 150

200180160140120100806040200

Backside Contamination

193 nm Ret1DUV Ret2Linear (193 nm Ret2)

193 nm Ret2Linear (DUV Ret2)Linear (193 nm Ret1)

193 nm Ret1Linear (DUV Ret1)

Figure 11. Plot of the number of defects formed as a function of exposure energy on backside of reticle.

I N S P E C T I O N

©2003 KLA-Tencor Corporation.

FAMOUS LAST WORDS

TeraScanBecause any defect can matter.


For the latest product results, go to:www.kla-tencor.com/terascan


IntroductionThis paper describes an SL3UV inspectiontool-based infrastructure for contaminationinspection of reticles in wafer fabs. This toolscans the patterned surface of the reticle usinga 364 nm laser in simultaneous transmittedand reflected (STARlight™) mode to detectdefects. Such defects include particle conta-minants, stains, scratches, crystal growth oralso certain kinds of pattern defects/irregu-larities.1 Central to the defect detectionmethodology of these requalification toolsis the procedure of STARlight calibration.During this procedure, the tool acquiresimages by sampling various geometries onthe reticle and constructs a database of theirtransmitted and reflected (T/R) light prop-erties. Then, during inspection, the toolscans the reticle, one swath at a time, andthe algorithms compare the digitized T/Rmeasurements at each point on the reticleagainst the previously constructed T/Rdatabase to identify outliers or defects.Unlike pattern defect tools, which use adie-to-die or die-to-database comparison,

the SL3UV tool does not require a reference compari-son image to identify defects.

The STARlight tools have a sensitivity limit of ~0.18 µmat the 0.25 µm pixel (P250), as measured on polystyrenelatex spheres (PSLs). The tools can also be equippedwith the unpatterned reticle surface analysis (URSA)option, which allows quick inspection of the chrome-sidepellicle, the back glass surface and, if present, a backglass pellicle. URSA is a darkfield (off-axis illumination)inspection system which uses 690 nm laser light tolook for particles, scratches or pellicle tears down to aresolution limit of ~4 µm. Figure 1 on the followingpage shows a schematic of an SL3UV system withSTARlight and URSA.

In the following sections we describe the early stages ofimplementation of the SL3UV inspection tools at highvolume manufacturing wafer fabs. First, we discuss thereticle qualification and requalification methodology,followed by a section which compares the differencesand improvements of using the SL3UV tool in a waferfab, as compared with previous methods of reticle veri-fication. Then, we present some data illustrating thesuccess of these tools for reticle requalification.

Implementation of High ResolutionReticle Inspection in Wafer Fabs

Aditya Dayal, KLA-Tencor CorporationNathan Bergmann, Peter Sanchez, Intel Corporation

Many advanced wafer fabs are currently fabricating devices with 130 nm or smaller design rules. To meet the challengesat these sub-wavelength technology nodes, fabs are using a variety of resolution enhancement techniques (RETs) in lithog-raphy and exploring new methods of processing, inspecting and requalifying photomasks. The acceleration of the lithographyroadmap imposes more stringent requirements on mask qualification and requalification to ensure that device yields are notcompromised: mask inspection tools of today need to find smaller defects on reticles against considerably more complicatedpatterns or tighter critical dimensions (CDs). In this paper we describe the early stages of implementation and proliferationof advanced reticle inspection tools at high volume manufacturing wafer fabs. We describe the tools and procedure used tostreamline reticle requalification at the fabs and improve the feedback loop between the fabs and the mask shop.



Reticle Inspection MethodologyThe SL3UV reticle inspection tools in the fabs as well asat Intel Mask Operations (IMO) are connected to a cen-tral data server via Ethernet as shown in Figure 2. Thedata servers (KLA 9Xi) function as the central repository

for inspection reports and also communicate with various reticle repair tools. The primary data server iswhere inspection reports and recipes for outgoing reti-cles are stored. Each tool in the fab can download theinspection report and/or recipe from the primary dataserver. The connectivity of multiple inspection tools tothe primary data server facilitates the process of reticleIQC (incoming quality control) and reticle evaluation.

The reticle management flow is illustrated in Figure 3.All reticles are inspected at the mask house in afinal/outgoing contamination inspection, and therecipes and inspection reports are stored on the primarydata server. Upon receipt at the fab, when a reticle isloaded into the tool for inspection, the tool automati-cally identifies and reads the barcode on the reticle andretrieves the outgoing inspection report from the pri-mary data server. The fab engineer then reviews theoutgoing inspection report and uses the inspectionreport (recipe) to perform an incoming inspection onthe reticle, to identify any new defects added since thefinal inspection. Defect-free plates are sent to the expo-sure tools for printing wafers. If any new defects arefound that fail the defect specifications, the reticle isshipped back to IMO for cleaning and re-pelliclization.In the case of questionable defects, images of thedefects are stored in the inspection report during defect review and classification. The inspection reportsare then saved on the primary data server, and can beaccessed for evaluation by an engineer at IMO. Thedecision of whether to return the reticle to IMO, ornot, can thus be made quickly and more efficiently.

Transmittedlight sensor

Quartz

Chrome Pellicle

LaserGlass sidesensor

Chrome sidesensor

UV laser

Reflected lightsensor

URSASTARlight

Figure 1. STARlight and URSA options on the SL3UV.

Figure 3. Flowchart illustrating reticle management between IMO and

the fabs.

IMO inspects,ships mask

FAB inspectsmask

Newdefects?

Fab engineerreviews defect

Saveinspection

reportlocally

Send maskto stepper

Return maskto IMO fornext step

Save defectimage online

for IMO review

IMOengineerreviewsdefects

Pass?

Pass?

NoNotsure

No

No

Yes

Yes

Yes


SL3UV

IMO

PrimaryData

Server

SL3UV SL3UV SL3UV

Fab A Fab B Fab CFigure 2. Connectivity between the reticle inspection tools and the

data server.


Generally, for each reticle loaded into the tool forincoming inspection, three surfaces are inspected: thepatterned chrome surface, the chrome pellicle and theback glass surface. Depending on the process layer, thereticles are inspected at the 0.25 µm pixel (P250) orthe 0.375 µm pixel (P375). The average inspectionprocess at P375 pixel takes about 65 minutes: 45 min-utes for the chrome surface STARlight inspection, fiveminutes for the URSA glass and pellicle inspectionsand 15 minutes for setup and review. At P250, thecomplete inspection takes about two hours. For eachpixel size, the inspection times can be reduced by about40 percent by using the Fastscan mode albeit at thecost of somewhat reduced sensitivity. Requalification isdone after some pre-determined number of reticle loadsand, like the incoming inspection, also includes aninspection of all three surfaces. Depending on devicelayer and associated defect specification, the operatoridentifies all defects that violate the given defect specfor the surface that is being inspected. These defects aredispositioned appropriately following the flow definedin Figure 3.

Reticle inspection versus print testBefore implementation of the UV inspection tool, legacyinspection tools with lower defect sensitivity were usedto qualify all reticles for the current process. To reducethe number of false defects on the tightest layers of theprocesses, the previous tools were desensitized to catchonly defects larger than 3 µm. This was necessarybecause diffraction of the blue light on the fine lines of the critical layers caused false positive signals. Thepellicle can prevent most of the sub-micron sized parti-cles/contaminants from getting on the chrome surface,keeping the probability of a repeating bad die eventlow. However, if such an event were to happen, the riskto wafer yield would be extremely high. Therefore, tofurther curb the risk of repeating bad die events, thefabs implemented print tests. First, a test wafer wasprinted with the reticle that needed inspection. Thenthe wafer was inspected on a brightfield inspection toolfor repeating bad die defects. The tests consumed step-per and metrology tool time as well as engineer timefor writing the recipes. Additionally, the print test wasonly possible to do on multi-die reticles.

The introduction of the higher resolution reticleinspection tools in the fabs has provided a number ofimprovements over the previous reticle qualificationprocess (lower resolution inspection, followed by awafer print test) and eliminated the need for print test

verification. Some of the improvements/advantageswith the new qualification methodology are:

• Lower cost of reticle inspection: A wafer print testconsumes about 15 minutes of scanner and track timeas well as operator time. Such tools are kept fullyloaded, therefore 15 minutes worth of opportunitycost from product that is not produced, is lost as well.The wafer is inspected on a die-to-die inspection toolwith high sensitivity settings. This consumes aboutan hour of tool time and a half an hour of operatortime. Assuming a wafer average selling price of $2800,a throughput of 40 wafers per hour and 10 layers perdevice yields a lost opportunity cost of $2800 per maskper 15 minutes of scanner time.a Further, assuming adepreciation rate of 20 percent per year for lithoequipment, the total cost associated with performinga single print test verification is about $3000.b, 2 Onthe other hand a full plate reticle inspection of thepatterned surface, as well as the backside glass andpellicle takes about 65 minutes at the P375 inspectionpixel and about two hours at the P250 pixel. If allinspections are done at the smaller pixel size (about1.5 hours of machine time and about 30 minutes ofdedicated operator time for setting up the plate andreviewing the defects), and we use similar numbersas before for the rate of depreciation of the tool andhourly operator costs, the cost of a single reticleinspection is about $150. Considerable cost savingsare, therefore, realized if reticle inspection can elimi-nate or reduce the need for print test verification.

• Increased inspection automation: The STARlighttool inspections can be completed with little userintervention. The tool will load, align, calibrate,inspect, and unload automatically. When the inspec-tion is completed, the technician can go back toreview and disposition the inspection. In the previousmethodology of reticle qualification, every reticle wasrun through a two step process upon initial receipt: Acoarse reticle inspection, sensitivity about 3 µm, followed by a print test. This two-step process involvedsignificantly different tools as well as required multipleengineer support. The print tests were especiallydemanding because they required expensive lithographytool time. An engineer was required to write a first

aThese numbers are conservative averages taken from the literature. They donot represent specific Intel products.

bRepresentative cost of a state-of-the-art litho cluster (scanner + track) isassumed to be $14M, approx. 4x the cost of an SL3UV inspection tool.The costs associated with the wafer inspection tool required for the printtest are ignored here.



level job for the tools. After a wafer was exposed, asecond engineer was required to write a job for thedie-to-die wafer inspection tool. With the SL3UVs thisprocess has been streamlined to a single inspectionrequiring a single engineer/operator.

• Standardized defect classification and memory:One inherent disadvantage of conventional reticleinspection tools over a print test methodology is thefact that reticle inspection tools may detect somefraction of defects that are unlikely to print on thewafer3 (or are smaller than the defect spec for a givenlayer/node). To save time reviewing defects that havepreviously been reviewed and passed, the SL3UV’shave a “Display New Defects” option. This optionallows the operator to define a particular inspectionas the baseline inspection. Generally this baselineinspection is one where the operator has carefullyreviewed all of the relevant defects. Thereafter, everysubsequent inspection of the reticle in the New Defectsmode compares each defect found in the currentinspection with the defect list in the baseline inspec-tion, and reports only new defects. Using this featureenables the operators to ignore defects that havealready been reviewed and for which a decision hasalready been taken, and dramatically reduces redun-dancy in the defect disposition process. Reviewingnew defects on the pattern surface typically takes acouple of minutes. The chart in Figure 4 illustratesthe effect of using the New Defects option on fiveproduct reticles. The fractional decrease in defectcount, directly translates into an equivalent decreasein review time for each inspection.

The total defect count, which can include some nuisance or sub-spec defects, can vary considerablydepending upon the reticle. However in almost everycase there is a significant decrease in review time inthe New Defects mode.

• Batch processing: The SL3UV tools can also beconfigured with autoloader capability to handle multiple reticles. The software allows the operator toqueue up multiple inspections with different recipes,cycling through one or more of the ten slots. Whenthe autoloader queue is completed, the operator canreview all the inspections together at once. This feature increases the efficiency when a large reticlethroughput is required and facilitates operator multi-tasking, i.e. handling of multiple tools.

• Increased sensitivity on tighter layers: TheSTARlight tools have a PSL sensitivity of approxi-mately 180 nm at P250 and 269 nm at P375.Defects of this size can be reliably detected on thepatterned chrome surface without being overwhelmedby “false” defects due to scattering or diffractioneffects.

• Imaging microscope integration and enhancedfeatures: The integrated on-the-tool review capa-bilities of the SL3UV allow for rapid review and dispositioning of all the defects within a few minutesfollowing an inspection. The default review screenuses a 150 nm pixel size for live image review andoffers the option to apply an additional 4x zoom(electronic), as well as a user-defined bounding boxto size the defect.

The use of the SL3UV tool has been especially useful inthe introduction of new products to the factory and inthe rush to bring them to the market. The introductionof these new products to the factory can continue with-out extra delays. Previously, the arrival and qualificationof reticles would be the gating factor for delivery ofnew products. The first lots of the product would bedelayed by the inspection and qualification times of thereticles that were received “just in time.” New reticleswould first need to be inspected on the legacy reticle

inspection tool, wait for an engineer towrite a scanner job, and make a firstlevel print on a test wafer. The waferwould then be sent to the die-to-dieinspection tool where a second engineerwould create a recipe and inspect thewafer. If the entire process went smooth-ly the reticle would be qualified about12-18 hours after it was received at thefactory. By using the SL3UV tool, newreticles are qualified immediately uponreceipt (i.e. within about two hours) andsent into production right away.


1.21

0.80.60.40.2

01 2 3 4 5

Tota

l, N

ew D

efec

tCo

unts

(no

rmal

ized

)

Normalized Defect Count by Reticle

Reticle

Normalized Total Count

Normalized New Defect Count

Figure 4. New Defect counts normalized by the total defect counts for five product reticles.


Reticle requalification results As illustrated earlier (Figure 3) the SL3UV tools atIMO and the fabs are connected to a central data server.The decision of whether to return the reticle to IMO,or not, can thus be made quickly and more efficiently.Figure 5 shows the proportion of total reticles shippedthat were returned to the mask shop for “invalid” reasonsover the period 2001-2002. This period also coincideswith the introduction and proliferation of SL3UV toolsinto the fabs. The solid line in the figure is a linear fit tothe data over the two-year period. Though fluctuationsin the return rate from one quarter to another can be

attributed to a variety of factors, the trend doesshow a gradual improvement (decrease) in thepercentage of invalid returns. We attribute thisimprovement in part to the improved communi-cation/flow between the mask shop and the fabs.

Finally, we present an example where a poten-tial killer defect was identified and caught bythe SL3UV, and the mask was appropriatelyhandled with minimal disruption to the fab orIMO. Figure 6 shows the example of a “dam-aged upon use” mask site that was caughtusing the SL3UV. This defect was initiallymissed during the reticle inspection with the0.375 µm pixel, but was detected by the waferinspection tool (KLA-Tencor 2135) during printtest, as shown in Figure 6(b). However, identi-

fication of the layer containing the defect from thewafer images was found to be very difficult due to thedefect geometry and its location.

Once the suspect mask layer was identified, the reticlewas re-inspected at tighter sensitivity on the SL3UV(with the 0.25 µm pixel) and the defect was detectedwith a 100 percent capture rate. A saved image of thedefect was then reviewed electronically with IMO engineers, and the mask was removed from the produc-tion line. This entire problem was resolved withoutshipping the reticle back to IMO.


1.2

1

0.8

0.6

0.4

0.2

0

Inva

lid

Retu

rns

(% o

f to

tal s

hipp

ed, n

orm

.)

QuarterQ101 Q201 Q301 Q401 Q102 Q302 Q302 Q402

Fab Returns 2001 - 2002

Figure 6. (a) Reflected light image of defect on horizontal line pattern taken on the SL3UV at 0.25 µm pixel. (b) Image of the same site from the

wafer inspection tool. The defect area is marked.

Figure 5. Fraction of total reticles shipped that were invalid returns to the mask house

from 2001-2002, normalized to Q101. Solid line is a linear fit to the data.


Whereas the above event illustrates the value of havingan effective reticle management system, it also pointsout the importance of selection of the inspection pixelon the SL3UV system. As with any inspection system,defect sensitivity of the tool depends upon the featuresize and half pitch on the reticle. For optimal perfor-mance the pixel size should be selected such that thebackground pattern is well sampled. This is specified as

Inspection Pixel Size ≤ 1 * Primary Feature Linewidth2

For the SL3UV the required minimum primary featurelinewidth is 750 nm for the P375 inspection pixel and500 nm for the P250 inspection pixel.

ConclusionsThe SL3UV tools, connected to a central data server atIntel Mask Operations, are being used to provide anintegrated solution for reticle management at Intel fabs.Use of these tools not only provides a significant relieffrom the high opportunity cost of using steppers for printtest verification, but also streamlines the communicationbetween the fabs and the mask shop. The automationand “new defects” features on these tools enable fasterincoming qualification (IQC), particularly for new productreticles. Shorter IQC and requalification times, and a

steady decline of reticle returns for nuisance/invalid reasonsfrom the wafer fabs to the mask shop, have resulted inincreased productivity at both ends of the line.

AcknowledgementsFrom Intel we would like to thank Rajesh Nagpal fordetailed comments on the paper, and Kraig Kottenstetteand Barbara Greenebaum for their help with the waferinspection tool. From KLA-Tencor we wish to thankJim Wiley, Christian Desplat, Bill Volk and GaryPeacock for their ideas and suggestions, and CharikaBecker, Bar Houston and Chris Aquino for applicationsassistance during the early stages of this project.

References1. Dayal, A., Sanchez, P., Eschbach, F., Vargas, A. & Kim,

J., Proc. SPIE Vol 4689 (2002), pp 45-52.2. Muzio, E “Optical Lithography Cost of Ownership- final

report for LITG501” International Sematech, Oct 31st 2000.3. Bald, D., Munir, S., Lieberman, B., Howard, W.H. &

Mack, C.A, Proc. SPIE, Vol 4889 (2002), pp 263-270.

This ar ticle was presented at SPIE Microlithography Conference, February 2003, Santa Clara, California,USA. Proceedings 2003 SPIE Microlithography Confer-ence, Vol. 5038, pp. 1153-1160.


To register online for the upcoming YMS, please visit us at:http://www.kla-tencor.com/seminar

Date: Wednesday, April 21, 2004Time: 1:00 pm – 6:00 pm Location: Munich, Germany

YMS at a GlanceDATE LOCATION

April 21 Munich, GermanyJuly 13 San Francisco, CaliforniaAugust SingaporeAugust Hsinchu, Taiwan

Lithography


IntroductionShrinking design rules and low k1 lithogra-phy bring an increased sensitivity to reticledefects during the wafer printing process.1 Asingle, printable reticle defect that destroysthe chip in which it resides can reduce theyield of a fab area by 25 percent in the caseof a four die reticle, and up to 100 percent inthe case of a single die reticle. The increasein wafer cost, particularly at 300 mm,intensifies the adverse financial impact ofsuch yield losses. Great care is taken bywafer lithographers to interact with reticlesuppliers to generate defect specificationswhich will prevent this occurrence. Indeed,much of the expertise of a modern maskshop centers on the prevention, detectionand repair of these defects.

The task of inspection, however, does notend when a reticle is delivered to the litho-grapher and placed production. In the firstplace, many wafer lithographers prefer to doan incoming quality control (IQC) on thereticle to assure the reticle manufacturerhas met the specifications. Second, a largebody of evidence exists2 showing that

defects can actually grow under the pellicle of a oncedefect-free reticle, causing a printable, and in someunfortunate cases, a killer defect. The defects are parti-cles, crystal growth, and electrostatic damage (ESD) toname a few (Figure 1). The ultimate cost of such defectshas been known to run into the hundreds of millions ofdollars per incident. In cases where the proper reticleinspection equipment and a rigorous procedure for itsuse are in place, the incidence of catastrophic reticledefects has been reduced, effectively, to zero.

Clearly, wafer lithographers must enter the world ofreticle defect inspection.

The purpose of this article is to assist the user in select-ing the best reticle inspection tool for IQC and reticlequalification at each wafer fab site. First, it is importantto establish the goals of the inspection program withrespect to application, defect size and design rule. Somegoal setting considerations will be presented. Second,and most important, it is essential to select a suite oftest reticles that will thoroughly evaluate the toolsunder consideration with respect to sensitivity andinspectability, but also from the standpoint of ease andspeed of operation. Some commonly available test reticleswill be described. Next the actual evaluation processwill be discussed, emphasizing hands-on operation of


Techniques for Evaluating ReticleInspection Equipment for 130 nm

Lithography and Beyond

James A. Reynolds, Reynolds Consulting

The cost of losing a lot of 300 mm wafers is enormous and the impact of an undetected reticle defect that damages hundredsor even thousands of wafers can run into the millions of dollars. The most effective way to prevent this loss is to perform areticle inspection at regular intervals as the reticle is used. Effective reticle qualification requires the selection of reticleinspection equipment which will perform fast, accurate screening of current product reticles and will remain viable for sev-eral generations of products into the future. This article provides a comprehensive methodology for selecting reticle defectinspection equipment for wafer lithography applications.


the system and witnessing of the running of the testplates. Finally, there will be a section on how to assemblethe evaluation data and make a final equipment choice.

GoalsThe first goal to follow is to look beyond the specifica-tion sheet provided by the inspection system vendor.These specifications are provided to set a predeterminedperformance level for inspection system acceptance.The only way to determine actual performance is toallow for a thorough system capability evaluation.

One of the best sources of information on setting goalsfor an inspection program is the reticle manufacturer.Reticle inspection engineers spend much of their timeevaluating reticle inspection equipment and decidingwhich is best for each inspection challenge. Most arewilling to share this wisdom with good customers.

Because of the high cost of the reticleinspection equipment, the programgoals should be based on at least thenext two generations of product intro-ductions. If 130 nm is in currentwafer production, the reticle inspec-tion equipment typically desiredwould be capable of also doing pilotreticles at 90 nm. Once this decisionis made, the International TechnologyRoadmap for Semiconductors (ITRS)will yield a fairly simple table ofrequirements for defect size sensitivity,pattern inspect-ability (i.e. the mini-mum pattern size which can beinspected without too many falsedefects). See Table 1.

It is important to decide on the specificapplications intended so the correctequipment can be determined. Table 2shows several such choices.

If IQC is intended, the inspection system suite shouldmatch that of the reticle manufacturer, providing fulldie-to-die and/or die-to-database capabilities for detec-tion of hard pattern defects. For reticle re-qualification,simultaneous transmitted and reflected light systemsare recommended. They are fast and highly sensitive.These strategies are outlined in Table 1.

In addition to these plans, a rigorous operational regimemust be implemented to make most effective use of theequip-ment. In addition to operating procedures for theequip-ment, such a plan should include frequency ofinspection and defect size requirements for each type ofreticle.

Part of the equipment selection plan should includetime and resources to travel to the inspection systemmanufacturer and do hands on demonstrations of theequipment. Only then is it possible to observe the ease


Node

130 nm

115 nm

90 nm

360 nm

300 nm

260 nm

Minimum 4XGeometry(line space)

180 nm

150 nm

130 nm

Minimum 4XOPC feature

104 nm

90 nm

80 nm

Printabledefect @ 4X Application

IQC

ReticleRe-qualification

Inspectiontechnology

Die to database +die to die

Transmitted &reflected light

Specific system Names(KLA-Tencor products)

TeraScan and TeraStar

TeraSTAR with STARlightinspection

Type of defectto be found

Pattern defects andcontamination

Contamination only

Table 1. Defect detection requirements according to the ITRS Roadmap. Table 2. Recommended equipment for different inspection applications.

Defect Types Found at Reticle Qualification

Defect Appearance Cause

ESD Defects

Crystal Growth

Particles

Caused by handling reticle and inducing electrostatic charge which breaks downquartz at corners and small gaps. Thesedefects grow over time and must bedetected before they become printable.

Caused by photochemical reactionbetween pellicle adhesive and other chemical compounds with chrome/quartz surface.

Caused by contamination atpelliclization station at reticle vendor, or particle movement under pellicle.

Figure 1. Photographs of reticle defects which have been created under pellicles after reticle

manufacture and may cause wafer damage.


of system operation, the ease of defect classification andthe absence of small sensitivity-improving adjustmentsduring the inspection of test reticles. Resources for testreticle acquisition should also be anticipated.

Selecting the test reticleA common mistake in the selection of a test reticle isto present to the equipment vendor a single reticle, frequently the very one which has a printable defect thatcaused a recent yield loss. Most probably, this defectwill be easily found by all types of reticle inspectionequipment. Finding this single large defect is no guar-antee that the system will also find much smaller andmore subtle defects which will also cause killer defectson wafers. It is far better to use a suite of reticles(including the problem reticle) which will exercise allareas of equipment performance.

Many such reticles have been developed and used byreticle and equipment manufacturers for inspection system purchase decisions. Table 3 shows some of thesedesigns and states their advantages and disadvantages.

Selection criteria for test reticlesDefects in “real life” geometries — It is beneficialfor test reticles to simulate actual device geometrieswhere possible. This forces the system to find defects inenvironments similar to those it will encounter in aactual product reticle. Naturally, the test reticle maynot exactly match the designs being inspected but theyshould present a typical situation.

Redundant defects — For assessing sensitivity, it isimportant to have multiple identical defects. This willallow rapid assessment of sensitivity and easy locationof problem defects. At least three identical defects inidentical surroundings for each defect type and sizeincrement is recommended.

Small defect incrementing — Most inspection systemswill find a 300 nm defect and will not find a 30 nmdefect. The way to truly differentiate between systemsis to use a test reticle with small defect increments sothe true sensitivity differences can be demonstrated. A15 nm increment is recommended.

Testing false defect detection capability — The lay-out of a test reticle is very important. Newer test reticledesigns allow the comparison of two non-defective diefor the purpose of determining the occurrence of falsedefect detections. System vendors are then forced to

demonstrate sensitivity and false defect performancewith the same system settings.

No special sensitivity options activated — Some inspection systems have so called“cell to cell” mode which is automatically activatedwhen repeating identical cells are detected. Sensitivityis increased in these areas. Since uniform sensitivityover the entire reticle is the real life requirement, a testreticle should be used that prohibits “cell to cell” mode.This is accomplished by randomly varying the cell sizein which a programmed defect appears.

Highest quality manufacturing — It is vital that thetest reticles be made by the most exacting reticle man-ufacturing techniques. Common reticle errors such asstripe butting errors and CD variations will be detect-ed by the most advanced inspection systems causingthe system to be less sensitive to the programmeddefects. Under these conditions, the comparativeresults will be clouded. The system manufacturershould either have plates which are satisfactory or pro-vide information on where they can be purchased.

An ideal reticle suite might consist of the following:

REYCON 2 — for defects in random geometry andtesting of false defect detection capability

REYCON 3 — for defects in contacts and testing offalse defect detection capability

CETUS — for defects in contacts measured by trans-mitted flux

UIS — for inspectability of simulated patterns whichcause problems for reticle inspection

Running the evaluationAs stated earlier, it is imperative to conduct a defectinspection equipment evaluation in person and toobserve, first hand, the operation of the inspection system.Most inspection system vendors will accommodate thisrequirement. This is the best way to observe not onlythe system operation but to determine the capability ofthe manufacturer to manufacture systems reliably andto support them in the field. Typically three to fivedays will be required for this activity.

Items to accomplish during visitSystem overview — The reticle inspection system



vendor should present information on how the systemworks and how it is operated. This should includeinformation on the number of systems in the field, per-centage uptime achieved, field service strength, upgradepaths and roadmaps for future technology improvements.

System setup — The steps required to set up the sys-tem to run the test plates should be thoroughlyexplained. This should include a discussion on all of thesensitivity and inspectability options available and theway these options are stated on the inspection report.

System operationScanning — The plates should be set up and scannedby the system. It is useful to note the time required tostart and complete this operation as a guide to whatthroughput can be achieved. Typically 10 scans should bemade to accurately demonstrate the system’s capability.

Classification — This very critical step can only beevaluated first hand. The system optics must be goodenough to do accurate and fast classification of thedefect sites established during scanning. If it is hard tosee the defects, an operator might either misclassify adefect or ignore it altogether. This misclassificationcould cause a real defect to be classified as a false defect,resulting in a defective reticle being used on wafers.

Reporting — The system should be capable of manip-ulating data and generating useful accurate reportswhich contain all of the system parameters used in theinspection.

The evaluation event should leave the prospective userwith the feeling that the system will do the job and thatthe company behind the system can keep it running andupgrade it as required by future technology improvements.


Name/Source

VerimaskDuPont

Many defect types with defect sizes down to 54 nm at 54 nm increment

Universally usedEquipment can betuned to detect thesedefects only

Defect location notknown without first inspecting reticle

None

None

Available for larger features

PSL spheres downto 80 nm

Only truecontaminationstandard

Excellent for“Real Life” test.Good incrementing

Excellent fordifficult contactdefects

Excellent for difficultcontact defects.Good incrementing

Good for inspectabilitytests

Universal, Impartial

Defects in simulated devicegeometry down to 600 nmsize and 30 nm increment

Defects in simulated contactsdown to 600 nm and 30 nm increment

Defects in contacts from 1%to 30% flux increment

OrionKLA-Tencor

Reycons 2KLA-Tencor

Reycons 3KLA-Tencor

CETUSKLA-Tencor

UISDuPont

SEMI

Pattern Description Advantage Disadvantage

Many different feature types

None

Programmed defect test masks for lines and spaces, and contact holes

SPICAKLA-Tencor

Defects in simulated device geometry at 15 nmincrements

Applicable for mostadvanced nodes None

None

Table 3. Available test reticles for inspection equipment evaluation in order of technology.


Data reduction A typical defect inspection event, such as the evaluation ofa test reticle, produces a large amount of data consistingof system set up information followed by a completelisting of all of the defects found. To create useful infor-mation from this report, the defect coordinates must becompared with the known locations of programmeddefects on the test reticle. Looking up the size of theprogrammed defect at that location makes it possible todetermine the detection sensitivity of the system (i.e.what was the smallest defect of each type that was found).

This can involve a massive amount of work unless theprocess is automated by the equipment vendor. It isimportant to establish that this capability exists beforebeginning the evaluation.

Finally, for the data to be useful, it must be plotted ona chart similar to Figure 2. Here the detection require-ment for the planned nodes is compared with thedetection capability of the system for each of the defecttypes on the test reticle. Note in the example shown

that, while there were variations in the sensitivity of thesystem to different kinds of defects, all were detected100 percent of the time (10 inspections were made)down to the 100 nm level. This indicates that the systemis satisfactory for the 130 nm node. Testing of this typeon multiple test reticles will guarantee that the inspec-tion system will satisfy the requirements for IQC andreticle qualification.

Final decisionWhen the testing is finished and all the reports arecomplete, a decision about system purchase can be made.The overriding concern is to pick a system which hassufficient defect detection capability to find printabledefects that will cause the loss of wafers and to giveearly warning to degradation of reticle quality due toprogressive defects like particles, crystal growth, andESD. All other criteria are secondary to this. The costof a wafer yield mysteriously dropping to 75 percent or33 percent, or even 0 percent, is just too high to com-promise on this vital parameter. Defect detection capa-bility must be sufficient for the generation of productbeing run now as well as for one or two planned futuregenerations.

When two systems compare favorably from this stand-point, the other points such as company stability, systemextendability, and ease of system operation should becompared.

Reticle defects generated after pelliclization which affectmore than ten lots are being reported at higher rates eachyear. The financial impact of these events is huge. Wafermanufacturers who have taken the time to select theproper reticle inspection equipment have reduced theirlosses from post fabrication reticle defects to near zero.

References1. A. Nhiev, J. Hickethier, H. Zhou, T. Hutchinson, A Study

of Defect Measurement Techniques and Corresponding Af-fects on the Lithographic Process Window for 193nmEPSM Photomask, Proc. BACUS 2003.

2. B. Grenon, K. Bhattacharyya, W. Volk, A. Poock, ReticleSurface Contaminants and Their Relationship to Sub-pellicleParticle Formation, Proc. BACUS SPIE 2003.K. Bhattacharyya, W. Volk, B. Grenon, C. Peters, Forma-tion and Detection of Sub-Pellicle Defects by Exposure toDUV System Illumination, Proc. BACUS SPIE 1999.


Figure 2. Plot of detected defect level versus size for defects on a test

reticle — with a line showing requirements for that specific node.

Unpatterned Wafer


IntroductionHaze, the low frequency signal of lightscattering on unpatterned wafers is a commontechnique used in semiconductor productionfabs to monitor and qualify a variety ofprocess steps. The information distilled outof the captured scattering light is two-fold:1) scattering events (light point defects)used to count and size particles, and 2)haze, or the background scattering signal(Figure 1). This study shows that haze, collected as the low frequency signal from adarkfield inspection tool, is a very effectiveway to gather surface information. Theanalysis of the haze data can be used as apowerful tool to evaluate process performanceconcerning defectivity, uniformity, rough-ness, sealing, etc.

Light scattering toolsIn this study, we focus on the use of theKLA-Tencor Surfscan SP1DLS unpatternedwafer inspection tool to extract the hazesignal from the tool’s scattered signal. Thewafer is illuminated by a laser, with a beameither normal to the wafer surface or oblique(70° to the normal). The scattered light,coming from different defects as well as thebackground of the wafer surface, is collected

by two separate channels. The low frequency componentof the signal of these channels is given as the haze signal, expressed as scattering power fraction per area ofdetector to the total incident power (ppm/Star radial).

Haze reference wafersTo validate the haze signal, a set of standard calibrationwafers was developed on a SEZ spin processor. Thesewafers, which remained stable over time and were


Seeing Through the Haze

Process Monitoring and Qualification Using Comprehensive Surface Data

Frank Holsteyns, Jan Roels, Quoc Toan Le, Karine Kenis, Paul W. Mertens, IMEC

Haze, the low frequency signal of light scattering on unpatterned wafer, is already accessible on the Surfscan SP1 in mostfabs and contains very useful surface information. It can be used as a proxy for other metrology tools to measure thickness,reflectivity, roughness, defects, and can be integrated in SPC tests for equipment monitoring. When combined with defectmeasurements, it provides additional wafer surface information unrevealed by defect monitoring alone.

Figure 1. The captured scattered light consists of light point defects

(LPD) and the haze signal.

Max LPD Area

LPD

Min LPD

Noise

Actual Haze


cleanable, allowed us to evaluate tool stability and toperform tool-to-tool comparisons for different lightscattering tools. As shown in Figure 2, a set of differentstandard haze wafers is used as a reference to monitorthe haze signal over time for the different channels ofthe SP1 (in this case the darkfield wide oblique chan-nel). A good reference is necessary, since a shift in hazevalue was observed after a technical intervention withthe inspection tool.

The creation of these different haze standards, usingvarying surface roughnesses, allows us to link AFMmeasurements (RMS (nm)) with haze (ppm/Sr). Figure 3demonstrates that most of the SP1 channels are verysensitive for changes in roughness, especially for waferswith a particular frequency diagram.

The creation of these standard haze wafers provided theopportunity to integrate the haze data as an evaluationtool in the statistical process control (SPC) methods,enabling process excursions to be flagged.

Process monitoring and qualificationShrinking design rules and collapsing process windowsare stretching metrology tool capability. For this reason

5

4

3

2

1

0Bi-weekly Monitoring

Avg.

Haz

e [p

pm/S

r], D

WO

Chan

nel

Technical Intervention

Haze wafer 1Haze wafer 2Haze wafer 3Haze wafer 4

Figure 2. Bi-weekly monitoring of the SP1 with dif ferent haze wafers.

0.1

0.01

0.2 0.3RMS [nm]

Avg.

Haz

e [p

pm/S

r]

DWODNODWNDNN

Figure 3. Relation between AFM (RMS) and SP1 (Haze) measurements

for five dif ferent wafers.


Monitoring with hazeThe haze signal monitoring capability on KLA-Tencor’sSurfscan SP1DLS unpatterned wafer inspection tool canbe used in many ways: as a measure of nano-sizedparticles (<50 nm) density, surface roughness ofmetallic layers, grain size variations, and to inspectsmall process defects induced in CMP and depositionprocesses The new MX 4.0 haze normalization optionfurther allows normalized haze data to be used forthorough monitoring of process excursions in wafer andIC fabs as the tool inspects wafers and captures defects.

Fluctuations in process parameters, such as temperatureand pressure, often cause deviations in poly grain sizeduring the poly gate process, one of the most criticalsteps in DRAM device production. These deviationscan lead to lower-binning products or device failures.One example of haze monitoring of grain size vari-ation for a rugged poly process is shown below:

Aver

age

Haz

e (p

pm)

Haze Monitor

Upper & lowerlimit

Chamber backto normal

Day1

Day1

1Da

y10

Day9

Day8

Day7

Day6

Day5

Day4

Day3

Day2

Normalized haze measurement can be used for poly furnace pro-

duction monitoring.


it is important that, in addition to light point defects(LPDs), the haze data in defect detection is taken intoaccount to understand and monitor a broader spectrumof process-induced variations.

CVD and PVD processesFor CVD and PVD processes, the surface roughnessand spatial frequency of metallic layers like tungsten(W) and tantalum/tantalum nitride (Ta/TaN), and thethickness uniformity and roughness for transparent layers like silicon oxynitride (SiO2), low-k and photo-resist (typically spin-on processes), can be evaluatedusing haze data. Thickness information can be extractedbecause the standing waves in the metallic layer causedifferent laser light intensities at the top layer. The hazesignal can be related to other metrology data such asreflectivity, thickness and sheet resistance. The benefitsof using the haze signal as a proxy for other metrologysteps are that it can be combined with particle measure-ments, it has a very short process time that reduces overallinspection time, and a full wafer map is provided.

Tungsten CVD processTungsten CVD processes are evaluated in SPC tests onparticles (using the SP1 unpatterned wafer inspection

tool), absolute reflectivity (using the FT-700 tool), andsheet resistance (using the RS75 resistivity measurementtool). From an earlier study,1 the relation between reflec-tivity and haze was shown. This makes it possible toreplace the 49-point reflectivity measurement (Figure 4),of the FT-700 and replace it with a full wafer plot fromthe SP1. By doing so, this measurement — usingoblique incident beam and s-s-s polarization (for beamand two detectors) — can be combined with the particlemeasurement. An upper spec limit for haze can bedetermined (using the maximum reflectivity laid downby the tool manufacturer) and set for the process(Figure 5). A sequence of variations observed in thefinal haze value (but still in spec) of the W could berelated to the use of reclaim wafers of lesser quality. Theexcursion was due to a variation in the process condi-tions: a fluctuation in temperature).

Ta/TaN LayerThe study of the Ta/TaN layers2 focuses more on thesensitivity of the detectors (varying sensitivities for dif-ferent scattering angles) for different spatial frequencies(see the power spectral density diagram) of the wafersurface. The higher the spatial frequency, the morelight will be scattered to the wide detector. The ratioof the detectors to the frequency of the wafer surfacesprovides information about the overall morphology ofthe surface under consideration. Therefore, we couldconclude that a deposition process with a higher biasprovides smoother surfaces (Figure 6). AFM imagesconfirm these findings,for the 50-50 and the 128-128bias setting (biasTaN-biasTa). Similarly, the copper-seedlayer can be evaluated, and the self-anneal process for thedifferent stacks can be monitored by the haze channelof the SP1. Control of this self anneal process plays arole in the suppression of defects like void formationduring plating. Haze information for the barrier andcopper-seed layers allows us to select the optimummaterial for the process, as well as to set specs forequipment SPC tests.

Oxide depositionOxide deposition processes can be monitored for uni-formity or roughness by the haze channel. Both mea-surements are determined by polarizing the light indifferent ways. The uniformity can be evaluated by theS-polarization. The SP1 haze plot can be comparedwith the thickness plot of the KLA-Tencor SpectraFxthin film metrology tool (Figure 7). Any surface unifor-mity problem can be detected by the SP1, but notquantified. The surface roughness and also possibledefect regions can be evaluated by C-polarization. The

75ppm/sr79refl/Si%

80ppm/sr

Figure 4. Output file haze measurement (A) and a reflectivity measure-

ment (B).

9080706050403020100

Weekly Monitoring

Reclaim wafers

Upper spec limitTemperature out of spec

0 5 10 15

Avg.

Haz

e [p

pm/S

r]

A B

Figure 5. Weekly monitoring of the W-CVD process in the prototyping

line.



SPC tests for particles can be extended to the measure-ment of haze and particles. As shown in Figure 8, therole of haze can play an important role in identifyingtool defects; in this particular case, wafer cooling prob-lems. It is interesting to note that, in all cases, haze dataindicates process problems, unlike the LPD channel.

Nano-particlesThe industry is facing new challenges concerning parti-cle removal beyond the resolution of the state of the artlight scattering tools (φLSE <50 nm). The limitations of

being able to measure wafers with small particles and/orin high densities can be overcome at the full-wafer levelby using haze. This method3 can be used to evaluateperformance and uniformity for cleaning tools likemegasonic cleaners (Figure 9). A lot of 30 nm particlesare not removed by megasonics due to the shadowingeffect of the wafer carrier. Based on the Raleigh approx-imation, a simple model is developed to describe theadded haze of a wafer ηadd due to a higher density ofparticles σ.

ηadd = Ωtool • Πpart • σ

In this equation, Ωtool stands for the tool constant(influenced by laser-light-wavelength and optical char-acteristics) and Πpart for the particle constant (influencedby parameters like diameter and refractive index). Theadded haze increases proportionally to the particle

1

0.1

0-128 0-0 50-50 100-100 128-128 128Ta 128TaN

Different barriers: biasTaN -biasTa

bias 50-50: RMS 0.7 nm

Ta on TaN bilayers singlelayers

RMS [nm]

Wid

e H

aze/

Nar

row

Haz

e

0.2

0.4

0.6

0.8

0.10

bias 128-128: RMS 0.3 nm0.2

0.4

0.6

0.8

0.10

Figure 6. HF/LF ratio for dif ferent Ta/TaN barriers and AFM measure-

ments. Higher bias provides a smoother surface.

A B228nm zone

251nm zone

Below Calculated MeanAbove Calculated Mean

-+

Figure 7. Output file of (A) a haze measurement and (B) a thickness

measurement.

Figure 8. SPC tests for 200 nm oxide using haze and the LPD channel.

Cooling problems are monitored with haze in five cases, and with the

LPD channel alone in four cases.

Figure 9. An evaluation of a megasonic cleaning tool for 30 nm SiO2

particles. The SEM review tool is used to count particles.

5

4

3

2

1

0

3000

2500

2000

1500

1000

500

0

Daily Monitoring

Haze +LPDs Only

Haze

Added DefectsHaze (ppm)

0 5 10 15 20 25 30 35 40

Haze [ppm

],

Adde

d De

fect

s

3 x 1014 #/cm3

55 - 9025 - 550 - 25

PRE (%)

Low-masscarrier

Transducearray



dielectrics, after CMP, treated with toluene and mea-sured with the SP1. This haze data is analysed using theMX4.0 haze analysis capability of the SP1. The resultsreveal the easily-neglected condition that a clear sealingis lacking at the edge of the wafer and at certain pointson the wafer surface, due to the presence of big particles.

AknowledgemensThe author would like to thank the Surfscan Divisionof KLA-Tencor for the fruitful and interesting coopera-tion in this study, and SEZ for the creation of the hazereference wafers.

This article was originally presented at the 2003 ISSMConference. Proceedings of the 2003 IEEE InternationalSymposium on Semiconductor Manufacturing,September 30 to October 2, San Jose, California, USA.

Refernces1. F. Holsteyns et al., “Process Monitoring and qualification

of CVD/PVD tools using comprehensive surface haze in-formation,” presented at the KLA-Tencor Yield ManagementSeminar, Japan, 2002.

2. L. Carbonell et al., “Defectivity study of Cu MetallizationProcess by Dark- and Bright-Field inspection,” Solid StatePhenomena, vol. 92, pp 281-286, 2003.

3. K. Xu et al., “Relation between Particle Density and Hazeon a Wafer: a new approach to measuring Nano-SizedParticles,” Solid State Phenomena, vol. 92, pp 161-164,2003.

4. A.L.P. Rotondaro et al., “Interaction of Sulphuric Acid Hydrogen Peroxide Mixture with Silicon Surfaces,” Pro-ceedings of the 2nd international symposium on ultra-clean processing of silicon surfaces, pp 301-304, 1994.

density. Using SEM review, a clear relationship can bethen established between haze and particle density.

Cleaning performanceA spray acid tool (batch stripper) is used for chemicalcleaning, stripping and etching. For the daily SPC tests,a blank silicon wafer is processed with H2SO4/H2O2

(10:1 ratio) for 10 minutes at 95 degrees C. In additionto detecting traditional particle defects, haze is usefulfor identifying other process problems. For example,when the rinse step following the acid step is not per-forming well, sulfuric residues will remain on the wafersurface and form ammonium sulfate crystals.4 The hazesignal will be high because of the presence of thesecrystals. Figure 10 illustrates that the haze signal is toohigh with respect to the target value set for the Si wafers(0.05 ppm). To detect these problems and test the effec-tiveness of the cleaning process, the haze data is neces-sary, and can be simultaneously used with the LPD data.

Sealing defectsThe combination of solvent adsorption and haze allowssealing defects at the surface (BEOL) to be localizedand quantified. Results on different hardmasks(HM)/dielectric stacks, such as CVD HM on CVDdielectric, CVD HM on spin-on dielectric, and spin-onHM on spin-on dielectric, can be easily evaluated.Figure 11 provides an example of a CVD HM on CVD

Figure 11. On the left, a haze plot after toluene treatment; on the

right, a decorated defect which caused the sealing problem.


Figure 10. SPC tests for a batch stripper, haze and LPDs are given, in

some cases only haze is measured.

3000

2500

2000

1500

1000

500

0

-500

25

20

15

10

5

0

Defe

cts

> 0.

2 µm

Haz

e [p

pm] Presence of crystals


at nominal focus/exposure. The modeling will be com-pared to SEM measurements on the wafer.

Test vehicleThe programmed defect mask selected for this analysisis the DuPont Photomask VT491™ Verithoro design.The mask is an embedded phase shift mask (EPSM)designed for 193 nm lithography. The photomask isfabricated with six percent transmission molybdenumsilicide (MoSi) on quartz blank. The VT491 mask has anominal design circuit of 400 nm space (reticle scale)with a 1:2 ratio pitch. The nominal contact design is900 nm at reticle scale with a pitch of two microns. Thereare 20 defect types, each ranging in design size of 0 to450 nm in 50 nm steps (reticle scale). The mask isdesigned to run in die-to-die inspection mode, with theprogrammed defect die in the middle of a seven by onedie array. Figure 1 shows the defect types, design, andSEM sizes, as well as the 100 percent capture rate (shownby the darkened cells) and review measurement size foundin each of two UV and one DUV inspection systems.Columns 5-9 have been omitted from this chart, as theselarger defects are found by the inspection 100 percent ofthe time and would always be transferred to the wafer.

IntroductionPhotomask manufacturers typically repairmasks when any visible defect is found during reticle inspection. This repair addsextra steps to the manufacturing processand increases the risk of damage to themask. With a comprehensive analysis ofdefect sizing techniques, and modeling theimpact to the wafer of various defect typesand sizes, a better decision can be madeconcerning whether an individual defectwill have an effect on the lithographicprocess. This is also beneficial to devicemanufacturers who periodically re-inspectphotomasks between production lots andmust decide when a mask needs to bereplaced due to increasing number ofdefects. This paper will look at size mea-surements made by UV and DUV reticleinspection systems compared to SEM mea-surements on the mask. It will then modelindividual defects through hardware-basedand software-based aerial imaging simula-tion to determine the impact of the defect

Simulating the Impact of Reticle Defects

A Study of Defect Measurement Techniques and CorrespondingEffects on the Lithographic Process for a 193 nm EPSM Photomask

Anthony Nhiev, Jason Hickethier, DuPont PhotomasksHaiqing Zhou, Texas Instruments

Trent Hutchinson, William Howard, Mohsen Ahmadian, KLA-Tencor Corporation

Photomasks with small dense features and high mask error enhancement factor (MEEF) lithography processes require stringent reticle quality control. The ability to quickly and accurately measure reticle defects on a high-resolution inspectionsystem and to simulate their impact on wafer printing are key components in ensuring photomask quality. Tests show thatthe inspection system can quickly and accurately determine sizes of most defects. The study also indicates that the simulationtechniques can accurately tract the lithographic results, and can be used to reduce or eliminate the use of test wafers andexpensive lithography and wafer metrology time. The outcome of this study leads to better defect dispositioning by providingtechniques to determine the size and printability of reticle defects.



Photomask CDSEM analysisEach of the 200 defects were manually measured on themask with a KLA-Tencor 8250-XPR™ low voltageCDSEM at 1000eV. The system was calibrated using a1000 nm pitch standard supplied with the system. Themeasurements were taken at the appropriate scan rota-tion to reflect accurate measurements of defects on cor-ners and angled lines. High-resolution images of eachdefect were captured at 100,000 magnification. The

defect size recorded is the maximum extent of the defectrelative to the “0” column, where no defect is present.Typical repeatability of a CDSEM measurement is betterthan 2 nm (3 sigma).

Photomask inspection and reviewThree KLA-Tencor inspection systems (two TeraStarSLF-77™ UV and one TeraScan DUV 525™ model)were used to inspect the test mask in die-to-die mode.

Figure 1. Defect types, design, SEM, review sizes, and capture rate (shaded). All sizes are reticle scale in nanometers. For the design images shown

in the table, black represents a space in the EPSM material. A “*” indicates the features did not resolve on the photomask. A “**” indicates that the

features were found during inspection but cannot be measured with review linewidth measurement software.



For each system, four inspections were conducted tocomplete the repeatability and sensitivity analysis.Each of the captured defects was measured using thereview linewidth measurement software included withthe systems. The defect sizes were graphed as a functionof SEM measurements. Sensitivity analysis was performedand is shown in Figure 1. The pin-hole and pin-dotdefects were detected as shown by the shading in thetable. However, the linewidth, measurement reviewsoftware failed to measure their size. Figures 2-4 showsome of the typical defect types.

Wafer printing and analysisTwo focus exposure matrix wafers were printed with thetest mask using a 193 nm DUV lithographic scanner,

Nikon model-S305™. The standard 100 nm node DUVmoat resist process was used to print the wafers. Thetwo bare silicon wafers were first coated with DUVBARC of 0.043 µm, and then coated with DUV resistof 0.23 µm. For rows A-L, Q, and R, best exposure wasdetermined to be 46 mJ/cm2 at a focus offset of - 0.25microns. For the contact rows M-P, S, and T, the bestexposure was 38 mJ/cm2 at a focus offset of - 0.25microns. Wafers were analyzed using the KLA-Tencor8250-XPR CDSEM at 800eV. All 200 programmeddefects were measured at best focus and exposure.Measurements were performed at a scan rotation per-pendicular to the defect and reflect the maximum CDchange from the reference (0) column. Figure 5 displaysthe design defect size along with the change in CD(absolute value) using three methods: wafer SEM mea-surement, AIMS, and TeraSim.

AIMS simulation and analysisAIMS simulation was conducted and compared foraccuracy and ease-of-use with the wafer printingresults. This optical lithography simulation consistedof AIMS (aerial image measurement system) Fab 193™from Carl Zeiss, the most common system used forfinal qualification and dispositioning of reticle defects.It is a hardware-based simulator that requires the maskto be loaded to obtain high-resolution images thatapproximate the aerial image when exposed with aDUV lithographic scanner. The illumination conditionwas set to match the scanner’s settings. AIMS resultswere measured using five-pixel averaging over the ref-erence and defect area. Intensity values were measuredand recorded for both clear and dark geometry. Usingthe AIMS software linewidth versus threshold plot, ref-

erence regions were used to set an intensitythreshold that resulted in a printed CD corre-sponding to the non-defective nominal spaceand pitch of the reticle scale. This intensitythreshold was then applied to each defect regionto measure CD impact on the wafer. Clear reference calibrations for image normalizationwas acquired approximately every hour toreduce the error attributed to laser instability.

Figures 6 and 7 show typical defects, AIMS-Fab simulation and actual mask measurementsversus wafer SEM measurements. The mask

values were divided by four to account for the scannerreduction. All three inspection systems match themask SEM measurements very well. The AIMS resultshave a good correlation to the printed wafer results.

0.600

0.500

0.400

0.300

0.200

0.100

0.0000.000 0.100 0.200 0.300 0.400 0.500 0.600

SEM Size (microns)

Row A - Clear Extension on 30 Degree Space

SLF-77ASLF-77B525

Figure 2. Row A, inspection system size as a function of SEM mea-

surement. SEM image of mask, and SLF review image.

0.600

0.500

0.400

0.300

0.200

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SEM Size (microns)0.000 0.100 0.200 0.300 0.400 0.500 0.600

SLF-77ASLF-77B525

Figure 3. Row E, inspection system size as a function of SEM mea-

surement. SEM image of mask, and SLF review image.

0.600

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Row Q - Vertical Over-sized Space

SEM Size (microns)0.000 0.100 0.200 0.300 0.400 0.500 0.600

SLF-77ASLF-77B525

Figure 4. Row Q, inspection system size as a function of SEM measurement. SEM

images (reference and test) of mask, and SLF review image.



converted into a pair of defect and reference simulationmasks used to predict the aerial image at best focus. Thelithographic impact was evaluated using two methods.

First, the intensity difference metric (IDM) was calcu-lated as described below. Consultations with variousAIMS users have shown that most use a single-valueintensity metric to judge the printability of reticledefects. Further, it is common to use a standard of tenpercent for determining whether a defect should or

Simulation and analysisA new prototype version of TeraSim™, KLA-Tencor’sreticle defect printability software, was used to simulatethe lithographic impact of the programmed defects. Thesimulation settings were adjusted to match the hardwaresimulations made with the 193 AIMS Fab system forscanner wavelength, NA, and illumination condition.Defect and reference transmitted light images werestored after the TeraScan inspection and were convertedto bitmapped images. These bitmapped images are

Figure 5. Defect type, design size, SEM, AIMS, and TeraSim measured sizes. All sizes are wafer scale in nanometers. A “*” indicates that the defect

did not resolve on the wafer or the AIMS-FAB and TeraSim modeling suggested the programmed defects would not have resolved. A “**” indicates

that the main feature did not print or was not predicted to print by simulation.



Figure 8a and 8b shows two examples to illustrate howthe IDM is defined.

An example of a comparison between AIMS and TeraSimbased on IDM is shown in Figure 9. The R-seriesdefect is an over-sized clear horizontal line shown inblack near the bottom of the cell. The IDM increasesmonotonically with defect size, as one would expect,and the match between TeraSim and AIMS is good.

A second comparison was made by matching the pre-dicted change in critical dimension (CD) from AIMS andTeraSim to the actual wafer CD change measured on theCDSEM. The AIMS data was processed by the AIMSoperator at DPI, and the TeraSim data was processedusing the new prototype version. Both AIMS and TeraSimresults are contour plots of simulated aerial image inten-sity. To extract CD values from these data, the edges mustfirst be located by selecting a particular threshold con-tour. This is done by calibrating to several non-defective

should not be repaired. That is, if the intensity metric isless than 10 percent, the defect is not repaired. As partof this study, we used such a metric to determine howit can be used to better understand and quantify theprintability issue. The IDM is defined by equation 1:

IDM =100%x IRef – ITest (1)MaxRange

The values in the numerator are taken at the locationwhere the test and reference aerial images differ by thelargest amount. Using the absolute value ensures thatthe IDM is always a positive number expressed as apercent. The denominator is the normalization factor,which is calculated from the maximum range of theaerial images in the vicinity of the defect location. Forthe results presented here, the IDM was calculatedusing the prototype version of TeraSim, which can readAIMS data. The AIMS test and reference data wereprocessed using the same software used to process thesimulated aerial images from TeraSim.

Figure 6. Row M, inspection review, reticle SEM CD, and AIMS CD

versus wafer SEM CD measurements (units in microns).

Figure 7. Row Q, inspection review, reticle SEM CD, and AIMS CD

versus wafer SEM CD measurements (units in microns).

0.000 0.020 0.040 0.060 0.080 0.100 0.120 0.140 0.160

0.160

0.140

0.120

0.100

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Wafer SEM CD Measurements (microns)

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ecti

on R

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w, R

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le S

EM C

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nd A

IMCD

Mea

sure

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ts

Mask SEM/4Review Avg/4 SLF AReview Avg/4 SLF BReview Avg/4 525AIMS CD

Row M - Over-sized Contact

0.160

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0.0000.000 0.020 0.040 0.060 0.080 0.100 0.120 0.140 0.160

Wafer SEM CD Measurements (microns)

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nd A

IMCD

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Mask SEM/4Review Avg/4 SLF AReview Avg/4 SLF BReview Avg/4 525AIMS CD

Row Q - Linewidth Variation

Figure 8a. A simulation mask with chrome extension (left) and the

resulting aerial image intensity along a horizontal slice centered on

the defect (right). The nominal peak and trough intensities of the aerial

images are shown with dashed horizontal lines and the drop in inten-

sity of the peak is shown with a solid line.

IDM = 100% x |.62-.58|/(.62-.20) = 9.5%.

Figure 8b. A simulation mask with quartz extension (left) and the

resulting aerial image intensity along a horizontal slice centered on

the defect (right). The nominal peak and trough intensities of the aerial

images are shown with dashed horizontal lines and the increase in

intensity of the trough is shown with a solid line.

IDM = 100% x |.25-.20|/(.62-.20) = 11.9%.

1.2

1.0

0.8

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0.0-1000 -500 0 500 1000

X Position (nm)

Relative Intensity

1.2

1.0

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0.6

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0.0-1000 -500 0 500 1000

X Position (nm)

Relative Intensity



features on the wafer. This calibration step is done inde-pendently for the AIMS and TeraSim data. After thiscalibration, the CD difference values were calculated ateach of the defective sites. The simulated CD changefrom TeraSim and AIMS can then be compared to eachother and the wafer print results. When one makes sucha comparison, caution must be exercised, because theAIMS and TeraSim data are simulations of the aerialimage which do not take into account the resist pro-cessing effects. For example, previous research hasshown that line end shortening (LES) is caused by multiple effects and that a portion of LES is caused by resist processing.4 Therefore, the amount of LESpredicted by simulating an aerial image will normallybe less than that seen on the wafer.

An example of this comparison is shown in Figure 10.The K-series defect is a misshapen EPSM feature shownin white on the left side of the cell. The change in CDincreases monotonically with defect size, as one wouldexpect, and the match between TeraSim, AIMS andwafer print data is good.

ConclusionIn this paper we demonstrated that the inspection sta-tion review tool is capable of predicting the size of defects

within ± 50 nm for a normal line/space geometry andover/undersize contact. However, pinhole and pin dotdefect types are less predictable. This study showed thatboth UV-based and DUV inspection systems are capableof detecting these defect types well below 200 nm, butAIMS and wafer printing correlation revealed they haveno significant impact on printability. To produce highlyaccurate prediction beyond the inspection review tool,AIMS and TeraSim simulations can be used to estimatedefects on complex design circuitry. AIMS system is wellknown within the industry for accuracy in simulatingthe lithographic process, and this data shows that theAIMS results correlate well with wafer printing. Itrequires the extra step of loading the mask, changinghardware settings, and capturing image for simulation.TeraSim software-based simulation achieves resultscomparable to AIMS system with inspection capturedimages as input. TeraSim is PC based software, and mustuse KLA-Tencor X-link™ software package to importreview images. TeraSim has the advantage that its usedoes not require any additional handling of the reticle.

AcknowledgementThe authors would like to acknowledge Kevin Rentzsch(DuPont Photomasks, Inc.) for his assistance in setupof KLA-Tencor CD SEM file of all 200-defect on themask; and Carl Siniard (DuPont Photomasks, Inc.) forhis support in collecting AIMS data.

A version of this article was presented at the 23rd AnnualBACUS Symposium on Photomask Technology,September 2003, Monterey, California, USA. Publishedin the 2003 BACUS Symposium proceedings Vol. 5256,pp. 1120-1129.

References1. L. Pang, B. Volk, J. X. Chen, et. al. “Simulation-based

Defect Printability Analysis on Alternating Phase ShiftingMasks for 193nm Lithography” Proc. SPIE Vol. 4889,pp. 947-954.

2. W. D. Kim, S. Akima, C. Aquino, and et. al. “Mask Inspection Challenges for 90nm and 130nm Device Technology Nodes: Inspection Sensitivity and PrintabilityStudy using SEMI Standard Programmed Defect Mask”Proc. SPIE Vol. 4889, pp. 972-983.

3. L. Zurbrick, J. Lee, and et. al. “Reticle programmed defectsize measurement using low voltage SEM and patternrecognition techniques” Proc. SPIE Vol. 3996, pp. 64-70.

4. V. Wiaux, V. Philipsen, R. Jonckheere, G. Vandenberghe,S. Verhaegen, T. Hoffmann, K. Ronse, W. Howard, W.Maurer, and M. Preil, “Assessment of OPC EffectivenessUsing Two-Dimensional Metrics,” Optical MicrolithographyXV, Proc., SPIE 4691.

Figure 9. IDM comparison for Row R, over-sized horizontal space.

60

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20

10

0

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nsit

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[%]

R1 R3 R5 R7 R9Defect Number for R-Series

TeraSim

AIMS Data Processed ThroughTeraSim

Figure 10. Simulated CD difference of AIMS and TeraSim versus SEM

measured CD difference for row K.

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Predicted CD Change TeraSIm [nm]CD Change Wafer SEM [nm]Predicted CD Change AIMS [nm]



KLA-Tencor’s eS30 receives SST’s WestWorldAttendees’ Choice Award for Best Solution to a

Problem. The eS30 overcomeselectrical defects in the produc-XXtion process, providingXXXXXXXchipmakers with electricaldefect monitoring strategiesXfor high-volume production,XXXXX

XXXXXwhich increases yields and ROI.XXXX

WestWorld Attendees’ Choice Award

KLA-Tencor won the “best solution to a problem”award at the wafer-processing portion ofSemicon West for its eS30 e-beam inspectionsystem. From left to right: Todd Henry, seniordirector of marketing, E-beam Inspection Div.;Bob Haavind, editor in chief, SST; Stan Yarbro,group VP of worldwide operations, CustomerGroup; and Ken Schroeder, CEO.

Best Solution To A Problem: KLA-Tencor’se-beam inspection system combinesspeed and sensitivity

The eS30 e-beam inspection system provides thethroughput and production worthiness requiredfor electrical line monitoring. The eS30 combinesspeed, sensitivity, and ease-of-use into a singleplatform for all phases of the IC technology life-cycle, enabling chipmakers to reap gains in yieldand fab ROI. Significant reductions in tool over-

head, including wafer loadingand set-up time, coupled withfaster scanning speed and ease-of-use enhancements, effectivelytriple the throughput of theeS30 compared to the manu-facturer’s eS20XP system toenable whole-wafer, high sensitivity inspection in underan hour for many applications.

P R O D U C T A W A R D S

Solid State Technology, September, 2003Copyright © 2003 — PennWell Corporation


Product NewsPROLITH v8.0 As feature sizes continue to shrink, lithography processes are being pushedto their limits. Lithography simulation essentially must solve complexproblems in both reticle and wafer manufacturing as lithographers pushexisting 248-nm and 193-nm technologies to smaller and smaller featuresizes through the use of increasingly complex techniques, such as off axisillumination, phase-shifted reticles, and double exposure processes. Thislevel of sophistication demands that simulation tools be accurate, versatile,easy to use, and fast in order to support decision making across a widerange of technologies, processes, and materials.

Leading the way in this critical emerging area of lithography managementis KLA-Tencor’s PROLITH software, the industry’s leading lithographysimulation tool. PROLITH’s optical lithography modeling capabilitiesenable customers to maximize yield, more rapidly implement new processesand technologies, and increase their lithography equipment utilization.

The newest PROLITH release, version 8.0, allows lithographers to be evenmore efficient in resolving lithography simulation problems. With a newmulti-measurement capability, lithographers can determine the best overallprocess settings, enabling creation of an overlapping process window thatsimultaneously accounts for all critical dimensions and measurements.PROLITH v8.0 enables measurement of up to 11 different locations on across-section and up to 22 additional, top-down dimensions with the PROLITH 3D option. These additional measurements take no additionalsimulation time. Additionally, metrology planes can be added or moved usinga table or by drawing or dragging on a graph. Whether measuring aerialimages, resist profiles, or anything in between, additional measurementinformation significantly helps shrink decision time. PROLITH v8.0 alsoincludes a simulation capability for liquid immersion lithography (LIL),enabling determination of the potential performance advantages of this newprocess technology in meeting specific device and technology requirements.

Other new features/benefits:• Quick viewing of full-chip GDSII or MEBES design files

• Evaluation of the impact of using a different polarization setting for eachpass on the exposure tool, which helps determine which exposure processgives the best lithography process results

• Measurement of features on diagonals or on any angle, optimizing totalfeature performance on today’s most advanced device layouts

• Metrology data along planes that do not start or stop at a simulation grid point. New flexibility assures necessary information from the exactlocation desired

• Wider range of template files allows designation of default PROLITHinput values so they correspond to common technology nodes, makingstarting point closer to actual process

• Improved PROLITH Programming Interface (PPI) documentation. PPI nowincludes low-level commands for working with multiple metrology planes

With PROLITH v8.0’s new multi-mea-

surement capability, lithographers can

determine best overall process settings.

PROLITH v8.0 can easily identify out-

of-spec features.

PROLITH v8.0 can create an overlap-

ping process window in one step that

simultaneously accounts for all critical

dimensions and measurements.

PROLITH v8.0 Benefits• Helps determine best overall

process settings

• Optimizes total feature perfor-mance on the most advanceddevice layouts

• Provides critical feature datafrom the exact location required

• Enables investigation of process andtechnology tradeoffs including LIL

• Provides faster analyses anddecisions with multi-measurementcapability


MetriX 100™ MetriX 100 is the industry’s first inline, non-contact metal films metrologysystem to provide independent measurements of film composition andthickness on product wafers. Controlling film composition and stoichiometryof new materials introduced in production of 90-nm and below devices isas important as controlling film thickness. With its versatile electron-beamtechnology, MetriX 100 leapfrogs current techniques, bringing a wellunderstood and proven technology to the production floor that, for the firsttime, enables chipmakers to address this new challenge. This system offersadvanced capabilities that meet thin film process control requirements forthe 90-nm and below nodes, including SiON gate dielectric, bi-layer TaN/Tabarrier seed, and ultra-thin atomic layer deposition (ALD) barrier films.

Utilizing electron beam stimulated x-ray technology (ESX), MetriX 100’selectron beam stimulates characteristic x-rays and quantifies the x-rayintensity into composition and film thickness data. MetriX 100 alsoreduces the use of monitor wafers to lower manufacturing costs throughsmall-spot measurements in the scribe line of product wafers. An easy-to-use UI enables fast, highly reliable measurements, while remote diagnosticsand support capabilities ensure high in-fab productivity. Providing highlyprecise non-contact films measurement on product wafers, MetriX 100incorporates the latest 300-mm advanced automation requirements, remotediagnostics, and the same user interface as the production-proven SpectraFx100 dielectric films metrology system.

MX 4.0 (Monitor eXpert) MX 4.0 software for KLA-Tencor’s Surfscan SP1 unpatterned wafer inspectionsystem enables the Surfscan SP1 tool to conduct defect detection andprocess monitoring in a single scan — providing a fast and cost-effectivealternative to many time-consuming and manual process-monitoring stepswith little additional overhead. MX 4.0 enhances existing software featuresand introduces three new major software options that provide the SP1 withnew inspection and process monitoring capabilities.

Haze normalization introduces the ability to match haze measurementsbetween SP1 systems. Haze analysis, a powerful software analysis feature,models and detects haze defects in the SP1 haze map. Brightfield sizingenables the SP1 to provide consistent brightfield inspection results fromtool to tool, taking this capability beyond engineering analysis to produc-tion worthy inspection. MX 4.0 also provides valuable new defect analysisand process monitoring capabilities for wafer and IC production thatimprove the SP1’s data reporting for backside inspection, haze measure-ments, and analysis and brightfield inspection.

MetriX 100

MX 4.0 brightfield scans allow

Surfscan SP1 to detect large-area

defects such as slurry burns during

wafer IQC.

USERS FORUM

LITHOGRAPHY

Sunday, February 22, 2004

6:00 - 9:00 pm

Keynote address by:Dr. Frank Schellenberg,

Mentor Graphics“What DFM Really Means”

Join us at KLA-Tencor’s 5 th annualLithography Users Forum.Featuring technical papers on advanced solutions for CD and overlay control, photocell monitoring,simulation techniques for immersion lithography

... and more.

Location: Techmart

Silicon Valley Room

5201 Great America Pkwy

Santa Clara, CA 95054

Register online at www.kla-tencor.com/spie

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