Spike anneal optimization for digital and analog high ... anneal optimization for digital. ... T=1113C is the best trade-off between Boron diffusion and activation. ... for both digital

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  • 1E.Josse and al. ESSDERC02 Firenze, Italy

    Spike anneal optimizationSpike anneal optimization for digitalfor digitaland analog highand analog high performance 0.13m performance 0.13m

    CMOSCMOS platformplatform

    E.E.JosseJosse, F.Arnaud, F., F.Arnaud, F.WacquantWacquant, D., D.LenobleLenoble, O., O.MenutMenut, E., E.RobilliartRobilliart

    STMicroelectronicsSTMicroelectronics, Central R&D, Crolles, France, Central R&D, Crolles, France

  • 2E.Josse and al. ESSDERC02 Firenze, Italy

    Outline

    Motivation for spike anneal

    Impact on 0.13 m pMOSFET

    Impact on 0.13 m nMOSFET

    CMOS optimization for digital and analog applications

    Conclusions

  • 3E.Josse and al. ESSDERC02 Firenze, Italy

    Motivation for spike anneal : thermal ramps profile

    350

    450

    550

    650

    750

    850

    950

    1050

    1150

    0 20 40 60 80

    Time (sec)

    Tem

    pera

    ture

    (C

    )Ramp-up

    Ramp-down

    Peak

    High peak temperature : maximize dopant activation

    Aggressive ramp-up : minimize dopant diffusion

    Aggressive ramp-down : minimize dopant deactivation

  • 4E.Josse and al. ESSDERC02 Firenze, Italy

    Motivation for spike anneal : simulated 2D MOSFET profiles

    Standard RTA : 1025C 15s Spike RTA at 1113C

    Simulated : 0.13 m pMOSFET with either a standard RTA (1025C 15s) or a spike RTA at 1113C

    motivation for spike RTA : reducing Boron diffusion

    challenge : optimizing the spike RTA temperature and ramps to obtain both reduced Boron diffusion and high level of Boron and Arsenic activation

  • 5E.Josse and al. ESSDERC02 Firenze, Italy

    Motivation for spike anneal : experimental

    Context : 0.13 m CMOS flow (Lg=0.11 m and tox=20)

    nMOS junction : As at 2 keV + double pocket (Indium + Bore)

    pMOS junction : BF2 at 4 keV + double pocket (Arsenic + Phosphorus)

    Demo done with an industrial Lamp-based RTP (AMAT CENTURA XE+)

    Various spike anneal T and ramps conditions are compared with a standard RTA 1025C 15s :

    XXXX1150C

    XXXX1113C

    XXXX1075C

    100 / 100 75 / 100 100 / 75 75 / 75 Ramp : up / down [C/s]

  • 6E.Josse and al. ESSDERC02 Firenze, Italy

    Outline

    Motivation for spike anneal

    Impact on 0.13 m pMOSFET

    Impact on 0.13 m nMOSFET

    CMOS optimization for digital and analog applications

    Conclusions

  • 7E.Josse and al. ESSDERC02 Firenze, Italy

    Impact on 0.13 m pMOSFET : Vt-L plots

    -0.7

    -0.65

    -0.6

    -0.55

    -0.5

    -0.45

    -0.4

    -0.35

    -0.30.1 1 10

    Lg [m]

    Vt [V

    ]

    75/75 75/100100/75 100/100

    ramp (up and down) slope in C/s

    1113C

    1150C

    RTA 1025C 15s

    1075C

    1st order player is temperature :

    Aggressive ramps are not required

    Compared to reference RTA :

    T=1150C : SCE not corrected

    T=1075C : SCE inverted = RSCE

    T=1113C : flat Vt-L profile

    Major impact of the final RTA temperature on Vt-L plots at pMOS side :

    Boron diffusion is driven by the spike temperature

  • 8E.Josse and al. ESSDERC02 Firenze, Italy

    Impact on 0.13 m pMOSFET : Boron activation

    10

    100

    1000

    1000 1025 1050 1075 1100 1125 1150 1175 1200

    spike temperature [C]

    sq. r

    esis

    tanc

    e [o

    hm/s

    q]

    P+ S/D extension

    P+ deep S/D

    P+ poly gate

    1025C 15s

    Boron activation

    No impact from ramp-up and down

    (not presented here)

    Compared to reference RTA :

    T=1150C : higher B activation

    T=1075C : lower B activation

    T=1113C : same B activation

    Major impact of final RTA temperature step on Boron activation :

    T=1113C is the best trade-off between Boron diffusion and activation

  • 9E.Josse and al. ESSDERC02 Firenze, Italy

    Impact on 0.13 m pMOSFET : Boron penetration

    0.9

    0.91

    0.92

    0.93

    0.94

    0.95

    0.96

    -1.3 -1.25 -1.2 -1.15 -1.1

    Vgate [V]

    Cga

    te/C

    max spike 1113C

    spike 1075C

    spike 1150C

    RTA 1025C 15s

    C-V plot : zoom on gate depletion

    0.4

    0.45

    0.5

    0.55

    0.6

    0.65

    0.7

    0.8 0.85 0.9 0.95 1 1.05

    Vgate [V]

    Cga

    te/C

    max

    increased B penetration

    12

    34

    1. spike 1075C2. spike 1113C3. RTA 1025C 15s4. spike 1150C

    C-V plot : zoom on VFB shift

    Spike RTA 1113C compared to reference RTA 1025C 15s:

    Both gate depletion and Boron penetration reduced : improved gate stack

  • 10E.Josse and al. ESSDERC02 Firenze, Italy

    Outline

    Motivation for spike anneal

    Impact on 0.13 m pMOSFET

    Impact on 0.13 m nMOSFET

    CMOS optimization for digital and analog applications

    Conclusions

  • 11E.Josse and al. ESSDERC02 Firenze, Italy

    Impact on 0.13 m nMOSFET : Vt-L plots

    0.25

    0.27

    0.29

    0.31

    0.33

    0.35

    0.37

    0.39

    0.1 1 10Lg [m]

    Vt [

    V]

    75/75 75/100100/75 100/100

    ramp (up and down) slope in C/s

    1075C1113C

    1150CRTA 1025C 15s

    No significant impact of the final RTA on Vt-L plots at nMOS side :

    Arsenic diffusion is not driven by the spike temperature

  • 12E.Josse and al. ESSDERC02 Firenze, Italy

    Impact on 0.13 m nMOSFET : Arsenic activation

    10

    100

    1000

    1000 1025 1050 1075 1100 1125 1150 1175 1200

    spike temperature [C]

    sq. r

    esis

    tanc

    e [o

    hm/s

    q]

    N+ S/D extension

    N+ deep S/D

    N+ poly gate

    1025C 15s

    Arsenic activation

    No impact from ramp-up and down

    (not presented here)

    Compared to reference RTA :

    T=1150C : higher As activation

    T=1075C : lower As activation

    T=1113C : same As activation

    Major impact of final RTA temperature step on Arsenic activation :

    T=1150C is the best trade-off between Arsenic diffusion (none) and activation

  • 13E.Josse and al. ESSDERC02 Firenze, Italy

    Impact on 0.13 m nMOSFET : performance

    -9.5

    -9

    -8.5

    -8

    -7.5

    -7

    -6.5

    350 400 450 500 550 600 650 700 750Ion [A/m]

    Ioff

    [logA

    /m

    ]

    spike 1075Cspike 1113Cspike 1150CRTA 1025C 15s

    0.9

    0.91

    0.92

    0.93

    0.94

    0.95

    0.5 1 1.5

    Vgate [V]

    Cga

    te/C

    max

    spike 1113C

    spike 1075C

    spike 1150C

    RTA 1025C 15s

    Major impact of final RTA temperature step on performance :

    T=1150C : reduced gate depletion and enhanced performance T=1113C : gate depletion and performance are the same than with ref. RTA

  • 14E.Josse and al. ESSDERC02 Firenze, Italy

    Within wafer uniformity : full sheet Rs mapping

    RTA 1025C 15s Spike RTA at 1113C

    -95.0

    -65.0

    -35.0

    -5.0

    25.0

    55.0

    85.0

    95.0

    75.0

    55.0

    35.0

    15.0

    -5.0

    -25.

    0

    -45.

    0

    -65.

    0

    -85.

    0

    110.5111.2111.9112.6

    Rs map

    111.9-112.6

    111.2-111.9

    -95.0

    -70.0

    -45.0

    -20.0

    5.0

    30.0

    55.0

    80.0

    95.0

    75.0

    55.0

    35.0

    15.0

    -5.0

    -25.

    0

    -45.

    0

    -65.

    0

    -85.

    0

    110.7111.4112.1112.8113.5114.2

    Rs map

    113.5-114.2

    112.8-113.5

    112.1-112.8

    111.4-112.1

    1 color = 1C variation

    Activation uniformity is not significantly degraded when compared to thestandard RTA 1025C 15s, except on the extreme edge of the wafer

  • 15E.Josse and al. ESSDERC02 Firenze, Italy

    Outline

    Motivation for spike anneal

    Impact on 0.13 m pMOSFET

    Impact on 0.13 m nMOSFET

    CMOS optimization for digital and analog applications

    Conclusions

  • 16E.Josse and al. ESSDERC02 Firenze, Italy

    CMOS optimization : spike RTA selection

    nMOS pMOS

    =+=+1150C+===1113C

    ++-=-1075CdiffusionactivationdiffusionactivationTemp. [C]

    compared to reference RTA 1025C 15s : + better / = same / - worse

    1113C : CMOS optimum for SCE control enhancement

    1150C : CMOS optimum for performance enhancement

    Aggressive ramps not needed (1st order is temperature) : 75C/s is enough

  • 17E.Josse and al. ESSDERC02 Firenze, Italy

    CMOS optimization : device optimization (1/2)

    Device optimization : for both digital and analog applications

    Reference RTA 1025C 15s

    Digital (short channel)

    strong pocket dose neededpoor voltage gain (long channel)

    poor matching (short channel)

    Analog

    Spike RTA at 1113C

    Digital (short channel)

    low pocket dose neededimproved voltage gain (long channel)

    improved matching (short channel)

    Analog

  • 18E.Josse and al. ESSDERC02 Firenze, Italy

    CMOS optimization : device optimization (2/2)

    0

    20

    40

    60

    80

    100

    120

    140

    160

    180

    200

    0.1 1

    Lmask [m]

    gain

    As 4.2e13 + RTA 1025C 15sAs 1.9e13 + spike 1113CAs 2.2e13 + spike 1113CAs 2.5e13 + spike 1113CAs 2.8e13 + spike 1113C

    Vds=-0.6V and Vgt=-0.2V

    -0.6

    -0.55

    -0.5

    -0.45

    -0.4

    -0.35

    -0.3

    -0.25

    -0.20.1 1 10

    Lg [m]

    Vt [

    V]

    As 4.2e13 + RTA 1025C 15sAs 1.9e13 + spike 1113CAs 2.2e13 + spike 1113CAs 2.5e13 + spike 1113CAs 2.8e13 + spike 1113C

    Spike RTA at 1113C allows As pocket dose lightenning (from 4.2e13 to 1.9e13)