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Sparkk: Quality-Scalable Approximate Storage in DRAM
Jan Lucas, Mauricio Alvarez-Mesa, Michael Andersch and Ben Juurlink
Embedded Systems Architectures Group - TU Berlin
June 14, 2014
1
Introduction
I DRAM bitcells are leaky and need refreshing to keep the data
I Most bitcells can keep data for much longer time than the most leaky cells
I Not all data needs bit exact storage
I We can save power and/or gain performance by providing good enough storageinstead.
2
Motivation
I Refresh is projected to use almost half of the DRAM power within just the next 3device generations!1
I Capacity increase → more cells need refreshI Smaller bit cells → cells need to be refreshed more often
I Mobile devices can put CPUs and GPUs into sleep but still need continuousDRAM refresh
I Large parts of the stored data can tolerate imperfect storage
1Liu et al.: “RAIDR: Retention-Aware Intelligent DRAM Refresh” ISCA ’2012
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Flikker
Liu et al.:“Flikker: Saving DRAM Refresh-power through Critical Data Partitionin”ASPLOS ’2011
I Reduce refresh in one part of the memory
I Provide more power efficient storage
I But only for ”non-critical” data.
I Images, sounds, etc.
I Good idea, but we can do better! → Let’s see how!
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Different significances
10% of all MSBs flipped 10% of all LSBs flipped
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Most DRAM Interfaces use multiple chips
CPU
DRAM0
DRAM1
DRAM2
DRAM3
8-bit
8-bit
8-bit
8-bit
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Most DRAM Interfaces use multiple chips
Flikker
CPU
3s refresh0.16% bits fail
3s refresh0.16% bits fail
3s refresh0.16% bits fail
3s refresh0.16% bits fail
8-bit
8-bit
8-bit
8-bit
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Use different refresh rates on the different chips!
Sparkk
CPU
15.42s refresh8.7% bits fail
5.63s refresh0.98% bits fail
2.69s refresh0.11% bits fail
1.41s refresh0.01% bits fail
8-bit
8-bit
8-bit
8-bit
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Conventional Mapping of Bytes to DRAM
01234567012345670123456701234567
01234567012345670123456701234567
DRAM chip 0DRAM chip 1DRAM chip 2DRAM chip 3
Byte 0Byte 1Byte 2Byte 3
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Permutation
01234567012345670123456701234567
01234567012345670123456701234567
DRAM chip 0DRAM chip 1DRAM chip 2DRAM chip 3
Byte 0Byte 1Byte 2Byte 3
9
Permutation
01234567012345670123456701234567
01234567012345670123456701234567
DRAM chip 0DRAM chip 1DRAM chip 2DRAM chip 3
Byte 0Byte 1Byte 2Byte 3
9
Permutation
01234567012345670123456701234567
01234567012345670123456701234567
DRAM chip 0DRAM chip 1DRAM chip 2DRAM chip 3
Byte 0Byte 1Byte 2Byte 3
9
Permutation
01234567012345670123456701234567
01234567012345670123456701234567
DRAM chip 0DRAM chip 1DRAM chip 2DRAM chip 3
Byte 0Byte 1Byte 2Byte 3
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Quality Results
0 10 20 30 40 50 60 70 80 90
100
1 10 100
PS
NR
[dB
]
Average refresh period[s]
Sparkk 8Sparkk 4Sparkk 2
Flikker
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Comparison
Flikker(8s) Sparkk(8s)
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More information in the paper!
I Choosing optimal refresh rates for the different memory chips
I How to refresh different chips from the same rank at different rates
I Managing memory areas with different refresh requirements
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