Chapter – 3

SPACE VECTOR PULSE WIDTH MODULATION BASED

ALGORITHMS FOR MULTILEVEL INVERTERS

3.1 INTRODUCTION

Three-level inverter topology being widely used in high

voltage/high power applications due to its high voltage handling and

good harmonic rejection capabilities with currently available power

devices. In the previous chapters, the space vector pulse width

modulation scheme for two-level inverter is described in detail. But

the three-level inverter has nearly four times better in harmonic

content compared with two-level topology. The harmonic contents of

the output voltage are fewer than those of two-level inverter at the

50

same switching frequency. In addition, blocking voltage of each

switching device is a half of the dc link voltage, it is easy to realize

high voltage and large capacity inverter system.

In this chapter, at first the space vector pulse width modulation

(SVPWM) algorithm for a three-level inverter fed induction motor is

presented and analyzed, then a novel approach for generation of space

vector PWM for multilevel inverter based on fractals has been

proposed and applied for three-level and five-level inverters. The first

proposed SVPWM algorithm provides high safety voltages with less

harmonic components compared to two-level structures and reduces

the switching losses by limiting the switching to two thirds of the

pulse duty cycle. The voltage vector selection procedure, switching

time calculation and switching pattern generation for three-level

inverter are described in detail. This space vector pulse width

modulation algorithm contributed for the reduction of switching power

losses and proved the advantages of three-level inverter that carryout

voltage with contents of less harmonic injection than two-level

inverter. The proposed method can be applied to the multilevel

inverters above the three-level. But, as the level of inverter increases,

the sector identification and switching vector determination and

dwelling time calculation becomes more complex. The computational

complexity and the execution time increases.

The second proposed method for the generation of space vector

PWM for multilevel inverter based on fractals reduces the algorithm

complexity and execution time. This SVPWM method using the fractal

51

approach is motivated from the fact that the switching vector

representation of any multilevel inverter has an inherent fractal

structure, with the basic unit of this structure being the triangle

formed by the vertices of three adjacent inverter voltage space vectors.

As the number of levels increases, it can be viewed that each sector

gets further divided into smaller triangular regions or sectors.

The present work is pivoted on this idea, and an algorithm is

also proposed for generating the sectors of higher level inverter from

the triangular regions of an equivalent two-level inverter. The

proposed method uses simple arithmetic for determining the sector

and does not require look up tables, hence fractal approach is applied

for multilevel inverters using SVPWM. The implementation of space

vector pulse width modulation involves:

(i) Identification of the sector in which the tip of the reference vector

lies.

(ii) Determination of the three nearest voltage space vectors.

(iii) Determination of the duration of each of these switching voltage

space vectors.

(iv) Choosing an optimized switching sequence.

The sector identification can be done by using coordinate

transformation of the reference vector into a two dimensional co-

ordinate system. The sector can also be determined by resolving the

reference phase vector along a, b and c axes and by repeated

comparison with discrete phase voltages. After identifying the sector,

the voltage vectors at the vertices of the sector are to be determined.

52

Once the switching voltage space vectors are determined the switching

sequences can be obtained. The calculation of the duration of the

voltage vectors can be simplified by mapping the identified sector to

corresponding to a sector of two-level inverter. To obtain optimum

switching, the voltage vectors are to be switched for their respective

durations, in a sequence such that only one switching occurs as the

inverter moves from one switching state to another. Conventional

techniques involve look up tables for achieving this optimum

switching sequence.

3.2 SVPWM FOR THREE-LEVEL INVERTER

3.2.1 Three-level Inverter Topology and Switching states

Fig. 3.1 shows a schematic diagram of a three-level inverter.

Each phase of the inverter consists of two clamping diodes, four

IGBTs and four free wheeling diodes. Since three kinds of switching

states and terminal voltages exist in each phase, the three-level

inverter has 27(33) switching states. Fig. 3.2 shows the

representation of the space voltage vectors for output voltage and

the space vector diagram of all switching states, where the P, O, N

represent terminal voltage respectively, that is Vdc/2, 0, -Vdc/2.

According to the magnitude of the voltage vectors, we divide them

into four groups; zero voltage vector (V0), small voltage vectors (V1,

V4, V7, V10, V13, V16), middle voltage vectors (V3, V6, V9, V12, V15, V18)

and large voltage vector (V2, V5, V8, V11, V14, V17). The zero voltage

53

vector (ZVV) has three switching states, small voltage vector (SVV)

has two switching states, the middle voltage vector (MVV) and large

voltage vector (LVV) have only one switching state.

Fig. 3.1 Schematic diagram of three-level inverter.

Table 3.1 Switching states of three-level inverter

Switching Symbols

Switching Conditions Output Voltage (Vao)S11 S12 S13 S14

P ON ON OFF OFF +Vdc/2O OFF ON ON OFF 0N OFF OFF ON ON -Vdc/2

Fig. 3.2 Space vector diagram of three-level inverter.

POOONN

POPONO

OOPNNO

OPPNOO

OPONON

PPPOOONNN

PPOOON

PNN

PON

PPNOPNNPN

NPO

NPP

NOP

NNP ONP PNP

PNO

54

3.2.2 Voltage Vectors and Calculation of Switching Times

Fig. 3.3 shows the triangle formed by the voltage vectors V0, V2

and V5. This triangle is divided into four small triangles 1, 2, 3 and 4.

In the space voltage vector PWM, generally, output voltage vector is

formed by its nearest three vectors in order to minimize the harmonic

components of the output voltage and the current. The duration of

each vector can be calculated by vector calculation. For instance, if

the reference voltage vector falls into the triangle 3, the duration of

each voltage vector can be calculated by the following equations.

Fig. 3.3 Voltage vectors of three-level inverter in sector-I.

Srefc4b3a1 TVTVTVTV =++ (3.1)

Scba TTTT =++ (3.2)

θππ

==== jrefjj

VeVVeVVeVVV ;21;

23;

21 3

46

31 (3.3)

Substituting Eq. (3.3) in Eq. (3.1) and in trigonometric form

V0

V4

Ta

V1

V3

V2

Ta T

a

Ta

Tb T

b

Tb

Tb

TcT

c

Tc

Tc

4

321

θ

Vref

V5

55

scba jVTj3cosV.Tj

6cosVV.T

21 T.)θnisθsoc( +=

π+π+

π+π+ .

3sin

21

6sin.

23

(3.4)

Separating real and imaginary parts from Eq. (3.4)

scba TVTTT ).(cos).3(cos

21).

6(cos

23.

21 θ=π+π+ (3.5)

scb TVTT ).(sin).3(sin

21).

6(sin

23 θ=π+π (3.6)

The values of Ta, Tb and Tc by solving Eq. (3.2), Eq. (3.5) and Eq. (3.6)

( )[ ]θ2ksin1TΤ sa −= (3.7) ( )[ ]1−+= 60θ2ksinTΤ sb (3.8)

( )[ ]1+−= 60θ2ksinTΤ sc (3.9)

Where Vk 32=

In other regions (1, 2, 4), duration for each voltage vector can be

calculated in the same way. Table 3.2 shows the switching times of

voltage vector in sector-I. The switching states of different sections of

three-level inverter are shown in Table 3.3.

Table 3.2 Switching times of three-level inverter

Region Ta Tb Tc1 2kTs sin(60-θ) Ts[1-2ksin(θ+60)] 2kTs sin(60-θ)2 2Ts[1-ksin(θ+60)] 2kTs sinθ Ts[2ksin(60-θ)-1]3 Ts[1-2ksinθ] Ts[2ksin(θ+60)-1] Ts[2ksin(θ-60)+1]4 Ts[2ksinθ-1] 2kTs sin(60-θ) 2Ts[1-ksin(θ+60)]

3.2.3 Optimized Switching Sequence

56

Fig. 3.4 Switching pattern for three-level inverter.

Table 3.3 Switching states of three-level inverter

Section Samples States Switching States

1.2

1 5-17-16-4 POO-PON-PNN-ONN2 4-16-17-5 0NN-PNN-PON-POO3 5-17-16-4 POO-PON-PNN-ONN

1.3 4 4-7-17-5 0NN-OON-PON-POO

1.4

5 6-18-17-7 PPO-PPN-PON-OON6 7-17-18-6 OON-PON-PPN-PPO7 6-18-17-7 PPO-PPN-PON-OON8 7-17-18-6 OON-PON-PPN-PPO

2.2

9 6-18-19-7 PPO-PPN-OPN-OON10 7-19-18-6 OON-OPN-PPN-PPO11 6-18-19-7 PPO-PPN-OPN-OON

2.3 12 9-19-7-8 OPO-OPN-OON-NON

2.4

13 9-19-20-8 OPO-OPN-NPN-NON14 8-20-19-9 NON-NPN-OPN-OPO15 9-19-20-8 OPO-OPN-NPN-NON16 8-20-19-9 NON-NPN-OPN-OPO

3.2

17 9-21-20-8 OPO-NPO-NPN-NON18 8-20-21-9 NON-NPN-NPO-OPO19 9-21-20-8 OPO-NPO-NPN-NON

3.3 20 11-8-21-10 NOO-NON-NPO-OPP

V2

V17

V15

18

6, 7

16

17

27

262524

23

22

21

20 19

10, 11 1, 2,3

12, 13

8, 9

4, 5

14, 15

Ta

Tb

TcTa

Ta

Tc

Tb

Ta

Tc

Tb

Tb

Tc

Ta

Ta

Ta

TbTc

Tc

Tb

57

Section Samples States Switching States

3.4

21 5-17-16-4 OPP-NPP-NPO-NOO22 4-16-17-5 NOO-NPO-NPP-OPP23 5-17-16-4 OPP-NPP-NPO-NOO24 4-16-17-5 NOO-NPO-NPP-OPP

4.2

25 10-22-23-11 OPP-NPP-NOP-NOO26 11-23-22-10 NOO-NOP-NNP-OPP27 10-22-23-11 OPP-NPP-NOP-NOO

4.3 28 12-23-11-13 OPP-NOP-NOO-NNO

4.4

29 12-23-24-13 OPP-NOP-NNP-NNO30 13-24-23-12 NNO-NNP-NOP-OPP31 12-23-24-13 OPP-NOP-NNP-NNO32 13-24-23-12 NNO-NNP-NOP-OPP

5.2

33 12-25-24-13 OOP-ONP-NNP-NNO34 13-24-25-12 NNO-NNP-ONP-OOP35 12-25-24-13 OOP-ONP-NNP-NNO

5.3 36 12-25-15-13 OOP-ONP-ONO-NNO

5.4

37 14-26-25-15 POP-PNP-ONP-ONO38 15-25-26-14 ONO-ONP-PNP-POP39 14-26-25-15 POP-PNP-ONP-ONO40 15-25-26-14 ONO-ONP-PNP-POP

6.2

41 14-26-27-15 POP-PNP-PNO-ONO42 15-27-26-14 ONO-PNO-PNP-POP43 14-26-27-15 POP-PNP-PNO-ONO

Section Samples States Switching States6.3 44 5-27-15-4 POO-PNO-ONO-ONN

6.4

45 5-27-16-4 POO-PNO-NPO-NOO46 4-16-27-5 NOO-NPO-PNO-POO47 5-27-16-4 POO-PNO-NPO-NOO48 4-16-27-5 NOO-NPO-PNO-POO

3.2.4 Results and Discussions

To verify the proposed space vector pulse width modulation

algorithm, simulation studies have been carried out for two-level

inverter and three-level inverter fed induction motor. The simulation

parameters of induction motor used in this method are given in

Appendix-I.

58

The simulation results for two-level inverter are shown in Fig.

3.5 to Fig. 3.11. The gate pulses and pole voltages of two-level inverter

are shown in Fig. 3.5 and Fig. 3.6. The phase voltage and line voltages

of two-level inverter are shown in Fig. 3.7 and Fig. 3.8. The d-axis and

q-axis stator currents of two-level inverter fed induction motor are

shown in Fig. 3.9. The torque, speed and flux responses for two-level

inverter fed induction motor are shown in Fig. 3.10, for a load torque

(TL) of 10.32 N-m. The output line voltage and its harmonic spectrum

are shown in Fig. 3.11.

For the same conditions Fig. 3.12 to Fig. 3.18 gives the results

for three-level inverter fed induction motor. Fig. 3.12 and Fig. 3.13

show the gate pulses and pole voltages of three-level inverter. The

phase voltages and line voltages of three-level inverter are shown in

Fig. 3.14 and Fig. 3.15. The d-axis and q-axis stator currents of three-

level inverter fed induction motor are shown in Fig. 3.16. The torque,

speed and flux responses for three-level inverter fed induction motor

are shown in Fig. 3.17, for a load torque (TL) of 10.32 N-m. The output

line voltage and its harmonic spectrum are shown in Fig. 3.18. The

Table 3.4 and Table 3.5 show the comparison between two-level

inverter and three-level inverter performance.

Fig. 3.11 and Fig. 3.18 show the output line voltage harmonic

spectrum of two-level and three-level inverters. From these figures it is

observed that the increase in level of inverter improves the output

voltage waveform and reduce the total harmonic distortion. The

improvement in torque, speed and flux responses with the level of

59

inverter are shown in Fig. 3.10 and Fig. 3.11. The Table 3.4 shows the

improvement of speed, peak value of output voltage fundamental

component and reduction of THD of two-level and three-level

inverters. Table 3.5 shows that as the modulation index increases, the

fundamental value of output voltage increases and at the same time

total harmonic distortion decreases.

The interpretation of all the results shows that in case of the

three-level inverter, the output voltage, speed and torque responses

are considerably improved and a reduction in torque ripples and total

harmonic distortion.

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10

0.5

1

Gat

e pu

lses

ga,

gb,

gc

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10

0.5

1

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10

0.5

1

Time(s)

Fig. 3.5 Gate pulses of two-level inverter.

60

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10

100

200

300

400

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10

100

200

300

400

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10

100

200

300

400

Time (s)

Pol

e vo

ltage

s V

ao, V

bo, V

co (

V)

Fig. 3.6 Pole voltages of two-level inverter.

0 0 .0 1 0 .0 2 0 .0 3 0 . 0 4 0 . 0 5 0 .0 6 0 . 0 7 0 . 0 8 0 .0 9 0 .1

- 2 0 0

0

2 0 0

0 0 .0 1 0 .0 2 0 .0 3 0 . 0 4 0 . 0 5 0 .0 6 0 . 0 7 0 . 0 8 0 .0 9 0 .1

- 2 0 0

0

2 0 0

0 0 .0 1 0 .0 2 0 .0 3 0 . 0 4 0 . 0 5 0 .0 6 0 . 0 7 0 . 0 8 0 .0 9 0 .1

- 2 0 0

0

2 0 0

T i m e ( s )

Pha

se v

olta

ges

Van,

Vbn

, Vcn

(V)

Fig. 3.7 Phase voltages of two-level inverter.

61

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-400

-200

0

200

400

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-400

-200

0

200

400

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-400

-200

0

200

400

Time (s)

Line

vol

tage

s V

ab, V

bc, V

ca (

V)

Fig. 3.8 Line-to-line voltages of two-level inverter.

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-100

-50

0

50

100

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-100

-50

0

50

100

Time (s)

Sta

tor

curr

ents

Id, I

q (A

)

Fig. 3.9 Stator currents of two-level inverter fed induction motor.

62

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-50

0

50

100

Tor

que

(N-m

)

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-500

0

500

1000

1500

Spe

ed (

rpm

)

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10

0.25

0.5

Time (s)

Flu

x (w

b)

Fig. 3.10 Torque, speed and flux responses of two-levelinverter fed induction motor.

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08-400

-200

0

200

400

Time (s)

FFT window: 5 of 50 cycles of selected signal

0 1000 2000 3000 4000 50000

20

40

60

80

100

Frequency (Hz)

Fundamental (50Hz) = 267.6 , THD= 54.02%

Mag

(%

of F

unda

men

tal)

Fig. 3.11 Output line voltage and its harmonic spectrumof two-level inverter.

63

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-1

0

1

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-1

0

1

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-1

0

1

Time (s)

Gat

e pu

lses

ga,

gb,

gc

Fig. 3.12 Gate pulses of three-level inverter.

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-200

0

200

Pol

e vo

ltage

s V

ao, V

bo, V

co (

V)

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-200

0

200

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-200

0

200

Time (s)

Fig. 3.13 Pole voltages of three-level inverter.

64

0 0 .0 1 0 .0 2 0 .0 3 0 .0 4 0 .0 5 0 .0 6 0 .0 7 0 .0 8 0 .0 9 0 .1-2 0 0

0

2 0 0

0 0 .0 1 0 .0 2 0 .0 3 0 .0 4 0 .0 5 0 .0 6 0 .0 7 0 .0 8 0 .0 9 0 .1-2 0 0

0

2 0 0

0 0 .0 1 0 .0 2 0 .0 3 0 .0 4 0 .0 5 0 .0 6 0 .0 7 0 .0 8 0 .0 9 0 .1-2 0 0

0

2 0 0

T im e (s )

Pha

se v

olta

ges

Van

, Vbn

, Vcn

(V)

Fig. 3.14 Phase voltages of three-level inverter.

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1

-400

-200

0

200

400

Line

vol

tage

s V

ab, V

bc, V

ca (

V)

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1

-400

-200

0

200

400

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1

-400

-200

0

200

400

Time (s)

Fig. 3.15 Line-to-line voltages of three-level inverter.

65

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-100

-50

0

50

100

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-100

-50

0

50

100

Time (s)

Sta

tor

curr

ents

Id, I

q (A

)

Fig. 3.16 Stator currents of three-level inverterfed induction motor.

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-50

0

50

100

Tor

que

(N-m

)

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

0

500

1000

1500

Spe

ed (

rpm

)

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10

0.25

0.5

Time (s)

Flu

x (w

b)

Fig. 3.17 Torque, speed and flux responses of three-levelinverter fed induction motor.

66

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08-400

-200

0

200

400

Time (s)

FFT window: 5 of 50 cycles of selected signal

0 1000 2000 3000 4000 50000

20

40

60

80

100

Frequency (Hz)

Fundamental (50Hz) = 268.6 , THD= 28.60%

Mag

(%

of F

unda

men

tal)

Fig. 3.18 Output line voltage and its harmonic spectrum of three-level inverter.

3.2.4.1 Analysis of Two-level and Three-level Inverters

From simulation results, the analysis has been made on the

performance of two-level and three-level inverters. It shows the

effectiveness of three-level inverter than two-level inverter in terms of

rotor speed of induction motor and total harmonic distortion as shown

in Table 3.4. From Table 3.5 it is clear that as the modulation index

increases, the total harmonic distortion decreases.

Table 3.4 Performance of two-level and three-level inverters

Parameters Two-level inverter Three-level inverter

67

Input dc voltage 300V 300VSpeed 1442rpm 1443rpmT.H.D 54.02% 28.60%

Peak value of

fundamental Harmonic

267.6V 268.6V

Switching frequency 2400Hz 2400Hz

Table 3.5 Performance of inverters with respect to modulation index

Modulation Index (m)

Two-level VSI Three-level VSIFundamental

Peak voltage

(V)

THD% Fundamental

Peak voltage

(V)

THD%

0.7 236.3 73.47 237 33.880.75 251.9 67.09 253.7 31.340.8 267.6 54.02 268.6 28.600.86 269 51.52 270.7 26.51

3.3 SPACE VECTOR PULSE WIDTH MODULATION FOR

MULTILEVEL INVERTERS USING FRACTAL APPROACH

The space vector representation of a higher level inverter can be

conceived as generated from the space vector representation of two-

level inverter, wherein the sectors of two-level inverter get

progressively divided and subdivided. The basic structure, a triangle

(sector) is transformed by further dividing itself into smaller triangles.

A basic structure that evolved by dividing itself into structures similar

to it which has an associated fractal. The switching voltage space

vector representation of multilevel inverters also has an associated

fractal. In fractal theory, the basic triangle is divided into four smaller

triangular regions, joined by the midpoints of the sides of the triangle.

3.3.1 Inherent Fractal Structure of Multilevel Inverter

68

Fig. 3.19 explains the voltage space vectors of two-level inverter.

The voltage space vector locations for a three-level inverter are shown

in Fig. 3.20, where A00, A01. A02, A03, A04, A05 and A06 are same as

locations of voltage space vectors of two-level inverter. Consider the

region marked 1 in the case of two-level inverter, formed by the

vectors located at A00, A01 and A02. In the case of three-level inverter,

this region has three additional voltage space vectors as shown in

Fig.3.20. It can be observed that the three additional voltage space

vectors are located at the midpoints of each side of the sector of

equivalent two-level inverter. The three additional switching voltage

space vectors together with switching voltage space vectors located at

A00, A01, and A02 results in four sectors within (sector-I) A00,A01,A02 of

three-level inverter.

Fig. 3.19 Voltage space vectors of two-level inverter.

A06

A01

A02A03

A04

A05

1

6

5

4

3

2

A00

69

Fig. 3.20 Voltage space vectors of three-level inverter.

Fig. 3.21 Voltage space vectors of five-level inverter by inherent fractal structure.

Considering the triangular region formed by the space vectors

located at A00, A01, and A02, besides the voltage space vectors of three-

level inverter, nine additional voltage space vectors are present as

shown in Fig. 3.21. The nine additional vectors are located at A21, A22,

A01A11A00

A02

A05

A03

A06

A04

A12 A13

A27

A12

A23

A26

A22

A25

A24

A21

A00

A11

A03 A02

A01

A05

A06

A04

A13

A29

A28

70

A23, A24, A25, A26, A27, A28, and A29. It can be clearly observed that the

nine additional vectors are located at the midpoints of the sides of

sectors of three-level inverter. The nine additional vectors together

with the voltage space vectors of three-level inverter results in 16

sectors within (sector-І) ΔAooAo1A02 of five-level inverter. In this manner,

each sector in the voltage space vector representation of an equivalent

two-level inverter is divided into four smaller sectors, resulting in

voltage space vector locations of three-level inverter. Each of the

sectors of three-level inverter is further divided into four smaller

sectors resulting in switching space vectors of five-level inverter. This

process gets repeated for generation of space vectors of higher level

inverters.

3.3.2 SVPWM Algorithm using the Fractal Approach

This algorithm explains the procedure to adapt the space vector

pulse width modulation for multilevel inverters using the fractal

approach. They are

1. Three phase (a,b,c) to two phase (d,q) transformation.

2. Identify the sector in which the tip of the reference vector

located.

3. Determine of three nearest voltage vectors.

4. Perform the triangularisation algorithm.

5. Calculate and compare the centroids of each triangle with the

reference vector.

6. For the higher level implementation of fractal approach, perform

triangularisation algorithm till the reference vector is nearer to

71

centroid of respective triangle on which triangularisation is to be

performed using Eq. (3.12) to Eq. (3.14).

7. Switching states are obtained using Eq. (3.15) to Eq. (3.17).

8. Switching time durations are calculated, taking the basic two-

level timings into consideration.

9. Optimized switching sequence is calculated by a). Taking the

virtual zero vectors, b). Eliminating the redundant switching states

and c). Considering optimum switching where only one switching is

involved as the inverter changes from one state to another.

3.3.2.1 Three phase (a, b, c) to two phase (d, q) Transformation

The three phase quantities can be transformed to their

equivalent two phase quantity either in synchronously rotating frame

(or) stationary frame. From this two-phase component the reference

vector magnitude can be found and used for modulating the inverter

output.

The three phase sinusoidal voltage components are

tVV ma ω= sin

tVV mb

π−ω=

32sin

π+ω=

32sin tVV mc (3.10)

The magnitude and angle of the rotating vector can be found by

means of Clark’s Transformation. Then, the (d, q) co-ordinates of the

corresponding space vector can be obtained as

72

( )ad VV 23=

( )cbq VVV −= 23

(3.11)

3.3.2.2 Location of the Reference Voltage Vector

The identification of sector in which the tip of reference vector

lies can be done using coordinate transformation of the reference

vector into a two dimensional coordinate system. The sector can also

be determined resolving the reference phase vector along a, b and c

axes and repeated comparison with discrete phase voltages.

Fig. 3.22 Location of the reference vector in two-level inverter.

After identifying the sector, the voltage vectors at the vertices of

the sector are to be determined. This can be done by the comparison

of reference angle with sector angle; Fig. 3.22 depicts SVPWM with six

sectors in (d, q) reference frame with as the reference angle.

If the reference angle

< 60°, reference vector is in sector 1

60° <

120°<

3.3.2.3 Determination of Nearest Three Voltage Vectors

The space vector voltage located in hexagon surrounded by

different states of the inverter which gives different voltage

magnitudes of the output voltage. These inverter states are nothing

but the ON/OFF states of the devices. After identifying the sector in

which the tip of reference vector is located, the voltage vectors of this

sector are determined to find out the three nearest voltage vectors of

space vector voltage Vref. In order to obtain these three nearest voltage

vectors, first the region in which the space vector voltage lies to be

determined.

If the reference vector lies in sector-I, the three nearest vectors

are determined by comparison of reference angle. If reference angle

Fig. 3.24 Triangularisation of two-level inverter in sector-I.

The following steps are involved to perform the triangularisation;

• Determine the sector on which the triangularisation is to be

performed.

• Determine the midpoints of each side of the sector by Eq. (3.12) to

Eq. (3.14). These are the co-ordinates of the three new vectors

which will divide the sector into four smaller, but similar triangular

regions.

• Determine the inverter states corresponding to these vectors using

Eq. (3.15) to Eq (3.17).

For example, consider region I of the two-level inverter formed

by vertices A00, A01 and A02. The co-ordinates of three vertices are

(00,β00), (01,β01) (02,β02) respectively. The co-ordinates of the three new

voltage space vectors located at A1l, A12 and A13 as shown in Fig. 3.38

can be obtained from the co-ordinates of A00, A 01and A 02

Co-ordinates of A11 are

( )010011 21 α+α=α

( )010011 21 β+β=β (3.12)

1

3

42

76

Co-ordinates of A12 are

( )020012 21 α+α=α

( )020012 21 β+β=β (3.13)

Co-ordinates of A13 are

( )020113 21 α+α=α

( )020113 21 β+β=β (3.14)

Fig. 3.25 Sector-I of two-level inverter.

Fig. 3.26 First triangularisation of two-level inverter.

The associated switching vector states can also be determined

in a similar manner. The inverter switching states correspond to the

voltage space vector located at A00, A01 and A02 are (a0 b0 c0), (a1 b1 c1)

and (a2 b2 c2) respectively. The switching states of the new voltage

Sector-I

A 01

(α01,

β01

)(a

1 b

1 c

1)

A 02

(α02,

β02

)(a

2 b

2 c

2)

A 00

(α00,

β00

)(a

0 b

0 c

0)

2

A 13

(α13,

β13

)(a

5 b

5 c

5)

A 12

(α12,

β12

)(a

4 b

4 c

4)

A 11

(α11,

β11

)(a

3 b

3 c

3)

A 01

(α01,

β01

)(a

1 b

1 c

1)

A 00

(α00,

β00

)(a

0 b

0 c

0)

A 02

(α02,

β02

)(a

2 b

2 c

2)

77

space vectors at A1l (a3 b3 c3), A12 (a4 b4 c4) and A13 (a5 b5 c5) can be

obtained as

( )103 21 XXX += (3.15)

( )204 21 XXX += (3.16)

( )125 21 XXX += (3.17)

where ‘X’ takes a, b and c for the respective phases.

The Eq. (3.12) to Eq. (3.14) represents the arithmetic procedure

used in the proposed method for dividing a triangular region (sector)

into four similar regions, by generating three additional vectors

situated at the mid points of the sides forming the original triangular

region. This is referred the triangularisation algorithm.

In order to generate sectors of higher level inverter by

progressively dividing sectors of two-level inverter, the

triangularisation algorithm is repeatedly applied. In the fractal theory,

algorithms whose repeated iterations will result in the pattern to grow

or evolve, are referred an iterated function system, the repeated

iteration of triangularisation algorithm will grow the inherent fractal

structure in space vector representation of multilevel inverters.

Therefore, the triangularisation algorithm can be viewed as the

iterated function system for this fractal structure.

3.3.2.5 Comparison of Reference Vector with the Centroid

The location of the tip of the reference voltage space vector from

among these four triangular regions is found by determining the

region whose centroid is the closest to the tip of reference space

78

vector. The co-ordinates of the centroid of an equilateral triangle can

be determined as the average of co-ordinates of the three vertices. For

an equilateral triangle with the co-ordinates of the vertices as (1,β1),

(2, β2), (3, β3), co-ordinates of the centroid (cent ,βcent) are given by

( )32131 α+α+α=αcent

( )32131 β+β+β=βcent (3.18)

Fig. 3.27 Triangularisation of sector-I of equivalent three-level inverter.

The triangle with centroid closest to tip of reference space vector

is ΔA11, A12 AI3. The triangularisation algorithm has to be applied once

again in case of five-level inverter. The application of Eq. (3.12) to Eq.

(3.14) to ΔA11A12AI3 will generate further three new voltage space

vectors A23, A25, A26 and also the inverter states corresponding to these

new voltage vectors. Thus, the three-level inverter space vector

diagram is further divided into four smaller triangles for a five-level

inverter space vector diagram as shown in Fig. 3.27.

A00 A01

A02

A28

A21

A22

A23

A25

A24

A26

A27

A11

A12

A29

A13

79

From these four triangles, one triangle enclosing the reference

space vector is chosen such that its centroid is the closest to tip of

reference space vector. The sector is identified and the inverter states

corresponding to the switching vectors located at the vertices of the

identified sector are also generated simultaneously.

3.3.2.6 Calculation Of Switching Times

The switching time durations are calculated, taking the basic

two-level timings into consideration, as these can be extended to N-

level. The switching voltage vectors approximate the volt-second of the

reference space vector by operating for specific durations. The

determination of the duration of operation of the switching voltage

space vectors is simplified by mapping the sector that is identified to

enclose the reference space vector to a sector of two-level inverter.

The switching time durations of the vectors can be determined

using the following formulae from Eq. (3.19) to Eq. (3.22).

( )( )( )O

OmT60sin60sin

1α−×= (3.19)

( )( )( )O

OmT60sin

60sin2

×= (3.20)

210 TTTT S −−= (3.21)

where dc

sr

V

Vm

=

32 (3.22)

3.3.2.7 Concept of Virtual Zero

80

According to the magnitude of the voltage vectors, they are

divided into four groups as the zero voltage vectors (ZVV), the small

voltage vectors (SVV), the middle voltage vectors (MVV) and the large

voltage vectors (LVV). Both zero voltage vectors and small voltage

vectors have redundant switching states. The mapping is done by

choosing one of the three vectors of the identified sector to coincide

with the actual zero vectors in the voltage space vector representation

of the inverter. In the present work, the vector selected to coincide

with the actual zero vector is referred virtual zero vector. The vectors

with minimum value for the sum of magnitudes of and β co-

ordinates are chosen to be the virtual zero vector for a particular

sector. The sum of magnitudes of and β coordinates represent the

total offset of the vector from actual zero vector. Therefore, in the

present work the virtual zero vectors chosen are at minimum offset

from zero vectors.

3.3.3 Implementation of Three-Level Inverter Algorithm

This section explains the proposed method for generation of

space vector pulse width modulation for three-level inverter using the

inherent fractal structure associated with the switching space vector

representation of multilevel inverter.

3.3.3.1 Determination of Switching Vectors

The process of obtaining the reference space vector includes the

transformation of (a,b,c) to (d,q) co-ordinates. Sector identification

determines the triangle that encloses the tip of the reference space

81

vector. The vertices of the triangle represent the locations of switching

voltage space vectors used to synthesize the reference space vector.

The (d,q) components of the space vector of an N-level inverter

can be normalized through division by Vdc/ N -1,where Vdc is the dc

link voltage. In the case of a three-level inverter, the voltage Vdc, in the

normalized space vector representation is, therefore, represented by a

vector of length ‘2’ as shown in Fig. 3.28.

Fig.

3.28 Space vector representation of three-level inverter

For a three-level inverter, the switching vectors located at the

six vertices of the hexagon forming the periphery are same as the

vectors of equivalent two-level inverter, but they have the switching

states as (200), (220), (020), (022), (002), (202).

The position of reference space vector A00P for a three-level

inverter is as shown in Fig. 3.29. The first step in the proposed sector

identification method is to determine the location of the tip of the

reference space vector A00P from among the six regions of the

A01

(2, 0)(2 0 0)

A02

(1, 1.732)(2 2 0)

A03

(-1, 1.732)(0 2 0)

A05

(-1, -1.732)(0 0 2)

A06

(1, -1.732)(2 0 2)

A00

(0, 0)

PV

refA04 (-2, 0)(0 2 2)

82

equivalent two-level inverter. This step is implemented by the

comparison of instantaneous reference phase voltages. In this case

the reference space vector A00P is located in region I of equivalent two-

level inverter. The region I is formed by the vertices A00, A01 and A02.

The co-ordinates of the vertices are (0,0), (2,0) and (1,1.732)

respectively. The switching states corresponding to the vectors located

at A00, A01 and A02 are also shown in Fig. 3.29(a). The switching states

of the vector located at A00, A01 and A02 are (000, 111, 222), (200) and

(220) respectively. The next step is to divide region I into four smaller

triangular regions by applying the triangularisation algorithm, it will

generate the coordinates of new voltage space vectors and the inverter

states corresponding to these new switching vectors. The three new

voltage space vectors divide region I into four smaller triangular

regions marked R1, R2, R3, R4 as shown in Fig. 3.29(b).

Thus, by determining the switching states through

triangularisation algorithm for three-level inverter, 27 switching states

and the sectors are represented in Fig.3.30.

(a) (b)

Fig. 3.29 Sector identification and switching vector

A12

(0.5, 0.86)(110 221)

A01

(2, 0)(2 0 0)

A02

(1, 1.732)(2 2 0)

PVref

A00

(0, 0)000 111 222

A13

(1.5, 0.86)(2 1 0)

A11

(1, 0)100 211

R2

R1 R

4R

3

A00

(0, 0)000 111 222

A01

(2, 0)(2 0 0)

A02

(1, 1.732)(2 2 0)

PVref

83

determenation of three-level inverter.

Fig. 3.30 Switching states and sectors of three-level inverter.

3.3.3.2 Determination of Centroid

The location of the tip of the reference voltage space vector A00P

among these four triangular regions is found by determining the

region whose centroid is the closest to the tip of reference space

vector. The co-ordinates of the centroid of an equilateral triangle can

be determined as the average of coordinates of the three vertices. For

an equilateral triangle with the coordinates of the vertices as (1, β1),

(2, β2), (3, β3), the co-ordinates of the centroid (cent ,βcent) can be

obtained from Eq. (3.18).

The triangle with centroid closest to tip of reference space vector

is ΔA11A12A13. From among these four triangles, the triangle enclosing

the reference space vector A00P is ΔA11A12A13 as its centroid is the

closest to tip of reference space vector. The Δ A11, A12, A13 corresponds

000111222

100211

201101212001112

011122

010121

110221021

120

210

220

012

200

202102002

1

5

4

3

2

6

8

911

7

101213

14

15

1617

1819

2021

22

23

022

020

24

84

to sector 8. The sector is identified and the inverter states

corresponding to the switching vectors located at the vertices of the

identified sector are also generated simultaneously.

3.3.3.3 Determination of Switching Times

The voltage reference vector A00P is identified in sector 8 as

shown in Fig. 3.29(b). The voltage space vector with a tip located at A12

becomes the virtual zero vector for sector 8. The sector 8 thus, gets

mapped to sector 1 of the three-level inverter. The determination of

duration now reduces to that of a two-level inverter since after

mapping one of the vectors of the identified sector coincides with the

zero vectors. The durations of the vectors can be determined in case of

two-level inverter.

3.3.3.4 Determination of Optimized Switching Sequence

Once the switching vectors are determined and their respective

durations are calculated, then vectors are to be switched in an

optimum sequence such that only one switching occurs when the

inverter changes its state. In the space vector PWM technique, the

optimum switching is achieved using the redundant states of the zero

vector for alternate switching cycles. In this thesis, the optimum

switching is achieved by using two redundant switching states of the

respective virtual zero vector in the alternate cycles. The tip of the

reference vector A00P is located in sector 8. The switching states

corresponding to the switching vectors at the vertices of sector 8 with

redundancies are A11 (100,211), A12 (110,221) and A13 (210). For sector

8, the virtual zero vector at A12 has two redundant switching states

85

while the voltage vectors at A11 has two redundancies and A13 has one

redundancy. If the redundancy of the virtual zero vector is greater

than two, the last two redundant switching states are selected for the

virtual zero vector. For the other two vectors, if redundant states are

more than one, the last redundant state is selected. In case of three-

level inverter as the zero vector at A12 has two redundant switching

states both of these are selected. As the space vector A11 has more

than one redundant state, the last switching state is selected. As A13

has only one redundant state it is selected. This strategy of choosing

the last two redundant states for the virtual zero vector and the last

redundant state for the other vectors will achieve optimum switching

sequence. The selection will result in switching states 110-210-211-

221 for the virtual zero vector. With this switching sequence only one

switching occurs as the inverter changes its state.

210T

0

020T

2

120T

0

200T

2

220T

1

021T

0

022T

1

010121T

1

110221T

2

011122T

2

100211T

1

000111222T

0

001112T

1

101212T

2

012T

0

002T

2

102T

0

202T

1

201T

0

86

Fig. 3.31 Space vector diagram of three-level inverter with rotating reference vector.

By following the above procedure of the fractal approach for

three-level inverter, the switching states and switching sequence of a

reference vector is generated. Considering twelve samples of reference

vector in a single sector as shown in Fig. 3.31, by rotating reference

angle from 0° to 360°, a total of seventy two samples are obtained. The

optimized switching sequence for seventy two samples of three-level

inverter is determined and presented in Table 3.6.

Table 3.6 Switching states of three-level inverter

Samples States Switching States

1 4-16-17-5 100-200-210-211

2 5-17-16-4 211-210-200-100

3 4-16-17-5 100-200-210-211

4 5-17-16-4 211-210-200-100

5 6-17-5-7 110-210-211-221

6 7-5-17-6 221-211-210-110

7 6-17-5-7 110-210-211-221

8 7-5-17-6 221-211-210-110

9 6-17-18-7 110-210-220-221

10 7-18-17-6 221-220-210-110

11 6-16-18-7 110-210-220-221

12 7-18-17-6 221-220-210-110

13 6-19-18-7 110-120-220-221

14 7-18-19-6 221-220-120-110

87

15 6-19-18-7 110-120-220-221

16 7-18-19-6 221-220-120-110

17 6-19-9-7 110-120-121-221

18 7-9-19-6 221-121-120-110

19 6-19-9-7 110-120-121-221

20 7-9-19-6 221-121-120-110

21 8-20-19-9 010-020-120-121

22 9-19-20-8 121-120-020-010

23 8-20-19-9 010-020-120-121

24 9-19-20-8 121-120-020-010

25 8-20-21-9 010-020-021-121

26 9-21-20-8 121-021-020-010

27 8-20-21-9 010-020-021-121

28 9-21-20-8 121-021-020-010

29 10-21-9-11 011-021-121-122

30 11-9-21-10 122-121-021-011

31 10-21-9-11 011-021-121-122

32 11-9-21-10 122-121-021-011

33 10-21-22-11 011-021-022-122

34 11-22-21-10 122-022-021-011

35 10-21-22-11 011-021-022-122

36 11-22-21-10 122-022-021-011

37 10-23-22-11 011-012-022-122

38 11-22-23-10 122-022-012-011

88

39 10-23-22-11 011-012-022-122

40 11-22-23-10 122-022-012-011

41 10-23-13-11 011-012-112-122

42 11-13-23-10 122-112-012-011

43 10-23-13-11 011-012-112-122

44 11-13-23-10 122-112-012-011

45 12-24-23-11 001-002-012-112

46 13-23-24-12 112-012-002-001

47 12-24-23-11 001-002-012-112

48 13-23-24-12 112-012-002-001

49 12-24-25-13 001-002-102-112

50 13-25-24-12 112-102-002-001

51 12-24-25-13 001-002-102-112

52 13-25-24-12 112-102-002-001

53 14-25-13-15 101-102-112-212

54 15-13-25-14 212-112-102-101

55 14-25-13-15 101-102-112-212

56 15-13-25-14 212-112-102-101

57 14-25-26-15 101-102-202-212

58 15-26-25-14 212-202-102-101

59 14-25-26-15 101-102-202-212

60 15-26-25-14 212-202-102-101

61 14-27-26-15 101-201-202-212

62 15-26-27-14 212-202-201-101

89

63 14-27-26-15 101-201-202-212

64 15-26-27-14 212-202-201-101

65 14-27-5-15 101-201-211-212

66 15-5-27-14 212-211-201-101

67 14-27-5-15 101-201-211-212

68 15-5-27-14 212-211-201-101

69 4-16-27-5 100-200-201-211

70 5-27-16-4 211-201-200-100

71 4-16-27-5 100-200-201-211

72 5-27-16-4 211-201-200-100

3.3.4 Implementation of Five-Level Inverter Algorithm

This section explains the proposed method for generation of

SVPWM for five-level inverter using the inherent fractal structure

associated with the switching space vector representation of multilevel

inverter. The schematic diagram of five-level inverter is shown in Fig.

3.32. The dc bus voltage is split into five levels by using four dc

capacitors, C1, C2, C3 and C4. Each capacitor has Vdc/4 volts and each

voltage stress will be limited to one capacitor level through clamping

diodes. In the five-level inverter, clamping diodes clamped the bus

voltage into three voltage level, +Vdc/2, +Vdc/4, 0,-Vdc/4,-Vdc/2. These

states are defined 4, 3, 2, 1 and 0. There are N3 possible states i.e.,

125 states for five level inverter and it consists of (5-1) = 4 capacitors

on the dc bus, 2(5-1) = 8 switching devices per phase and 2(5-2) = 6

clamping diodes per phase.

90

Fig. 3.32 Five-level diode clamped inverter.

3.3.4.1 Determination of Switching Vectors

In the case of five-level inverter, the voltage Vdc, in the

normalized space vector representation is represented by a vector of

length 4. The switching vectors located at the six vertices of the

hexagon forming the periphery are same as the vectors of equivalent

two-level inverter, but they have the switching states as (400), (440),

(040), (044), (004), (404).

The position of reference space vector A00P for five-level inverter

is as shown in Fig. 3.33. The first step in the proposed sector

identification of this method is to determine the location of the tip of

the reference space vector A00P from among the six regions of the

equivalent two-level inverter. The region I is formed by the vertices A00,

A01 and A02. The co-ordinates of the vertices are (0,0), (4,0) and (2, 2√3)

respectively as shown in Fig. 3.35. The switching states of the vector

located at A00, A01 and A02 are (000, 111, 222, 333, 444), (400) and

P

n

Vdc2

Vdc1

Vdc2

bc

a

Ta8

Ta7

Ta5

Ta6

Tb8

Tb7

Tb5

Tb6

Tc8

Tc7

Tc5

Tc6

z

Ta4

Ta3

Ta1

Ta2

Tb4

Tb3

Tb1

Tb2

Tc4

Tc3

Tc2

Tc1

n

91

(440) respectively. The next step is to divide region I into four smaller

triangular regions by applying the triangularisation algorithm and

generates the co-ordinates of the new voltage space vectors and the

inverter states corresponding to these new switching vectors. The

three new voltage space vectors divide region I into four smaller

triangular regions marked as R1, R2, R3 and R4 as shown in Fig. 3.35.

Fig. 3.33 Space vector representation of five-level inverter3.3.4.2 Determination of Centroids

The location of the tip of the reference voltage space vector A00P

among these four triangular regions is found by determining the

region whose centroid is the closest to the tip of reference space

vector. The co-ordinates of the centroid of an equilateral triangle can

be determined the average of co-ordinates of the three vertices.

P

A01

(4, 0)(4 0 0)

A02

(2, 3.564)(4 4 0)

A03

(-2, 3.564)(0 4 0)

A04

(-4, 0)(0 4 4)

A06

(2, -3.564)(4 0 4)

A05

(-2, -3.564)(0 4 4)

A00

(0,0)A

05 (-2,

-3.564)(0 4 4)

92

Fig.3.3

4 Switching states of five-level inverter.

The triangle with centroid closest to tip of reference space vector

is ΔA11A12AI3. For five-level inverter the triangularisation algorithm has

to be applied once again, which generates further three new voltage

space vectors and also the inverter states corresponding to these new

voltage vectors, thus dividing it into four smaller triangles, the triangle

enclosing the reference space vector A00P is ΔA23A25A26 as its centroid is

the closest to tip of reference space vector. The ΔA23A25A26 corresponds

to sector 27 of five-level inverter. The sector is identified and the

inverter states are also generated simultaneously.

3.3.4.3 Determination of Switching Times

For the voltage reference vectorA00P, the sector identified is

sector 27. The voltage space vector with tip located at A23 becomes the

444333222111000

433322211100

422311200

411300

400344233122011

244133022

144033

044

443332221110

432321210

421310

410343232121010

243132021

143032

043

342231120

442331220

431320

420242131020

142031

042

341230

441330

430241130

141030

041

240 340 440140040

434323212101

423312201

412301

401334223112001

234123012

134023

034

323213102

424313202

413302

402224113002

124013

024

314203

414303

403214103

114003

014

304 404204104004

93

virtual zero vector for sector 27. The sector 27, thus, gets mapped to

sector 1 of the five-level inverter. The determination of duration now

reduces to that of a two-level inverter since after mapping one of the

vectors of the identified sector coincides with the zero vector. The

durations of the vectors can be determined using the conventional

two-level inverter.

3.3.4.4 Determination of Optimized Switching Sequence

The tip of the reference vector A00P is located in sector 27 as

shown in Fig. 3.35. The switching states corresponding to the

switching vectors at the vertices of sector 27 with redundancies are

A23 (210, 321, 432), A25 (310, 421) and A26 (320, 431). For sector 27,

the virtual zero vector at A23 has three redundant switching states

while the voltage vectors at A25 and A26 has two redundancies each. In

the present work, if the redundancy of the virtual zero vector is

greater than two, the last two redundant switching states are selected

for the virtual zero vector. For the other two vectors, if redundant

states are more than one, the last redundant state is selected. This

strategy of choosing the last two redundant states for the virtual zero

vector and the last redundant state for the other vectors will achieve

optimum switching sequence. The selection will result in switching

states 321-432 for the virtual zero vector. The other vectors have

switching states 421 and 431. With these states, switching sequence

of inverter for the sector number 27 is 321-421-431-432 during a

sampling interval and 432-431-421-321 for the subsequent sampling

94

interval. It may be noted that only one switching occurs as the

inverter changes state.

A01

(4, 0)(4 0 0)

A02

(2, 2√3)(4 4 0)

P

A00

(0, 0)(000 111 222

333 444)

PA

13 (3, 3√3)

(4 2 0)A

12 (1, √3)

(220 331 442)

A11

(2, 0)200 311 422

R2

R1

R4R

3

A02

(2, 2√3)(4 4 0)

A01

(4, 0)(4 0 0)

A00

(0, 0)(000 111 222

333 444)

R3

P

A01

(4, 0)(4 0 0)

A02

(2, 2√3)(4 4 0)

A12

(1, √3)(220 331 442)

A13

(3, 3√3)(4 2 0)

A11

(2, 0)200 311 422

A23

(1, √3/2)(210, 321, 432)

A25

(3, √3/2)(310, 421)

A26

(2, √3)(320, 431)

A00

(0, 0)(000 111 222

333 444)

95

Fig. 3.35 Sector identification and switching vector determenation of five-level inverter

By following the above procedure of the fractal approach for

five-level inverter, the switching states and switching sequence of a

reference vector is generated. Considering twelve samples of reference

vector in a single sector as shown in the Fig. 3.36 by rotating

reference angle from 0° to 360°, total of seventy two samples are

obtained. The optimum switching pattern for these seventy two

samples obtained through the implementation of fractal approach for

five-level inverter is shown in the Table 3.7.

Fig. 3.36 Space vector diagram of five-level inverter with rotating reference vector.

Table 3.7 Switching states of five-level inverter

Samples States Switching States

96

1 66-102-103-67 300-400-410-411

2 67-103-69-66 411-410-310-300

3 68-103-67-69 310-410-411-421

4 69-104-103-68 421-420-410-310

5 68-103-104-69 310-410-420-421

6 71-69-104-70 431-421-420-320

7 70-104-105-71 320-420-430-431

8 71-105-73-70 431-430-330-320

9 72-105-71-73 330-430-431-441

10 73-106-105-72 441-440-430-330

11 72-105-106-73 330-430-440-441

12 73-106-105-72 441-440-430-330

13 72-107-106-73 330-340-440-441

14 73-106-107-72 441-440-340-330

15 72-107-75-73 330-340-341-441

16 75-107-108-74 341-430-240-230

17 74-108-107-75 230-240-340-341

18 75-77-108-74 341-241-240-230

19 76-109-108-77 130-140-240-241

20 77-108-109-76 241-240-140-130

21 76-109-79-77 130-140-141-241

97

22 79-109-110-78 141-140-040-030

23 49-111-110-78 030-040-140-141

24 79-109-110-78 141-140-040-030

25 78-110-111-79 030-040-041-141

26 79-111-110-78 141-041-040-030

27 80-111-79-81 031-041-141-142

28 81-112-111-80 142-042-041-031

29 80-111-112-81 031-041-042-142

30 83-81-112-82 143-142-042-032

31 82-112-113-83 032-042-043-143

32 83-113-112-82 143-043-042-032

33 84-113-83-85 033-043-143-144

34 85-114-113-84 144-044-043-033

35 84-113-114-85 033-043-044-144

36 85-114-113-84 144-044-043-033

37 84-115-114-85 033-034-044-144

38 85-114-115-84 144-044-034-033

39 84-115-87-85 033-034-134-144

40 87-115-116-86 134-034-024-023

41 86-116-115-87 023-024-034-134

42 87-89-116-86 134-124-024-023

98

43 88-117-116-89 013-014-024-124

44 89-116-117-88 124-024-014-013

45 88-117-91-89 013-014-114-124

46 91-117-118-90 114-014-004-003

47 90-118-117-91 003-004-014-114

48 91-117-118-90 114-014-004-003

49 90-118-119-91 003-004-104-114

50 91-119-118-90 114-104-004-003

51 92-119-91-93 103-104-114-214

52 93-120-119-92 214-204-104-103

53 92-119-120-93 103-104-204-214

54 95-93-120-94 314-214-204-203

55 94-120-121-95 203-204-304-314

56 95-121-120-94 314-304-204-203

57 96-121-95-97 303-304-314-414

58 97-120-121-96 414-404-304-303

59 96-121-120-97 303-304-404-414

60 97-120-121-96 414-404-304-303

61 96-123-122-97 303-403-404-414

62 97-122-123-96 414-404-403-303

63 96-123-99-97 303-403-413-414

64 99-123-124-98 413-403-402-302

65 98-125-123-99 302-402-403-413

66 99-101-124-98 413-412-402-302

67 100-125-124-100 301-401-402-412

99

68 101-124-125-100 412-402-401-301

69 100-125-67-101 301-401-411-412

70 67-125-102-66 411-401-400-300

71 66-102-125-67 300-400-401-411

72 67-125-102-66 411-401-400-300

3.3.5 Results and Discussions

To validate the proposed method of the generation of space

vector pulse width modulation for multilevel inverters using the fractal

approach, simulation studies have been carried out with a dc link

voltage of 400V and modulation index of 0.8. The simulation

parameters used in this method are given in Appendix-II. Fig. 3.37 to

Fig. 3.47 shows the simulation results for three-level inverter. Fig.

3.37 and Fig. 3.38 show the process of triangularisation and rotation

of reference voltage vector of three-level inverter. Fig. 3.37 shows the

basic SVPWM in which first triangularisation has done to locate the

reference voltage vector. Fig. 3.38 shows the rotation of reference

voltage vector through 0° to 360° in the d-q reference frame. In these

figures ‘red’ points represent the location of voltage vectors, ‘blue’

points represent the first triangularisation and ‘green’ points represent

the reference point corresponding to the reference vector in the

SVPWM. From Fig. 3.38 it is clear that the reference vector is rotated

from 0° to 360° and by the proposed technique the sectors are clearly

identified, when the tip of reference vector moved from sector 7 to

sector 24. As the reference vector is changing from one sector to other,

100

the simultaneous switching sequence is given to the multilevel

inverter.

Fig. 3.39 and Fig. 3.40 show the pole voltages and line voltages

of three-level inverter. Fig. 3.41 and Fig. 3.42 show the phase voltages

and gate currents. Fig. 3.43 shows the stator currents of three-level

inverter fed induction motor. The rotor speed and torque responses of

three-level inverter fed induction motor are shown in Fig. 3.44 and

Fig. 3.45. The harmonic spectrum of inverter output voltage along

with THD is shown in Fig. 3.46.

Fig. 3.47 to Fig. 3.57 shows the simulation results for five-level

inverter. Fig. 3.47 and Fig. 3.48 show the process of triangularisation

and rotation of reference voltage vector of five-level inverter. Fig.3.47

shows the basic SVPWM in which the triangularisation has done to

locate the reference voltage vector. Fig. 3.48 shows the rotation of

reference voltage vector through 0° to 360°, and sectors 25 to 54 in

the (d, q) reference frame in which ‘blue’ colour points represent the

first triangularisation and ‘pink’ colour points represent the second

triangularisation performed.

Fig. 3.49 and Fig. 3.50 show the pole voltages and line voltages

of five-level inverter. Fig. 3.51 and Fig. 3.52 show the phase voltages

and gate currents. Fig. 3.53 and Fig. 3.54 show the stator currents of

five-level inverter fed induction motor. The rotor speed and torque of

five-level inverter fed induction motor are shown in Fig. 3.55 and Fig.

3.56. The harmonic spectrum of five-level inverter output voltage

along with THD is shown in Fig. 3.57. The performance of three-level

101

and five-level inverters with the proposed algorithm is compared in

Table 3.8. From these results it has shown that the five-level inverter

attains a steady state response faster than that of three-level inverter

and the torque ripple and THD is reduced.

(a)

102

(b)Fig. 3.37 Space vector diagram of three-level inverter for

a basic reference angle () of 6°.

(a)

(b)

Fig. 3.38 Space vector diagram of three-level inverter when reference angle () rotated through 360°.

103

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10

100

200

300

400

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10

100

200

300

400

Pol

e vo

ltage

s V

ao, V

bo, V

co (

V)

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10

100

200

300

400

time (s)

Fig. 3.39 Pole voltages of three-level inverter.

104

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-400

-200

0

200

400

Line

vol

tage

s V

ab, V

bc, V

ca (

V)

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-400

-200

0

200

400

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-400

-200

0

200

400

Time (s)

Fig. 3.40 Line-to-line voltages of three-level inverter.

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-400

-200

0

200

400

Pha

se v

olta

ges

Van

, Vbn

, Vcn

(V

)

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-400

-200

0

200

400

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-400

-200

0

200

400

Time (s)

Fig. 3.41 Phase voltages of three-level inverter.

105

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10

1

2

Gat

e cu

rren

ts Ig

a, Ig

b, Ig

c (A

)

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10

1

2

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10

1

2

Time (s)

Fig. 3.42 Gate currents of three-level inverter.

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-60

-40

-20

0

20

40

60

Time (s)

Sta

tor

curr

ents

Ia, I

b, Ic

(A

)

Fig. 3.43 Stator currents of three-level inverter fed induction motor.

106

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-20

0

20

40

60

80

100

120

140

160

Time (s)

Rot

or s

peed

Wm

(ra

d/s)

Fig. 3.44 Speed response of three-level inverter fed induction motor.

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-10

0

10

20

30

40

50

60

70

80

90

Time (s)

Tor

que

(N-m

)

Fig. 3.45 Torque response of three-level inverter fed induction motor.

107

0 2 4 6 8 10 12 14 16 18 200

20

40

60

80

100

Harmonic order

Fundamental (50Hz) = 97.94 , THD= 5.70%

Mag

(%

of F

unda

men

tal)

Fig. 3.46 Output line voltage harmonic spectrum of three-level inverter.

(a)

108

(b)

Fig. 3.47 Space vector diagram of five-level inverter for a basic reference angle () of 6°.

(a)

109

(b)

Fig. 3.48 Space vector diagram of five-level inverter when reference angle () rotated through 360°.

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10

100

200

300

400

Pol

e vo

ltage

s V

ao, V

bo, V

co (

V)

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10

100

200

300

400

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10

100

200

300

400

Time (s)

Fig. 3.49 Pole voltages of five-level inverter.

110

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-400

-200

0

200

400 Vab

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-400

-200

0

200

400

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-400

-200

0

200

400

Time (s)

Line

vol

tage

s V

ab, V

bc, V

ca (

V)

Fig. 3.50 Line-to-line voltages of five-level inverter.

111

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1

-200

0

200

Pha

se v

olta

ges

Van

, Vbn

, Vcn

(V

)

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1

-200

0

200

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1

-200

0

200

Time (s)

Fig. 3.51 Phase voltages of five-level inverter.

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10

1

2

3

4

Gat

e cu

rren

ts Ig

a, Ig

b, Ig

c (A

)

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10

1

2

3

4

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10

1

2

3

4

Time (s)

Fig. 3.52 Gate currents of the five-level inverter.

112

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-60

-40

-20

0

20

40

60

Time(s)

Sta

tor

curr

ents

Ia, I

b, Ic

(A

)

Fig. 3.53 Stator currents of five-level inverter fed induction motor.

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-60

-40

-20

0

20

40

60

Time (s)

Sta

tor

curr

ent I

a (A

)

Fig. 3.54 Stator current of five-level inverter fed induction motor.

113

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-20

0

20

40

60

80

100

120

140

160

Time (s)

Rot

or s

peed

Wm

(ra

d/s)

Fig. 3.55 Speed response of five-level inverter fed induction motor.

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-10

0

10

20

30

40

50

60

70

Time (s)

Tor

que

Te

(N-m

)

Fig. 3.56 Torque response of three-level inverter fed induction motor.

114

0 5 10 15 200

20

40

60

80

100

Harmonic order

Fundamental (50Hz) = 128 , THD= 3.61%

Mag

(%

of F

unda

men

tal)

Fig. 3.57 Output voltage harmonic spectrum of five-level inverter.

3.3.5.1 Analysis of Three-level and Five-level Inverters

The results of three-level and five-level inverters have been

analyzed and shown in Table 3.8. The five-level inverter shows

improved performance than the three-level inverter.

Table 3.8 Performance of three-level and five-level inverters

S.No. Parameters Three-level inverter

Five-level Inverter

1 Torque (N-m) 10.41 10.672 Speed (rad/s) 151.4 150.713 Irms (A) 5.129 4.8594 THD (%) 5.70 3.61

3.4 CONCLUSIONS

In the field of high power, high performance applications the

multilevel inverters seem to be the most promising alternative. In this

chapter the application of space vector pulse width modulation control

strategy on three-level inverter and a novel approach for the

generation of space vector PWM for multilevel inverter based on

fractals have been proposed and analyzed. The performances of these

two methods are studied in terms of harmonic distortion.

115

The first proposed SVPWM algorithm provides high safety

voltages with less harmonic components compared to two-level

structures and reduces the switching losses by limiting the switching

to two thirds of the pulse duty cycle. This last aimed at the one hand

to prove the effectiveness of SVPWM in the contribution of switching

power losses reduction and to show the advantage of three-level

inverter that carries out voltages with contents of less harmonic

injection than the two- level inverter. On the other hand, from the

simulation results, it is seen that as modulation index is increased the

total harmonic distortion (THD) decreases and fundamental RMS

value increases linearly. In the first proposed method, the obtained

total harmonic distortion for two-level inverter and three-level inverter

are 54.02% and 28.60% respectively.

In this chapter, a second algorithm for the generation of space

vector PWM for multilevel inverter based on fractals has been

proposed and applied for three-level and five-level inverters. In this

method, the switching sequence is determined with out using look up

tables, so the memory of the controller can be saved. The switching

times of voltage vectors are calculated at the same manner as two-

level SVPWM. Thus, the proposed method reduces the execution time

of the three and five level SVPWM. It is easy to implement the

triangularisation algorithm as basic arithmetic is used. It can also be

applied to the SVPWM method for n-level. The obtained total harmonic

distortions for three-level and five-level inverters are 5.70% and 3.61%

116

respectively. Thus the complexity and execution time have been

reduced in this algorithm.

117