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1 Tuesday, June 12, 2007SOO KWAN EO
2007. 4. 112007. 4. 11
Soo Kwan EoSr. Vice President, System LSI DivisionSamsung Semiconductor Business Unit
Samsung Electronics
SoCSoC System Architecture Design:System Architecture Design:ESL ESL -- VViiPP ApproachesApproaches
2 Tuesday, June 12, 2007SOO KWAN EO
IntroductionIntroductionIntroduction
無無限限
競競爭爭
3 Tuesday, June 12, 2007SOO KWAN EO
Convergence Is On The WayConvergence Is On The Way
• From Analog to Digital• Smaller, Multi-functions• Components
• Heterogeneous Technologies• Mixed signals, MEMS…• Systems
• Inter-Industries• Total solutions
VerticalVerticalConvergenceConvergence
1990’s
HorizontalHorizontalConvergenceConvergence
Late ’90’s ~ 2000’s
SpatialSpatialConvergenceConvergence
’00’s 2nd half ~ 2010’s
Internet showing up Rapid digitalization
Internet showing up Rapid digitalization
Internet growth, *.com bubble &
collapse
Internet growth, *.com bubble &
collapse
Broadband, mobile life & connectivity
Broadband, mobile life & connectivity
Well-being lifeEnvironment
Robot
Well-being lifeEnvironment
Robot• Inter-sciences• Sensibility
IT + BT + NTIT + BT + NT
2010’s ~
4 Tuesday, June 12, 2007SOO KWAN EO
TodayToday’’s Wave: Mobile s Wave: Mobile -- Digital ConvergenceDigital Convergence
TelematicsImage Processing
Entertainment
BroadcastingComputing
Communication
• Smart Mobile Phone – A Variety of Functions• Mobile Devices
Center of Ubiquitous Media NetworkDriver for Semiconductor Industry
• Smart Mobile Phone – A Variety of Functions• Mobile Devices
Center of Ubiquitous Media NetworkDriver for Semiconductor Industry
Source: keynote in DATE05 by JT KongSolution BusinessSolution Business
SoCSoC
5 Tuesday, June 12, 2007SOO KWAN EO
Processor: AP - MCModem: GSM/GPRS - WCDMA - CDMA2000
Connectivity: Wireless LAN - GPS - Bluetooth
RF/Analog: Rx - Tx - Zero IF - PM
Camera Chipset: CIS - CCD - ISP
Display Driver IC (DDI): STN - TFT - OLED
Smart Card:Smart Card: SIMSIM
Flash Memory:Flash Memory: Code/Data StorageCode/Data Storage
SIP / MCP/POPSIP / MCP/POP
RAM: Mobile DRAM - SRAM - UtRAM
SoCSoC
• Samsung provides Total Semiconductor Solutions for Mobiles• Main Focus: Mobile AP, DDI, CIS, Smart Card, Mobile Memory
• Samsung provides Total Semiconductor Solutions for Mobiles• Main Focus: Mobile AP, DDI, CIS, Smart Card, Mobile Memory
Semiconductors in MobileSemiconductors in Mobile
11%11%
4%4%
5%5%
5%5%
15%15%
6 Tuesday, June 12, 2007SOO KWAN EO
Semiconductor Big BangSemiconductor Big Bang• Semiconductor market has grown continuously
through new market creation …
[Source: Samsung]
Digital TV
Cell Phone
~1995 2000 2005 2010
Sem
icon
duct
or C
onsu
mpt
ion
IT Infra PC Mobile
Consumer + Mobile
MP3
PCGraphic
$80B
DSC
Game Console
2015
$250B
SoC
Bio
RFID
Robot
HCI
Automotive
SemiconductorBig Bang
Health
and in 2015 we expect …
7 Tuesday, June 12, 2007SOO KWAN EO
[Source: Wayne Dai, VLSI Design Symposium, 2006 Tokyo IT panel]
80’s
Design
Fab
IDM
IDMIDM
Design
Fab
90’s
Fabless SemiSilicon Foundry
Separated
IDMIDM
Fab
DesignArchitecture
DesignImplementation
00’s ~Fabless Semi
Design FoundrySilicon Foundry
Separation ?IDM ?IDM ?
Fab-lite ?
SONY NXP
TI
INFINEON
LSI LOGICToshiba
FREESCALESEMI
TSMC SECUMC
CHARTERED
•
•
IDM’s annual sales to get meaningful ROI for R&D (2006 base)• $8.3B/year at 65 nm: Intel, Samsung, TI, STM, and Toshiba• $13.3B/year at 45 nm and $16.7B/year at 32 nm: Intel & Samsung only
Fab costs are also skyrocketing
[Source: Mark Lapedns, EE Times, March 30, 2007]
Challenges Facing the Challenges Facing the IDMIDM’’ss: Darwinian: Darwinian’’s struggles struggle
8 Tuesday, June 12, 2007SOO KWAN EO
SoCSoC ChallengesChallenges如如履履薄薄氷氷
9 Tuesday, June 12, 2007SOO KWAN EO
Example : DVDP SoC
CTV DVDP LCD TV
50% Price
CTV : 20 years
DVDP : 2 years
LCD TV : 1 year
Price Trend of Digital Devices
[Source : Samsung]
∆38%
∆13%
∆38%
∆32%
0
$4
$8
$12
$16
2001 2002 2003 2004 2005
• Recently, SoC prices have reduced 30~40% per year• Memory market is also lousy and even brutal
• ASP for DRAM 44% and NAND Flash 50% in Q1, 2007
A A PrestissimoPrestissimo Price ReductionPrice Reduction
10 Tuesday, June 12, 2007SOO KWAN EO
Scaling Continues But ItScaling Continues But It’’s Expensive!!!s Expensive!!!
1-3 4-6 7-1240%
50%
60%
70%
80%
100%
90%
Yield RampYield Ramp--upup
130nm
90nm
Months
[IBS, 2004]
$ per 1$ per 1stst Mask SetMask Set
0
0.5
1
1.5
2
3
130nm 90nm 65nm
Mill
ion
$
2.5
Shrinking Market WindowShrinking Market Window
12 months12 months 33--6months6months
MulticoreMulticore for low power increases chip areafor low power increases chip area Software + Hardware CostSoftware + Hardware Cost
180nm 130nm 90nm250nm350nm0
10M
20M
30M
40M
60M
Mill
ion
$
50M
HWHW
SWSW
Design Cost [IBS, 2004]
[Source : Samsung, ‘07]
SW (60%)SW (60%)HW (40%)HW (40%)
SW (80%)SW (80%)HW (20%)HW (20%)
11 Tuesday, June 12, 2007SOO KWAN EO
Gaps in High Performance & Low PowerGaps in High Performance & Low Power
3D graphics
ShannonShannon’’s laws law((2.8x / 18m)
2G (IS-95)9.6kbps
3G (CDMA 1xEV)3,100kbps
4G (1GMbps~100Mbps)
QVGA
D1
HD (720p)
Full HD (1080i)Mobile MultimediaMobile Multimedia
Productivity Gap: Design complexity vs. Moore’s law Power Gap: Design complexity vs. Battery
Moore’s law
2003200319951995 20122012
Battery capacity
Design Complexity
12 Tuesday, June 12, 2007SOO KWAN EO
Evolution of Design Resources AllocationEvolution of Design Resources Allocation
Source: IBS July 2004
8
9
22
16
6054
50.13μm (10M gates)
3
3
13
9
30
2
18
SW
Arch & pro j mgmt
Spec to RTL
Func verif
Phys ical des ign
Pos t-GDSII
0.18μm (5M gates)
29
26
42
28142170
17
90nm (20M gates)
66
58
88
58311390
41
65nm (40M gates)
180
nm13
0 nm
90 n
m65
nm
Architect SW HW System Head count
0
100
200
300
400
500
600
700
800
13 Tuesday, June 12, 2007SOO KWAN EO
SoCSoC ChallengesChallenges
RR &&DD
DesignVerification
Manufacturing
14 Tuesday, June 12, 2007SOO KWAN EO
Electronics Systems Level DesignElectronics Systems Level Design
-- Virtual Platform Virtual Platform --浩浩然然之之氣氣
15 Tuesday, June 12, 2007SOO KWAN EO
Just What is ESL?Just What is ESL?
By Wikipedia (March 30, 2007),
Electronic System Level design, or "ESL", is an emerging electronic design methodology which focuses on the higher abstraction level concerns first and foremost.
Electronic System Level is now an established approach at most of the world’s leading System-on-a-chip (SoC) design companies, and is being used increasingly in system design. From its genesis as an algorithm modeling methodology with ‘no links to implementation’, ESL is evolving into a set of complementary methodologies that enable embedded system design, verification, and debuggingthrough to the hardware and software implementation of custom SoC, system-on-FPGA, system-on-board, and entire multi-board systems.
ESL can be accomplished through the use of SystemC as an abstract modeling language.
http://en.wikipedia.org/wiki/System-on-a-chiphttp://en.wikipedia.org/wiki/System_designhttp://en.wikipedia.org/wiki/Algorithmhttp://en.wikipedia.org/wiki/Computer_modelhttp://en.wikipedia.org/wiki/Debugginghttp://en.wikipedia.org/wiki/Debugginghttp://en.wikipedia.org/wiki/Debugginghttp://en.wikipedia.org/wiki/Debugginghttp://en.wikipedia.org/wiki/Debugginghttp://en.wikipedia.org/wiki/SystemChttp://en.wikipedia.org/wiki/Modeling_languagehttp://en.wikipedia.org/wiki/Modeling_languagehttp://en.wikipedia.org/wiki/Modeling_language
16 Tuesday, June 12, 2007SOO KWAN EO
Managing Managing SoCSoC Design CostDesign Cost• Design costs are increasing rapidly as IC products become more complex• Slower yield ramp-up in Nano process also impacts on cost• Where is “Blue Ocean” to suppress the ever increasing design cost?
(Source :IBS, 2005)
0
20
40
60
10 20 30 40 50
0.065nm
0.09nm
0.13nmGate
Count(M)
DesignCost(M$)
Higher Design CostHigher Design CostDesign cost reductionDesign productivity is critical
Source: ITRS 2005
17 Tuesday, June 12, 2007SOO KWAN EO
Landscape of Design TechnologyLandscape of Design Technology
Synthesis
Analysis
Verification
Test
System leveldesign
Logicdesign
Circuitdesign
Physicaldesign
•Test architecture
•Functional design•HW/SW partitioning•SW development
•Performance modeling•System simulation
Formal Checking Layout CheckingEquivalence Checking
Dynamic Timing/SI verification
•Test logic insertion(BIST)
•Test model generation
•Noise, delay, defect tests•Pattern Gen.
•Chip test •Diagnostics
•Mask corrections data prep.
•Design for yield, manufacturability
Logic and interconnect planning
•Logic optimization•Technology mapping
Analysis macro models, opt. Objectives, opt. frameworkPower estimation and analysisNoise estimation and analysis
3D extraction
Circuit simulationManufacturability Checking
•Functional simulation
•Analog macro synthesis •Integrated
flow/API•Incremental opt.
•Param. Yield opt.
•Modeling tools•Statistical process modeling•Process calibration characterization•Failure analysis
•Process•Masks•Yield
Spec RTL code Gates/Cells Transistors Masks Chip
Fabrication
Source: ITRS 2003
18 Tuesday, June 12, 2007SOO KWAN EO
Latency, PowerLatency, Power
Fault/yield ProbabilityFault/yield ProbabilityArchitecture Design
Algorithm DesignESLESL
VariationInformation
[ESSCIRC’04]
Paradigm Shift of DesignParadigm Shift of Design--TechnologyTechnology
Fault-tolerant algorithm
Yield-improving architecture
Razor (ARM) Apollo (IMEC)
Statistical STA P&R w/ CMP sim.
fill & cheeselitho / etch
NA, NA, ToxTox
CriticalTiming,power VtVt, , LgLg, L, t, , L, t, tILDtILD
Quantum Physics
Mask / Process Design
Logic / PhysicalDesign
ProcessProcess
Designer’sIntention
?
?
VddVdd, Temp, Temp
19 Tuesday, June 12, 2007SOO KWAN EO
Design Productivity: ESLDesign Productivity: ESL
ComplexityComplexity
MooreMoore’’s Laws Law(# gates)(# gates)2x / 18m2x / 18m
ShannonShannon’’s Laws Law(bandwidth)(bandwidth)2.8x / 18m2.8x / 18m
Embedded SWEmbedded SW(# lines)(# lines)
1.5x / 12m1.5x / 12m
Heterogeneous MultiHeterogeneous Multi--processorprocessorArchitectureArchitecture
μP
IP
Mem
IP
PE
PE
PE
μP
Mem
PE
NoC
Higher Abstraction Level than RTL is RequiredTransaction Level Model (TLM)
Master SW & HW Design Complexity!
0
50
100
150
200
250
300
350
400
2004 2007 2010 2013 2016
#. PEs (250k gates, 8KB / PE)
Source: ITRS 2005 draft
HW designHW designcomplexitycomplexity
20 Tuesday, June 12, 2007SOO KWAN EO
ESL Design Hype Cycle: FootprintESL Design Hype Cycle: Footprint
Plateau of productivity~ 2H’00’s
2H’80’s ~ early 90’s
Trigger
~ middle 90’s
Peak of inflated
expectation~ late 90’s
Trough of disillusionment
~ 1H’00’s
Slope of enlightenment
New concept of ESL DT
SPW
Matlab/Simulink
MaxSim/ARM ESL
21 Tuesday, June 12, 2007SOO KWAN EO
ESL Design ChallengesESL Design Challenges
ESL DesignESL DesignTechnologyTechnology
Disruptive Design Technology• System synthesis• Heterogeneous simulation• Equivalence check• Formal verification• Power closure• Design reusability...
Daybreak
The Language Soup
SystemCVerilogJAVA
C++
Many Others
RTOS
UML
Platform based design• Simulation speed• Performance• System power• Timing• Verification...
Prosperity
Progress
HW/SW Co-design
• Automatic HW/SW partitioning• Architecture synthesis
• Behavioral• Software• HW/SW interface
• System integration::
22 Tuesday, June 12, 2007SOO KWAN EO
( Source : Gartner Group )View of Kiheung Complex(’04. Nov.)
Memory
Memory R&D
WhasungComplex
Onyang site
Austin site (U.S.A.)
Suhzou Site (China)
About Samsung SemiconductorAbout Samsung Semiconductor
靑靑雲雲之之志志
23 Tuesday, June 12, 2007SOO KWAN EO
Global Semiconductor MarketGlobal Semiconductor MarketExpecting 10% of CAGR during 2003~2007
Expecting single digit growth beyond 2008
System LSI market ~ 70% of the total semiconductor market
(US$ Billions)
126126 151151158158 164164
181181
20022002 20032003 20042004 20052005 20062006 20072007
System LSI
Memory & Discrete
5656
7676 79797878
8686
4848
111111
(Source: iSuppli)19931993
7.97
3.044
30.915.83
Intel
삼성
31.5419.84Intel vs.
38.2%
51.2%
62.9%
24 Tuesday, June 12, 2007SOO KWAN EO
WW Semiconductor Supplier RankingWW Semiconductor Supplier Ranking
Source: WSTS, October 2006
Global semiconductor market trendGlobal semiconductor market trend
213
137 151159
173195
7%
8.5%
8.6%
12.1%
24%
10%
5.5%
8.7%
13.2%
0
50
100
150
200
250
300
350
2004 2005 2006 2007 20080%
5%
10%
15%
20%
25%
30%SemiconductorSys. LSI반도체 성장률
WW LSI 성장률
(B$)
227247
268
300314
207
28%
4.7%
6.0%
2009
Source: IC insights, Feb. 2007
9%
14.3%
8.0%
17%
-11%
9.7%
US $MWorldwide semiconductor supplier rankingWorldwide semiconductor supplier ranking
0
5000
10000
15000
20000
25000
30000
35000
40000
2004 2005 2006
Intel
SEC
TI
ST
Toshiba
Ranking M/S‘03‘04
1513
2 %2 %
‘05 15 2 %‘06 15 2 %
LSI 부문
25 Tuesday, June 12, 2007SOO KWAN EO
SamsungSamsung’’s experiencess experiences
利利用用厚厚生生
26 Tuesday, June 12, 2007SOO KWAN EO
Just What is Virtual Platform?Just What is Virtual Platform?By Wikipedia (March 30, 2007),
A virtual platform is a software emulation of a computer or embedded system. A virtual platform contains the building blocks of a system, i.e. one or more processors, peripherals such as Ethernet and USB, and storage such as memory and disks. It can be used for the development, testing, and operation of software, such as firmware, drivers, protocol stacks, OS, and application software. It is usually integrated with software development tools such as an IDE (integrated development environment), compilers, debuggers.One particular, and commercially highly successful, variant of a virtual platform is a virtual machine as offered by VMware and Xen. Here, the virtual system is an x86-based PC with a restricted number of highly standardized components, such as USB 1.1 and 2.0, Ethernet controller, ATA disk drives, and VGA graphics. Very high performance of the emulated system, typically within 50%-75% of host performance, is made possible by directly using the memory and CPU of the host system, with some clever monitor software in the virtualization layer to model protected instructions and memory protection. See VMware and Xen for examples of x86-based virtual machines, and Hypervisor and Paravirtualization for more information on the techniques used for implementation.
http://en.wikipedia.org/wiki/Emulationhttp://en.wikipedia.org/wiki/Ethernethttp://en.wikipedia.org/wiki/USBhttp://en.wikipedia.org/wiki/Integrated_development_environmenthttp://en.wikipedia.org/wiki/Integrated_development_environmenthttp://en.wikipedia.org/wiki/Integrated_development_environmenthttp://en.wikipedia.org/wiki/Integrated_development_environmenthttp://en.wikipedia.org/wiki/Integrated_development_environmenthttp://en.wikipedia.org/wiki/VMwarehttp://en.wikipedia.org/wiki/VMwarehttp://en.wikipedia.org/wiki/Xenhttp://en.wikipedia.org/wiki/Xenhttp://en.wikipedia.org/wiki/Virtual_machineshttp://en.wikipedia.org/wiki/Hypervisorhttp://en.wikipedia.org/wiki/Paravirtualization
27 Tuesday, June 12, 2007SOO KWAN EO
Current Status of ESL DT @ SamsungCurrent Status of ESL DT @ Samsung
On-ChipFabrics(BUS)
On-ChipFabrics(BUS)
27
Simulation withAbstract Models
(ViP)
Simulation withAbstract Models
(ViP)
HW / SW Co-Design
HW / SW Co-Design
ArchitectureExploration
ArchitectureExploration
BehavioralSynthesis
BehavioralSynthesis
Early FW Development
Early FW Development
System LevelVerification
System LevelVerification
FW & SystemOptimization
FW & SystemOptimization
Behavioral model- Programmer’s view & Functionality validation- C++ or SystemC
TL model (TLM)- Architecture view & validate- HW optimization & verification- C++ or SystemC
RTL model- HW optimization & verification- Silicon path- Verilog or VHDL
Abstract
Concrete
LateEarly
Abstraction
Level
Time in Development Process
Low Power @Architecture
Low Power @Architecture
Reference: Nikkei Business Publications ’05 February
28 Tuesday, June 12, 2007SOO KWAN EO
Samsung Samsung VViiPP OverviewOverviewHW and SW coHW and SW co--designdesign
Identify the performance bottleneck on HW & SW systemSystem architecture design and exploration
TLM model library with C++/TLM model library with C++/SystemCSystemC usedusedPrePre--silicon SW development and optimizationsilicon SW development and optimizationSystem level low power design and profilingSystem level low power design and profiling100~1000X faster than RTL simulation100~1000X faster than RTL simulation
TLM use modelTLM use model AccuracyAccuracy Simulation speedSimulation speed
Programmer’s view (PV) SW application development
Untimed register-accurate > 50 Mcps
SW performance analysis
> 80%Interval: 10-100 Kcps
> 5 Mcps
Architecture/Bus exploration
> 90%Interval: 1-10 Kcps
< 1 Mcps
Cycle Approximate Architecture/Bus optimization
> 95% < 0.5 Mcps
Programmer’s viewWith Timing (PV+T)
29 Tuesday, June 12, 2007SOO KWAN EO
삼성삼성 VViiPP 기술적기술적 성과성과
핵심기술핵심기술 세부기술세부기술개발개발
시점시점기술적기술적 성과성과
SOC Platform 시스템의정량적 성능분석 및 최적화
• RTL 대비 architecture simulation speed 100~1000배 향상
RTL 대비 90% 이상의 정확도 유지• 상위레벨 IP (TLM) 모델링 기술 확보• 정량적 성능분석/ 최적화 기술 및 환경 확보
'03.01~
• SoC Platform Quality 향상• HW/SW 동시 성능분석 및 최적화 (WUSB, MIPS value 75% 향상)
HW Platform과 연계한내장형 SW 동시 개발/검증
• ViP를 기반으로 한 SW Profiling 및 최적화 기술
'04.01~
• Hybrid HDD 적용 결과, random read 성능 2.6 배 향상, command 당 처리 속도 60% 향상
시스템 수준 저전력 설계• SOC 시스템 전력 소모 예측 기술 개발• DPM (Dynamic Power Management) 기술개발 '04.01~
• DPM 기술 적용 up to 45% 전력 소모 감축 달성
HW Acceleration 기술과접목한 simulation 고속화
• HW IP를 HW Acceleration 방식으로 구현하여 ViP와의 연동, 혼합 시뮬레이션 할 수 있는 기술 확보
• 설계팀 기보유 개발 board 재활용• Tool Chain 자동화
'06/01~
• TLM 개발/확보 기간 단축: (MFC 기준, 36 1 MM)
• 시뮬레이션 속도 향상 (MFC 기준, 12K 200K cps)
30 Tuesday, June 12, 2007SOO KWAN EO
Samsung Experience #1Samsung Experience #1
MMC master
NAND master
ProcMMC slave
NAND slaveINTC
SRAM
ROMMMC
masterNAND master
MMC slaveNAND slaveINTC
SRAM1
ROM
Proc
SRAM2
Architecture Exploration HW/SW Co-Optimization
Accuracy 97% vs. Hardware Board Measurement
30% Design Cycle Reduction
Spec.Spec. HW DesignHW Design SW DesignSW Design Int.Int.
TimeTime
BeforeBefore
Spec.Spec. HW DesignHW Design
SW DesignSW Design
Int.Int.AfterAfter
MMCRS-MMC
SDminiSD™
MMCplus™ & MMCmobile™
0
2
4
6
8
10
12
Wri
te
Rea
d[MB
/s]
Memory Access 6x speedup
31 Tuesday, June 12, 2007SOO KWAN EO
Samsung Experience #2Samsung Experience #2
The entire system as well as the chip is modeledas a virtual platform (ViP)
CPU subsystem
Modem subsystem
GPS subsystem
DSP subsystem
USB subsystem
Flash memory
SDRAM
Basestationmodel
USB model
Satellite signal generator
ViP
33% Performance & power
10% of total area reduction
32 Tuesday, June 12, 2007SOO KWAN EO
Samsung Experience #3Samsung Experience #3
DRAMOneNAND®
Flash
Interface &Control
SoCDisk
ATA Cmds
No mechanical latency!
Less spin!
Application : Hybrid HDDApplication : Hybrid HDDConcept : Flash as non-volatile cache
MeritMeritFaster bootLarger Mean Time Between Failure (MTBF)Longer battery lifeCheaper than solid-state drive (SSD)
SoCSoC is the key hereis the key hereInformation from ViP: Where to optimize?
Various and useful profiling featuresHW/SW co-profiling
Solution development time reductionSolution development time reduction
Up to 90% Power Savingwhen powered down
Read and Write instantly while spindle stopped
33 Tuesday, June 12, 2007SOO KWAN EO
Profiling Environment
TargetFirmware
TestPattern
Call-Trace Browsing
Fun_A
Fun_B Fun_C
Fun_E
Fun_F
Path-based Analysis
PostProcessor
0
1 0 0
2 0 0
3 0 0
4 0 0
5 0 0
6 0 0
1 6 1 1 1 6 2 1 2 6 3 1 3 6 4 1 4 6 5 1 5 6 6 1 6 6 7 1 7 6 8 1 8 6 9 1 9 6
RunTimeHistory
ProfilingTracer
34 Tuesday, June 12, 2007SOO KWAN EO
Optimization ResultMore than 100% improvement W/O silicon revision!More than 100% improvement W/O silicon revision!
Latency Hiding, HW pipeliningSpecializationMemorization
34Performance improvement
via 4 device erase
1 2 3 4 5 6 7
Test #1
Test #2
Code Revision #
Processing time became < 1/2
Proc
essi
ng T
ime
34
Prep write Data transfer & program
Write preparation
4 deviceserial
solidification
Performance improvement by4 device erase
35 Tuesday, June 12, 2007SOO KWAN EO
Samsung Experience #4Samsung Experience #4
SyntaxProcessor
(SP)
Arbiter
DDRController
DDRSDRAM
MotionCompensationProcessor (MP)
4 banks x 2 Mbits x 2 x 16 bits(256Mbits)
TransformProcessor
(TP)
Multi-Format Decoder
FrameCapture
(Virtual Model)
HostProcessor(ARM920T)
StreamCapture
(Virtual Model)
SRAM/ROMController
SRAM
ImageLoader
MS
MSS M
AHB(32)AHB+(64)
M MasterS Slave
Basic System Model
Architecture Exploration Focus
Minimum Clock (MHz)
B1 B2 Diff.
146 39%
41%195
Average 203
Worst frame 275 • Improved bus architecture 40 % Lower clock speed Lower power
01
23
456
78
910
I P B B P B B P B B P B B I B B P B B P B B P B B P B B
B1
B2
36 Tuesday, June 12, 2007SOO KWAN EO
Multi format decoder Multi format decoder VViiPP ResultsResults
•ViP simulation speed / 1 HD frame:4 minutes 20 seconds* / 1 SD frame:16 seconds* HD stream used has far more B slices and 4x4 blocks.95% accuracy and speed > 400X than RTL
37 Tuesday, June 12, 2007SOO KWAN EO
Samsung Experience #5: Bandwidth AnalysisSamsung Experience #5: Bandwidth Analysis
MPCOREARM11 (x2)
L2CACHEDDRC0
AXI_SPINE0 (64bit, m12, s4)
AHB_SFR0 (32bit, m1, s3)
Memoryfor L2
MMM S
AXI_PERI (32bit, m2, s5)
X2H
DS
DMA1 DMA0
AHB_SFR2 (m1, s4)
H2H
SSSECURITY
AHB_SFR3 (m1, s13)
M
S
AHB_SFR1 (m1,s8)
H2H
OTGM
S
APB0 (32bit, m1, s16)
SS
3DM
SMFC
M
S
X2HDS
ROMeDRAM ExtDDRExt
DDR
SROMC
ExtNOR
ExtSRAM
AMCSRAM
X2P
CLK_RST PRNG TWIF SPDIF PKEI2C (x2)
APB1 (32bit, m1, s14)
X2P
UART (x5)SPI (x5) I2S (x3) ECID GPIO TIMERWDT
M
S
DDRC1SS
AHB_M
eDRAMCSS
4
S
TV_OUTM
SCAM_IN
M
S
AXI_SPINE3 (32bit, m13, s1)
EX
LCD_OUTM
S
H2H
FILE_SYSM
SDSPM
S
2
2DM
SALIVE
S
AXI_SPINE2 (32bit, m6, s2)
EX
AXI_SPINE1(64bit, m9, s1)
CAM_IN : JPEG, CAMIF, ISPDSP : AMC, ADM, ADM_INTCTV_OUT : VP, MIXER, HDOUT, HDMIFILE_SYS : SDIO, ATAPI, CEATA, ECC, FMCLCD_OUT : CLCD, LCDIFSECURITY : SHA1, AES, DATA_SEC
BUS_DATA
BUS_SFR
S
+
DSAXI IP
AHB IP
APB IP
Downsizer
EX Expander
X2P
H2H
X2H
H2X Ahb2Axi Br
Axi2Ahb Br
Ahb2Ahb Br
Axi2Apb Br
System clock frequency : 133MHzSystem clock frequency : 133MHz
400MHz
Multimedia Architecture
Does the IP utilize the bandwidth Does the IP utilize the bandwidth efficiently?efficiently?
Is memory bandwidth enough?Is memory bandwidth enough?
38 Tuesday, June 12, 2007SOO KWAN EO
Scenario Based AnalysisScenario Based Analysis
Basic data flow for 3D display scenarioMFC decodes a 1280x720p 24fps stream at 10Mb/secScaler downscales HD image into 600x600 size to provide image to 3D engine. (CSC is also provided.)MP11Core writes 3D commands into 3D engine3D engine reads the 600x600 image(bilinear) & other 2D objects texture, and map texture onto 3D objects at 60fpsTvout displays 1280x720p size frame at 60fps
ScalerScaler
DDR
Video frames(HD, YUV420)
Other 2DObjects
(RGB)
3D frame(HD, RGB)
AXI_SPINE (PL30x)
MFCMFC 3D3D TVoutTVout11 22
MP11coreMP11core
programs
AHB
AXI2AHB5544
Down scaledVideo image
(RGB)
33
39 Tuesday, June 12, 2007SOO KWAN EO
VViiPP for Worst Scenariofor Worst Scenario
MP11CoreL2 cache
MFC(64b)
3D(64b)
TVout(64b)
Audio(32b)
LCD(32b)
PL301(64b, 9x1) PL301(32b, 13x1)
PL340DDR1
PL340DDR0
PL340eDRAM AHB_MEM
SRAM ROMAXI_PERI
PL301 (64b, 12x5)
RS USRegister Slice Up-sizer
PL301(32b, 6x1)
EX Expander
EX
RS
EX
RS RS
H2X AHB2AXI BR
H2X H2XH2X
RSX2H
X2H AXI2AHB BR
DS Down-sizer
DS
MFC
Memory Controller + DDR
Video Processor
Scaler
3DMonitor
•Required system clock•Bandwidth analysis
• For each IP master and Memory•Analysis target
•Pure bandwidth (MB/s)•Bandwidth (MHz)•Memory utilization(%)
40 Tuesday, June 12, 2007SOO KWAN EO
Level of Model AbstractionLevel of Model AbstractionModel created by
Verilog2C Conversion
• Simulation speed < 50Kcps(Especially slow for huge IP)
• Accuracy > 95%• Legacy IP• IP from other company
Cycle Accurate Model
• Simulation speed 95%• Validate performance by TL
model, and start design• Create model for simulation
speed (ex: Bus Model)
Statistical Traffic Generator
• Simulation speed
41 Tuesday, June 12, 2007SOO KWAN EO
Samsung Experience #6:Samsung Experience #6: Latency AnalysisLatency Analysis
MPCOREARM11 (x2)
L2CACHEDDRC0
AXI_SPINE0 (64bit, m12, s4)
AHB_SFR0 (32bit, m1, s3)
Memoryfor L2
MMM S
AXI_PERI (32bit, m2, s5)
X2H
DS
DMA1 DMA0
AHB_SFR2 (m1, s4)
H2H
SSSECURITY
AHB_SFR3 (m1, s13)
M
S
AHB_SFR1 (m1,s8)
H2H
OTGM
S
APB0 (32bit, m1, s16)
SS
3DM
SMFC
M
S
X2HDS
ROMeDRAM ExtDDRExt
DDR
SROMC
ExtNOR
ExtSRAM
AMCSRAM
X2P
CLK_RST PRNG TWIF SPDIF PKEI2C (x2)
APB1 (32bit, m1, s14)
X2P
UART (x5)SPI (x5) I2S (x3) ECID GPIO TIMERWDT
M
S
DDRC1SS
AHB_M
eDRAMCSS
4
S
TV_OUTM
SCAM_IN
M
S
AXI_SPINE3 (32bit, m13, s1)
EX
LCD_OUTM
S
H2H
FILE_SYSM
SDSPM
S
2
2DM
SALIVE
S
AXI_SPINE2 (32bit, m6, s2)
EX
AXI_SPINE1(64bit, m9, s1)
CAM_IN : JPEG, CAMIF, ISPDSP : AMC, ADM, ADM_INTCTV_OUT : VP, MIXER, HDOUT, HDMIFILE_SYS : SDIO, ATAPI, CEATA, ECC, FMCLCD_OUT : CLCD, LCDIFSECURITY : SHA1, AES, DATA_SEC
BUS_DATA
BUS_SFR
S
+
DSAXI IP
AHB IP
APB IP
Downsizer
EX Expander
X2P
H2H
X2H
H2X Ahb2Axi Br
Axi2Ahb Br
Ahb2Ahb Br
Axi2Apb Br
System clock frequency : 166MHzSystem clock frequency : 166MHz
400MHz
Hot issue : memory access latency by CPUHot issue : memory access latency by CPU
42 Tuesday, June 12, 2007SOO KWAN EO
Memory controller performance issueMemory controller performance issue
Memory performance factorMemory performance factorLatency : Initial latency of first transactionThroughput : Page hit ratio of successive transactions in BUSY state
Latency issue Latency issue Initial latency is meaningful for first transaction after idle region
Latency is increased when close page is accessedLatency is decreased when open page is accessed
Initial latency can be changed by different precharge scheme
PL34
0 ar
bitr
atio
n qu
eue
dept
h
sequence
Initial latency reduction is meaningful for first transaction after idle region
: idle region
43 Tuesday, June 12, 2007SOO KWAN EO
Memory controller Latency AnalysisMemory controller Latency Analysis
Performance Analyzer
• Monitoring bus subsystem behavior
• Bus utilization• Memory utilization• Memory controller
analysis
Open page analysis for memory subOpen page analysis for memory sub--systemsystemOpen page access ratio of successive transactions in busy cycleInitial latency of first transaction in IDLE stateForce precharge condition analysis
44 Tuesday, June 12, 2007SOO KWAN EO
Closing RemarksClosing Remarks
臥臥薪薪嘗嘗膽膽
45 Tuesday, June 12, 2007SOO KWAN EO
Ongoing Paradigm Shift in Ongoing Paradigm Shift in SoCSoC DesignDesignCost is the biggest issue in the semiconductor industryOne of the challenges is the productivity enhancementESL DT has been adopted at SamsungViP is one of the most efficient tools dealing with:
Architectural issuesPre-silicon software development & optimizationTechnical marketing tool for the product promotion
But, there are some issues concerning the ViP technology
Constraints(Silicon Correlation)
ROI(IP & Effort)
Verification
Design
Sequential process Concurrent process
Front loadingPrototype
46 Tuesday, June 12, 2007SOO KWAN EO
System Level Design SolutionSystem Level Design Solution
SoC Global Core Competency
SoC Global Core Competency
Expert on System Expert on System ArchitectArchitect
System-level component reuse
Improved System-level power estimation techniques
Network on chip (NoC) design method
Automated interface synthesis
Automated HW-SW co-design & verification
47 Tuesday, June 12, 2007SOO KWAN EO
Vision: Virtual Design Kit (Vision: Virtual Design Kit (VViiDKDK))
RF, Analog ICs
Mobile AP
Baseband Modem
Smart Card, SIM
Mobile Camera ChipsetCMOS Image Sensor
Flash Card Controller
Display Driver
Wireless LAN, GPS, TV
ViP’s
RTOS
Software
FeaturesFeatures
Visualization of product concept & requirements
SoC specification derivation & verification
SoC architecture exploration & integration
System software development & verification
Real-time HW/SW Co-verification
Link to Test board for the system test
48 Tuesday, June 12, 2007SOO KWAN EO
“ESL Design and Verification” by Brian Bailey, Grant Martin & Andrew Piziali, 2007, published by Elsevier Morgan Kaufmann.
ISBN 13: 978-0-12-373551-5ISBN 10: 0-12-373551-3
Web sites:
Relates to the book, http://www.electronicsystemlevel.com/"Forum" on ESL that all of you can join and participate in,http://www.electronicsystemlevel.com/phpBB/index.php
Recommended Book to ReadRecommended Book to Read
http://www.electronicsystemlevel.com/http://www.electronicsystemlevel.com/phpBB/index.php
49 Tuesday, June 12, 2007SOO KWAN EO
SystemSystem--onon--Chip: Chip: SoCSoC
algorithms
manufacturing
SoC design integrates all the disciplines andspecialty groups into a team effort
SoC 란 무엇인가 ?System knowledge + Semiconductor technology + Software
50 Tuesday, June 12, 2007SOO KWAN EO
Beating Out IntelBeating Out Intel
SETMEMORY
SoC제조
51 Tuesday, June 12, 2007SOO KWAN EO
PlatformPlatform--based Design: based Design: VViiPP (Virtual Platform)(Virtual Platform)
Memory subsystem
• Memory controller• mDDR, DDR2, XDR,…• Hierarchical memory• Cache,…
Computationsubsystem
• DSP cores• Hard/Soft macros• Algorithm/IP• Application software
CPU subsystem• Processor cores• Peripherals• RTOS• Device driver• Middleware
Communicationsubsystem
• AMBA 2/3, OCP bus• Proprietary bus• Arbiter• Bridges
Function-accurate and cycle-approximate HW/SW system simulation model
FunctionFunction--accurate and cycleaccurate and cycle--approximate approximate HW/SW system simulation modelHW/SW system simulation model
High speed simulationwith high-level models (TLM)
High speed simulationHigh speed simulationwith highwith high--level models (TLM)level models (TLM)
52 Tuesday, June 12, 2007SOO KWAN EO
Tales from the trenches @ SamsungTales from the trenches @ SamsungToo much modeling effort @ TLM – IA & CA modelseSW design @ TLM: Too slow to behavioral and Less accurate than RTLLow ROI ?: Point tools & Lack of vertical/horizontal interoperabilityLack of equivalence checker and TLM coding rule checkerToo difficult to insert/extract non-functional parametersLack of common verification suite in different levels of abstractionNo Bi-annotation of design constraints from behavioral to RTL modelsFew IP @ TLM libraries available and insufficient reusabilityMore & more model-based, platform-based SoC designsLack of well-educated system architecture engineersLess & less new SoC designs with new technology nodeMore & more complex SoC designs and ever-increasing design costAnd so on,…………..
53 Tuesday, June 12, 2007SOO KWAN EO
System Level Design Potential SolutionSystem Level Design Potential Solution
Source: ITRS 2006 Update, Design
Challenges will create strange bedfellowsChallenges will create strange bedfellows
Convergence Is On The WaySemiconductors in MobileChallenges Facing the IDM’s: Darwinian’s struggleScaling Continues But It’s Expensive!!!Gaps in High Performance & Low PowerEvolution of Design Resources AllocationSoC ChallengesJust What is ESL?Managing SoC Design CostParadigm Shift of Design-TechnologyESL Design Hype Cycle: FootprintGlobal Semiconductor MarketJust What is Virtual Platform?Samsung ViP Overview삼성 ViP 기술적 성과Samsung Experience #1Samsung Experience #2Scenario Based AnalysisViP for Worst ScenarioLevel of Model AbstractionMemory controller performance issueMemory controller Latency AnalysisOngoing Paradigm Shift in SoC DesignSystem Level Design SolutionVision: Virtual Design Kit (ViDK)Recommended Book to ReadPlatform-based Design: ViP (Virtual Platform)Tales from the trenches @ SamsungSystem Level Design Potential Solution