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Building flexible SoCs Shanghai, China September 14 th 2017

Building flexible SoCs - From silicon cores platform, SoC ... · SOC + FPGA vs SOC with eFPGA FPGA MEM CPU LOGIC SoC Latency 6 6 MEM CPU eFPGA LOGIC SoC •Latency •Power ... -

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Page 1: Building flexible SoCs - From silicon cores platform, SoC ... · SOC + FPGA vs SOC with eFPGA FPGA MEM CPU LOGIC SoC Latency 6 6 MEM CPU eFPGA LOGIC SoC •Latency •Power ... -

Building flexible SoCs

Shanghai, China

September 14th 2017

Page 2: Building flexible SoCs - From silicon cores platform, SoC ... · SOC + FPGA vs SOC with eFPGA FPGA MEM CPU LOGIC SoC Latency 6 6 MEM CPU eFPGA LOGIC SoC •Latency •Power ... -

Flexible Trusted eFPGA

Julien EYDOUX

Technical Interface Director

Page 3: Building flexible SoCs - From silicon cores platform, SoC ... · SOC + FPGA vs SOC with eFPGA FPGA MEM CPU LOGIC SoC Latency 6 6 MEM CPU eFPGA LOGIC SoC •Latency •Power ... -

Copyright © 2017 – Menta S.A.S

Company

▪ HeadQuarter: France

▪ 10 years company

▪ Only focus on eFPGA

▪ Patented technology

▪ Silicon on different foundries and nodes

▪ Customers

▪ China commercial: Jiatao

▪ Staff of 15 people

▪ Currently hiring (6 open positions)

▪ Capital: 7M$

3

Page 4: Building flexible SoCs - From silicon cores platform, SoC ... · SOC + FPGA vs SOC with eFPGA FPGA MEM CPU LOGIC SoC Latency 6 6 MEM CPU eFPGA LOGIC SoC •Latency •Power ... -

Copyright © 2017 – Menta S.A.S

System On Chip

with eFPGA

4

eFPGA

IP1 IP2MEM

CPU

Interconnect (i.e. AXI)

Interfaces

Page 5: Building flexible SoCs - From silicon cores platform, SoC ... · SOC + FPGA vs SOC with eFPGA FPGA MEM CPU LOGIC SoC Latency 6 6 MEM CPU eFPGA LOGIC SoC •Latency •Power ... -

Copyright © 2017 – Menta S.A.S

eFPGA application scenarios

5

• MCU variants• Co-processor:

– AI

– Automotive

– Data center

– ISP

• Signal Processing

• Sensor Hub

• Security / Cryptography

• Satellite payload

Page 6: Building flexible SoCs - From silicon cores platform, SoC ... · SOC + FPGA vs SOC with eFPGA FPGA MEM CPU LOGIC SoC Latency 6 6 MEM CPU eFPGA LOGIC SoC •Latency •Power ... -

Copyright © 2017 – Menta S.A.S

SOC + FPGA

vs

SOC with eFPGA

FPGAMEM CPU

LOGIC

SoC

Latency

66

MEM CPU

LOGICeFPGA

SoC •Latency

•Power

•Cost

FPGA

Page 7: Building flexible SoCs - From silicon cores platform, SoC ... · SOC + FPGA vs SOC with eFPGA FPGA MEM CPU LOGIC SoC Latency 6 6 MEM CPU eFPGA LOGIC SoC •Latency •Power ... -

Copyright © 2017 – Menta S.A.S

7

Menta 4th Generation eFPGA

embedded Logic Block• Menta Look Up Table (MLUT)

• Carry chain

• Patented technology

embedded DSP Block• MAC

• Complex DSP

• Customer/3rd Party DSP

embedded Memory block• From Memory compiler (Foundry/Mem/Customer Provider)

• Type and size can be choosen

IO pinsDefine pins number

Configuration• Classical interface

• Optional soft IP (SPI/AHB)

DFT• Standard scan chain interface

• Patented technology

Page 8: Building flexible SoCs - From silicon cores platform, SoC ... · SOC + FPGA vs SOC with eFPGA FPGA MEM CPU LOGIC SoC Latency 6 6 MEM CPU eFPGA LOGIC SoC •Latency •Power ... -

Copyright © 2017 – Menta S.A.S

100% Standard Cell

Trusted eFPGA Hard-Macro

• 100% standard cell based

– From Std Cell provider library (Synopsys, ARM, etc…)

– Or from Foundry library (TSMC, GF, SMIC, UMC, etc…)

– Or from Customer library

• Standard EDA integration:

– No Blackbox

– Full Gate Level netlist Simulation

– STA + timings accuracy

– Power accuracy

– ATPG + vector files

– Cadence/Synopsys/Mentor compatibility

8

Standard cell

Customer can verify every stage

Page 9: Building flexible SoCs - From silicon cores platform, SoC ... · SOC + FPGA vs SOC with eFPGA FPGA MEM CPU LOGIC SoC Latency 6 6 MEM CPU eFPGA LOGIC SoC •Latency •Power ... -

Copyright © 2017 – Menta S.A.S

Trusted configuration

Not SRAM based

• SRAM eFPGA # SRAM Compiler

• SRAM eFPGA

– SRAM dedicated cell must be developed

– DFT not standard => custom DFT

– Characterization and testchip

• MENTA

– Use Standard-Cell Register technology

– Patented architecture

– Standard DFT (managed by EDA tools): FC=99.9%

– Very fast test time => low cost test

– Standard verification

– High Yield

– Less prone to radiation errors (SEU)

– Don’t need characterization or testchip9

Page 10: Building flexible SoCs - From silicon cores platform, SoC ... · SOC + FPGA vs SOC with eFPGA FPGA MEM CPU LOGIC SoC Latency 6 6 MEM CPU eFPGA LOGIC SoC •Latency •Power ... -

Copyright © 2017 – Menta S.A.S

Trusted

Standard Integration

10

SOC eFPGA software

SOC

design

+

verification

TAPEOUT

Origami

Programmer

SOC RTLRTL

applicationeFPGA

Hard Macro

eFPGA Hardware

GDS/NETLIST

Bitstream

Bitstream

STIL/SDF/LIB

ASIC provider

Menta

Page 11: Building flexible SoCs - From silicon cores platform, SoC ... · SOC + FPGA vs SOC with eFPGA FPGA MEM CPU LOGIC SoC Latency 6 6 MEM CPU eFPGA LOGIC SoC •Latency •Power ... -

Copyright © 2017 – Menta S.A.S

flexible eFPGA

11

Technology

• Foundry & node

• Standard cells provider

• Voltages

• VT flavors

• Metal stack

eFPGA fabric

• Form factor

• # IOs

• # LUTs

• DSP:

- Menta 18bits MAC

- Menta Complex DSP

- Customer blocks

• Memory # & types

Power and Speed

Trade-off

Up to 500k equivalent ASIC Gates

Page 12: Building flexible SoCs - From silicon cores platform, SoC ... · SOC + FPGA vs SOC with eFPGA FPGA MEM CPU LOGIC SoC Latency 6 6 MEM CPU eFPGA LOGIC SoC •Latency •Power ... -

Copyright © 2017 – Menta S.A.S

12

Trusted

Programming Software

• IEEE VHDL/Verilog/SystemVerilog

• Routing congestion map

• LUT, FF, DSP resources

• Automatic DSP/MEM inferring

• Max Freq result

• STA

• Verilog model + SDF back-annotation

• Floorplanning

EXPORT CONTROL ISSUES FREE

Page 13: Building flexible SoCs - From silicon cores platform, SoC ... · SOC + FPGA vs SOC with eFPGA FPGA MEM CPU LOGIC SoC Latency 6 6 MEM CPU eFPGA LOGIC SoC •Latency •Power ... -

Copyright © 2017 – Menta S.A.S

Menta offers

Pre-defined IP Menta (IPM)

Off-the-shelf eFPGA IP

Family of 5 optimized IPs

- From 7K to 60K equivalent ASIC gates

- Physical IP (GDSII)

Packaged with Origami Programmer13

Page 14: Building flexible SoCs - From silicon cores platform, SoC ... · SOC + FPGA vs SOC with eFPGA FPGA MEM CPU LOGIC SoC Latency 6 6 MEM CPU eFPGA LOGIC SoC •Latency •Power ... -

Copyright © 2017 – Menta S.A.S

Menta offers

Dedicated eFPGA IP

eFPGA designed with Origami Designer

and physically implemented by Menta

Menta deliverables:

- Up to 500K equivalent ASIC gates

- eFPGA dedicated array

- Physical Hard-Macro (GDSII)

Packaged with Origami Programmer

Pre-defined IP Menta (IPM)

Off-the-shelf eFPGA IP

Family of 5 optimized IPs

- From 7K to 60K equivalent ASIC gates

- Physical IP (GDSII)

Packaged with Origami Programmer14

Page 15: Building flexible SoCs - From silicon cores platform, SoC ... · SOC + FPGA vs SOC with eFPGA FPGA MEM CPU LOGIC SoC Latency 6 6 MEM CPU eFPGA LOGIC SoC •Latency •Power ... -

[email protected]

www.menta-efpga.com

Our partner in China

See us at our Booth

Page 16: Building flexible SoCs - From silicon cores platform, SoC ... · SOC + FPGA vs SOC with eFPGA FPGA MEM CPU LOGIC SoC Latency 6 6 MEM CPU eFPGA LOGIC SoC •Latency •Power ... -

谢谢


CPU Sizing vs. Latency Analysis FTS EDR Latency Simulation

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