SMART Modular Industrial-Grade Single-Chip Disk Drive (SCDD)c1170156.r56.cf3.rackcdn.com/UK_SMO_SG9SCDD2GHYB9_DS.pdf · ©2010 SMART Modular Technologies 2.0 PRODUCT DESCRIPTION The

SMART Modular Industrial-GradeSingle-Chip Disk Drive (SCDD)

SG9SCDSxxxHYBxxx

August 2010, Rev D

www.smartm.com

ESD Caution – HandlingStatic electricity may be discharged through this disk subsystem. In extreme cases, this may temporarily interrupt the operation or damage components. To prevent this, make sure you are working in an ESD-safe environment. For example, before handling the disk subsystem, touch a grounded device, such as a computer case, prior to handling.

SMART Modular Technologies39870 Eureka Dr.Newark, CA 94560(510) 623-1231 voice(510) 623-1434 [email protected] An ISO 9001 certified company.

© 2010 SMART Modular Technologies. All rights reserved.

REVISION HISTORY

Date Revision Section(s) Description

Jan 2010 A All Preliminary Release

Jan 2010 B 6 Added timing information for different modes.

Apr 2010 C All Updated based on DVT results; added packaging material and evaluation board sections.

Aug 2010 D Reflow Profile Added reflow profile section.

PRODUCT SPECIFICATION

Single-Chip Disk DriveSG9SCDSxxxHYBxxx

August 2010

TABLE OF CONTENTS1.0 General Description . . . . . . . . . . . . . . . .2

1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . 21.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . 31.3 Operational Characteristics. . . . . . . . . 4

1.3.1 Performance . . . . . . . . . . . . . . . . . 41.3.2 Reliability . . . . . . . . . . . . . . . . . . . . 41.3.3 Power Requirements . . . . . . . . . . . 51.3.4 Environmental Conditions

(Pending) . . . . . . . . . . . . . . . . . . . . 51.3.5 Physical Characteristics . . . . . . . . 6

2.0 Product Description . . . . . . . . . . . . . . . .72.1 SCDD Dimensions . . . . . . . . . . . . . . . . 72.2 PCB Footprint . . . . . . . . . . . . . . . . . . . . 72.3 Functional Block Diagram . . . . . . . . . . 82.4 Mean Time Between Failures (MTBF) . 92.5 Reflow Profile . . . . . . . . . . . . . . . . . . . . 9

3.0 Electrical Specification. . . . . . . . . . . . . .93.1 Electrical Interface . . . . . . . . . . . . . . . . 9

3.1.1 52-Pin BGA Pinouts. . . . . . . . . . . 103.1.2 Signal Descriptions . . . . . . . . . . . 12

3.2 Absolute Maximum Ratings. . . . . . . . 163.3 Recommended Operating

Conditions. . . . . . . . . . . . . . . . . . . . . . 163.4 DC Characteristics . . . . . . . . . . . . . . . 16

4.0 ATA Commands . . . . . . . . . . . . . . . . . 174.1 Supported ATA Commands. . . . . . . . 174.2 Supported S.M.A.R.T. Operations . . . 19

4.2.1 Supported S.M.A.R.T. Subcommands. . . . . . . . . . . . . . . 19

4.2.2 Supported S.M.A.R.T. Attributes . . . . . . . . . . . . . . . . . . . 20

4.3 Identify Device . . . . . . . . . . . . . . . . . . 20

5.0 Card Information Structure (CIS) . . . . 236.0 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6.1 Memory Mode . . . . . . . . . . . . . . . . . . . 316.1.1 Attribute Memory . . . . . . . . . . . . . 316.1.2 Common Memory . . . . . . . . . . . . 32

6.2 I/O Mode. . . . . . . . . . . . . . . . . . . . . . . . 336.3 True IDE Mode (PIO) . . . . . . . . . . . . . . 346.4 True IDE Mode (MWDMA). . . . . . . . . . 346.5 UDMA Timing . . . . . . . . . . . . . . . . . . . 35

7.0 Part Numbers . . . . . . . . . . . . . . . . . . . . 367.1 Part Numbering Information . . . . . . . 367.2 Part Number Decoder. . . . . . . . . . . . . 367.3 Packaging Material . . . . . . . . . . . . . . . 377.4 Evaluation Boards . . . . . . . . . . . . . . . 38

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Corporate Headquarters: 39870 Eureka Dr., Newark, CA 94560, USA ♦ Tel:(510) 623-1231 ♦ Fax:(510) 623-1434 ♦ E-mail: [email protected] Design Center: Three Highwood Dr., Ste. 103E, Tewksbury, MA 08176, USA ♦ Tel:(978) 805-2100 ♦ Fax:(978) 805-2357Asia: Plot 18, Lrg Jelawat 4, Kawasan Perinudstrian Seberang Jaya 13700, Prai, Penang, Malaysia ♦ Tel:+604-3992909 ♦ Fax:+604-3992903

©2010 SMART Modular Technologies


Single-Chip Disk DriveSG9SCDSxxxHYBxxxAugust 2010

1.0 GENERAL DESCRIPTION

1.1 OverviewSMART is a leading independent manufacturer of memory and embedded modular sub-systems, inclusive ofboard-level through systems-level design, manufacturing, test, and fulfillment services. SMART offers more than500 standard and custom products to leading OEMs in the computer, industrial, networking, and telecommunica-tions industries, worldwide.

The SMART Modular high-performance, single-chip disk drive (SCDD) product offering specifically targets theneeds of OEM markets, such as networking, telecommunications, and data communications applications. TheSCDD products are also a natural fit for mobile and embedded computing, medical, automotive, and industrialapplications.

The SMART Modular SCCD products offer reliability and high performance operation in a 52-pin BGA package.Available in capacities ranging from 128 MBytes to 4 GBytes, the SCCD products are operational in either 3.3. Vor 5 V hosts.

SMART Modular industrial-grade SCDD products offer an advanced static wear-leveling algorithm for extendingthe life span of the products in demanding applications. In addition, these flash products ensure repeatable, reli-able operation in industrial OEM applications.

The use of single-level cell (SLC) flash technology further increases the reliability of the industrial-grade SCDDproduct offering. Yielding more than two millions program/erase (P/E) cycles for most applications, SLC betterscompared to multi-level cell (MLC) technology by a factor of 10 in reliability and 2 in speed.

SMART has built its foundation by providing proven technology and quality products to the most demanding For-tune 100 OEMs. SMART engineers its products to perform at the highest degree of reliability and compatibilitywhile backing these products with outstanding services and technology expertise.

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August 2010

1.2 Features

• Type: 52-pin ball grid array (BGA) package with SLC flash technology

• Interface: PCMCIA 2.1, PC Card ATA; fully compliant to CF 3.0 and compatible with the 4.1 specification

• Interface Modes: memory mapped, I/O mapped, and true IDE

• Supported IDE Modes

PIO Modes: 0-6

Multiword DMA Modes: 0-4

Ultra DMA Modes: 0-4

• Card Interface Structure (CIS): programmed into 256 Bytes of attribute memory

• Capacities: 128 MBytes - 4 GBytes

• Low Power Dissipation:

Read Current: 30 mA @ 5 V (typical); 28 mA @ 3.3 V (typical)

Write Current: 33 mA @ 5 V (typical); 32 mA @ 3.3 V (typical)

Passive Mode: <4 mA @ 5 V; <5 mA @ 3.3 V

• Superior Flash Management

Two layers of error detection/correction (EDC/ECC) protection with four errors detected for every 512-byte sector ECC (Reed Solomon) and two-byte CRC16 correction

Full static and dynamic wear leveling

• Operating Temperatures:

Commercial: 0°C to +70°C

Industrial: -40°C to +85°C

• Self-Monitoring and Reporting Technology (S.M.A.R.T.) Support

• RoHS Compliant

• Warranty: 3 years

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1.3 Operational Characteristics

All listed values are typical unless otherwise stated.

1.3.1 Performance

1.3.2 Reliability

Table 1: Performance Characteristics

Item Performance

Read (Maximum)128 MBytes - 2 GBytes 20 MBytes/sec

4 GBytes 20 MBytes/sec

Write (Maximum)128 MBytes - 2 GBytes 9 MBytes/sec

4 GBytes 10 MBytes/sec

Command to DRQ Read < 65 μsec

Command to DRQ Write < 19 μsec

Single Sector Read < 570 μsec

Single Sector Write < 475 μsec

Power-To Ready (Time Until Drive Accepts Commands) < 16 msec

Power-To-True Ready (Time Until Drive Processes Commands) < 92 msec

Table 2: Reliability Characteristics

Item Value

Mean Time Between Failures (MTBF) > 14,000,000

Data Reliability < 1 Non-Recoverable Error in 1014 bits read

Data Retention 10 years @ 25 °C

Endurance > 2,000,000 program/erase cycles

Error Correction/Error Detection (Reed Solomon) Up to four errors detected for every 512-byte sector

CRC16 Two-byte cyclic redundancy correction

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August 2010

1.3.3 Power Requirements

1.3.4 Environmental Conditions (Pending)

1 Values are subject to change. SMART tests and ensures its products meet or exceed the environmental testing procedures and guidelines asdefined in MIL-STD 810-F.

Table 3: Power Requirements (PCMCIA 5 V)

Parameter Value (Typ) Value (Max) Unit

VCC 5 5.5 V

Read 30.0 67.0 mA

Write 33.4 67.0 mA

Idle 3.8 -- mA

Table 4: Power Requirements (PCMCIA 3.3 V)


VCC 3.3 3.5 V

Read 28.8 66.1 mA

Write 32.1 66.1 mA

Idle 4.9 -- mA

Table 5: Power Requirements (True IDE 5.0 V)


VCC 5.0 5.5 V

Read 125 125 mA

Write 84 125 mA

Idle 8.6 -- mA

Table 6: Environmental Conditions and Testing (Pending)1

Parameter Value

Shock – Operating 50 g maximum @ 11 msec

Vibration – Operating 15 g peak-to-peak

Operating TemperatureCommercial 0 °C to 70 °C

Industrial -40 °C to +85 °C

Storage Temperature -65 °C to 150 °C

Humidity 5% to 95%

Altitude 24,384 m [80,000 ft]

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1.3.5 Physical Characteristics

Table 7: Physical Characteristics

Parameter Value

Length 22.73 mm [0.90 in]

Width 20.24 mm [0.80 in]

Height 3.38 mm [0.13 in]

Weight (Maximum) 3.30 g [0.12 oz]

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August 2010

2.0 PRODUCT DESCRIPTIONThe industrial-grade SCDD product contains an ATA/IDE controller and one flash memory device. The ATA/IDEcontroller interfaces with a host system, allowing data to be written to and read from the flash memory devices.

2.1 SCDD DimensionsFigure 1: Single-Chip Disk Drive Dimensions (in mm [inches])

2.2 PCB FootprintFigure 2: Footprint (in mils)

20.24 [0.80]

22.73 [0.90]

20.24 [0.80] 3.38 [0.13]

Pin 1

766 mil 24 mil DIA (TYP)

30 mil

60 mil

P1P2

P14P15

P12P13

P25P26

P27P28

P38P39

P40P41

P51P52

812 mil

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2.3 Functional Block DiagramFigure 3: Single-Chip Disk Drive Block Diagram

Host Interface F3-LCT05

Voltage Regulators

Internal Oscillator, POR, V Detector

CE1

CE2

REG#

A[10:0}

OE#

IORD#

WE#

IOWR#

RST

CSEL

D[15:0]

PDAGI

DASP

IRQ

IORDY

IOCS16

DREQ

Cha

nnel

0C

hann

el 1

Flash Memory (Channel 0)

F0D[7:0]

F0CLE

F0ALE

F0RE

F0WE

F0WP

F0CE0

F0RB0

NOTE: All signals shown going to the flash devices come from the card controller. All the other signals, including those going to the card controller, come from the card interface.

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August 2010

2.4 Mean Time Between Failures (MTBF)

The MTBF statistic for the SCDD, shown below, was calculated based on the RDF2000 UTE C80-810 TelecomStandard at 25°C.

2.5 Reflow ProfileThe reflow profile parameters for the SCDD are listed in the following table.

3.0 ELECTRICAL SPECIFICATION

3.1 Electrical InterfaceThe SCDD functions in three basic modes: PC Card ATA using I/O mode; PC Card ATA using memory mode; andtrue IDE mode. The SCDD is also fully compliant with CF 3.0 and compatible with 4.1 specifications.

The following table lists the I/O signals in the three operating modes. Host-generated signals are designated asinputs (I), drive-generated signals are designated as outputs (O), and bi-directional signals are designated asinput/output (I/O). The SCDD logic levels conform to those specified in the PCMCIA Release 2.1 specification.

Table 8: MTBF Values

Capacity MTBF (Hours)

4 GBytes >14,000,00

Table 9: Reflow Profile Parameters

Parameter Lead-Free (SnAgCu)

Peak Temperature 235-250 °C

Time Above Liquidus 45-70 sec

Cooling Rate <4 °C/sec

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3.1.1 52-Pin BGA Pinouts

Table 10: 52-Pin BGA Pinouts

PinCard Memory Mode Card I/O Mode True IDE Mode

Signal Name In/Out Signal Name In/Out Signal Name In/Out

1 D8 I/O D8 I/O D8 I/O

2 BVD1 I/O STSCHG# I/O PDIAG# I/O

3 BVD2 I/O SPKR# I/O DASP# I/O

4 REG# DMACK# I REG# DMACK I DMACK# I

5 INPACK# DMARQ# O INPACK# DMARQ# O DMARQ O

6 WAIT# DDMARDY# DSTROBE O WAIT# DDMARDY#

DSTROBE O IORDY DDMARDY# DSTROBE O

7 RESET I RESET I RESET# I

8 CE1# I CE1# I CSO# I

9 D7 I/O D7 I/O D7 I/O

10 D6 I/O D6 I/O D6 I/O

11 D5 I/O D5 I/O D5 I/O

12 VSS GND VSS GND VSS GND

13 VCC PWR VCC PWR VCC PWR

14 D1 I/O D1 I/O D1 I/O

15 D0 I/O D0 I/O D0 I/O

16 A0 I A0 I A0 I

17 A1 I A1 I A1 I

18 A2 I A2 I A2 I

19 A3 I A3 I A3 I

20 CE2# I CE2# I CS1# I

21 D15 I/O D15 I/O D15 I/O

22 D14 I/O D14 I/O D14 I/O

23 D13 I/O D13 I/O D13 I/O

24 D12 I/O D12 I/O D12 I/O






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August 2010

30 D9 I/O D9 I/O D9 I/O

31 D10 I/O D10 I/O D10 I/O

32 A5 I A5 I A5 I

33 A6 I A6 I A6 I

34 A7 I A7 I A7 I

35 A8 I A8 I A8 I

36 A9 I A9 I A9 I

37 OE# I OE# I OE# I

38 D3 I/O D3 I/O D3 I/O

39 D4 I/O D4 I/O D4 I/O



42 D2 I/O D2 I/O D2 I/O

43 WP O IOIS16# O IOCS16# O

44 A4 I A4 I A4 I

45 CSEL# I CSEL# I CSEL# I

46 RDYBSY# O IREQ O INTRQ O

47 WE# I WE# I WE# I

48 IOWR# STOP I IOWR# STOP I IOWR# STOP I

49 IORD# HSTROBE HDMARDY I IORD# HSTROBE

HDMARDY I IORD# HSTROBE HDMARDY I

50 A10 I A10 I A10 I

51 D11 I/O D11 I/O D11 I/O


Table 10: 52-Pin BGA Pinouts (Continued)

PinCard Memory Mode Card I/O Mode True IDE Mode

Signal Name In/Out Signal Name In/Out Signal Name In/Out

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3.1.2 Signal Descriptions

Table 11: Signal Descriptions

Signal Name Pin(s) Mode of Operation Signal Description

IOWR#/STOP

48

I/O Write Input

IOWR#

Card Memory Not used.

Card I/OThe I/O Write strobe pulse is used to clock I/O data on the card data bus in the controller registers. The clocking occurs on the negative to positive going edge of the signal.

True IDE This signal has the same function as in card I/O mode when Ultra DMA mode is not active.

STOP All Modes – UDMA Protocol Active

When UDMA mode is active, asserting this signal terminates the UDMA burst.

IORD# 49

I/O Read Input


Card I/O This is a host-generated I/O Read strobe. This signal gates I/O data onto the bus from the card.True IDE

WE# 47

Write Enable Input

Card MemoryThis is a host-driven signal used for strobing memory write data to the registers of the card. It is also used for writing the configuration regis-ters.

Card I/O This signal is used to write the CIS and configuration registers.

True IDE This input signal is not used and should be connected to VCC by the host.

OE# 37

Output Enable Input

Card Memory This is a host-generated strobe used to read data from the card and to read the CIS and configuration registers.

Card I/O This signal is used to read the CIS and configuration registers only.

True IDE This input should be grounded by the host to enable true IDE mode.

VSS12, 25,27, 28, 29, 52

All Ground.

VCC 13, 26, 40, 41 All Power supply.

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August 2010

RESET/RESET#

7

Card Reset Input

RESET

Card Memory When this pin is high, the signal resets the flash card. The card is reset only at power up if this pin is left high or open. The card is also reset when the SOFT RESET bit in the Card Configuration Option register is set.

Card I/O

RESET# True IDE This input pin is active low from the host.

CE1#, CE2#/CS0#, CS1#

8, 20

Card Enable Inputs

CE1#, CE2#

Card Memory These input signals are used both to select the card and to indicate to the card whether a byte or a word operation is being performed. CE2# always accesses the odd byte of the word. CE1# accesses the even bye or the odd byte of the word depending on A0 and CE2#. A multi-plexing scheme based on A0, CE1#, and CE2# allows 8-bit hosts to access all data on D0-D7.

Card I/O

CS0#, CS1# True IDE

CS0# is the address range select for the task file registers while CS1# is used to select the Alternate Status register and the Device Control regis-ter. While DMACK# is asserted, CS0# and CS1# shall be held negated, and the width of the transfers shall be 16 bits.

WP/IOIS16#/IOCS16#

43

Write Protect/I/O Port 16 Output

WP Card Memory Because the card does not have a WP switch, this signal is held low after a reset initialization sequence.

IOIS16# Card I/O A low signal indicates that a 16-bit or odd-byte only operation can be performed.

IOCS16# True IDE This signal is asserted low when the card is expecting a word data transfer cycle. This open collector line is only driven on assertion (low).

CSEL# 45

Cable Select Input


Card I/O Not used.

True IDEThis signal is used to configure the device as Master or Slave. When this pin is grounded, the device is configured as Master. When tied to VCC, the card is configured as Slave.

[D15:D0]

1, 9-11, 14, 15, 21-24, 30, 31, 38, 39, 42, 51

16-Bit Data Input/Output Bus

Card Memory These lines carry the data, commands, and status information between the host and the controller. D15 is the most-significant bit (MSB) of the odd byte of the word, and D7 is the MSB of the even byte of the word.Card I/O

True IDE All register operations occur in byte mode on D7-D0, while all data transfers are word (16-bit) accesses.

Table 11: Signal Descriptions (Continued)


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[A10:A0]16-19, 32-36, 44, 50

Card Address Input Bus

Card Memory

These addresses, along with the REG# signal, are used to select the following: the I/O port address registers in the card; the memory-mapped port address registers; a byte in the CIS and the Configuration Control and Status registers.

[A2:A0] 16-18 True IDEOnly A2-A0 are used to select one of the Control/Status registers. All remaining unused address lines should be grounded by the host and on the CF card.

REG#/DMACK#

4

Attribute Memory Select Input/DMA Acknowledge

REG#Card Memory This signal is used to select between Register/Attribute Memory (REG#

= low) and Common Memory (REG# = high).

Card I/O Active low on this signal allows access to I/O space.

DMACK# True IDE

This is the DMA Acknowledge signal that is used for DMA data transfers between the host and the device. The device shall assert his signal when the device is ready to transfer data to or from the host. This signal is used in a handshake manner with DREQ.

RDY/BSY#/IREQ#/INTRQ

46

Ready/Interrupt Request Output

RDY/BSY# Card Memory

This signal is set high when the card is ready to accept a new data transfer operation and held low when the card is busy. The host must have a pull-up resistor on this signal. When powering up and when resetting, the signal is held low (busy) until the card has completed the power up or reset operation. When the signal indicates busy, no opera-tions to the card are permitted. The signal is held high whenever the card has been powered up with RESET# disconnected or asserted.

IREQ# Card I/O This signal is used as an interrupt request. This line is strobed low to generate a pulse-mode interrupt or held low for a level-mode interrupt.

INTRQ True IDE THe signal is the active high interrupt request to the host.

WAIT#/IORDY

6

Extend BUs Cycle/I/O Channel Ready Output

WAIT#Card Memory

Not used; pulled up to VCC.Card I/O

IORDY True IDEThis signal is held low to extend the host transfer of any host register access (read or write) when the card is not ready to respond to a data transfer request.



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August 2010

INPACK#/DREQ

5

Input Port Acknowledge Output/DMA Request

INPACK#


Card I/O

The CF card asserts the Input Acknowledge signal when the card is selected and responding to an I/O read cycle at the address on the address bus. The host uses this signal to control the enabling of any input data buffers between the CF card and the CPU. Hosts that support a single socket per interface logic, such as for Advanced Timing MOdes and UDMA operations, may ignore the INPACK# signal from the device and manage the input buffers based solely on the Card Enable signals.

DREQ True IDE

THis is the DMA Request that is used for DMA data transfers between the host and device. The device asserts this when the device is ready to transfer data to or from the host. This signal is used in a handshake manner with DMACK#.

BVD1/STSCHG#/PDIAG#

2

Battery Voltage Detect Output 1/Card Status Changed Output/Passed Diagnostics Input/Output

BVD1 Card Memory This signal is asserted high because the card does not maintain a bat-tery.

STSCHG# Card I/OThis signal is asserted low to alert the host to changes in the RDY/BSY# and Write Protect states. The Card Configuration and Status reg-isters control the use of this signal.

PDIAG# True IDEThe slave drive asserts this signal to indicate to the master drive that the slave drive has completed diagnostics and is ready to provide sta-tus.

BVD2/SPKR#/DASP#

3

Battery Voltage Detect Output 2/Audio Waveform Output/Drive Active/Drive 1 Preset Output

BVD2 Card Memory This signal is asserted high because the card does not maintain a bat-tery.

SPKR# Card I/O This signal is asserted high because the card does not support audio.

DASP# True IDE This signal indicates a drive is active or a slave drive (drive 1) is pres-ent.



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3.2 Absolute Maximum Ratings

3.3 Recommended Operating Conditions

3.4 DC Characteristics

Table 12: Voltage and Storage Temperature

Symbol Parameter Ratings (Max) Unit

VCC 3.3 V Supply Voltage 3.47 V

VCC 5.0 V Supply Voltage 5.5 V

IACTIVE Active Current @ 3.3 V 66.1 mA

IACTIVE Active Current @ 5.0 V 125 mA

TSTG Storage Temperature -55 to +70 °C

Table 13: Recommended Operating Conditions

Symbol Parameter Ratings Unit

VCC 3.3 V Supply Voltage 3.3 ± 5% V

VCC 5 V Supply Voltage 5 ± 10% V

TA Operating Temperature – Commercial 0 to +70 °C

TA Operating Temperature – Industrial -40 to +85 °C

Table 14: DC Characteristics (PCMCIA)

Symbol Parameter Typical Max Unit Condition

IRD3 Active Read Current 28.8 66.1 mA VCC = 3.3 V

IWR3 Active Write Current 32.1 66.1 mA VCC = 3.3 V

IIDLE3 Idle Current 4.9 -- mA VCC = 3.3 V

IRD5 Active Read Current 30.0 67.0 mA VCC = 5 V

IWR5 Active Write Current 33.4 67.0 mA VCC = 5 V

IIDLE5 Idle Current 3.8 -- mA VCC = 5 V

Table 15: DC Characteristics (True IDE)

Symbol Parameter Typical Max Unit Condition

IRD5 Active Read Current 125 125 mA VCC = 5 V

IWR5 Active Write Current 84 125 mA VCC = 5 V

IIDLE5 Idle Current 8.6 -- mA VCC = 5 V

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August 2010

4.0 ATA COMMANDSThis section documents the host interface commands the SCDD controller supports. Two standard classes ofinterface specifications are currently implemented: the ATA interface specification, when operating in true IDEmode; and the PC Card specification, when operating in a PC card mode.

4.1 Supported ATA CommandsThe SCDD supports the standard commands listed in Table 15. For more detailed descriptions of the commands,please refer to the ATA-6 specification.

Table 16: Supported ATA Commands

Command Name Op Code (Hex) Command Set (Category)

Check Power Mode E5 PwrMgmt

98 PwrMgmt

CFA Erase Sector(s) C0 CFA

CFA Translate Sector 87 CFA

CFA Request Extended Error 03 CFA

CFA Write Sector(s) w/o Erase 38 CFA

CFA Write Multiple w/o Erase CD CFA

Execute Device Diagnostic 90 General

Flush Cache E7 General

Format Track 50 Vendor-Specific

Identify Device EC General

IdleE3 PwrMgmt

97 PwrMgmt

Idle ImmediateE1 PwrMgmt

95 PwrMgmt

Initialize Device Parameters 91 General

Media Lock DE Removable Media

Media Unlock DF Removable Media

NOP 00 General

Read Buffer E4 General

Read DMA C8 General

Read DMA w/out Retries C9 General

Read Long 22 General

Read Long w/out Retries 23 General

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Read Multiple C4 General

Read Native Max Address F8 HPA

Read Sector(s) 20 General

Read Sector(s) w/out Retries 21 General

Read Verify Sector(s) 40 General

Read Verify Sector(s) w/out Retries 41 General

Recalibrate 10-1F General

Seek 70-7F General

Set Features EF General

Set Max Address F9 HPA

Set Multiple Mode C6 General

Set Sleep ModeE6 PwrMgmt

99 PwrMgmt

S.M.A.R.T. Operations B0 S.M.A.R.T.

StandbyE2 PwrMgmt

96 PwrMgmt

Standby ImmediateE0 PwrMgmt

94 PwrMgmt

Wear Level F5

Write Buffer E8 General

Write DMA CA General

Write DMA w/out Retries CB General

Write Long 32 General

Write Long w/out Retries 33 General

Write Multiple C5 General

Write Sector(s) 30 General

Write Sector(s) w/out Retries 31 General

Write Verify 3C General

Table 16: Supported ATA Commands (Continued)

Command Name Op Code (Hex) Command Set (Category)

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August 2010

4.2 Supported S.M.A.R.T. Operations

Self-monitoring analysis and reporting technology (S.M.A.R.T.) commands provide diagnostic information regard-ing drive operation and, in certain cases, can assist in predicting drive degradation. Because S.M.A.R.T. alerts thehost of possible drive problems, users can assess the situation and back up data prior to an operational failure.

Each S.M.A.R.T. attribute monitors a specific drive condition, with threshold levels configured for select attributes.When the drive exceeds these thresholds, the S.M.A.R.T. attribute reports the condition. In many cases, exceed-ing the threshold simply indicates you should monitor the drive more closely. Host systems initiate commands,generated manually or with a third-party diagnostic tool, to monitor S.M.A.R.T. attributes.

Although the SCDD supports several S.M.A.R.T. operations, which are subcommands of the S.M.A.R.T. Opera-tions command (see Table 16), the S.M.A.R.T. Return Status and S.M.A.R.T. Read Data subcommands are usedfor monitoring the drive.

Initiating a S.M.A.R.T. Return Status command returns the current state of the drive, specifying whether or not anattribute exceeded the assigned threshold. If an attribute has exceeded a threshold level, SMART Modular Tech-nologies recommends issuing the S.M.A.R.T. Read Data command to identify the specific attribute (see Table 17).

S.M.A.R.T. commands are issued with B0h in the Command register and the code for the desired operation in theFeatures register. A S.M.A.R.T. Enable Operations must be issued before any other S.M.A.R.T. command can beperformed.

4.2.1 Supported S.M.A.R.T. Subcommands

Table 17: Supported S.M.A.R.T. Subcommands

Subcommand Name Feature Code (Hex)

S.M.A.R.T. Read Data D0

S.M.A.R.T. Read Attribute Thresholds D1

S.M.A.R.T. Enable/Disable Autosave D2

S.M.A.R.T. Enable Operations D8

S.M.A.R.T. Disable Operations D9

S.M.A.R.T. Return Status DA

S.M.A.R.T. Read Remap Data E0

S.M.A.R.T. Read Wear Level Data E1

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4.2.2 Supported S.M.A.R.T. Attributes

4.3 Identify DeviceThe Identify Device command passes one sector of data to the host. This data describes the flash drive parame-ters. See the following table for a detailed description of the Identify Device information.

Table 18: Supported S.M.A.R.T. Attributes

Attribute ID (Dec) Name Possible

Values Indicates

196 Spare Block Count 0-100 The minimum remaining spare blocks as a percentage of the initial spare blocks for all flash chips.

199 UDMA CRC Errors The total number of UDMA CRC errors that have occurred.

203 Total ECC Errors The total number of ECC errors that have occurred (both correctable and uncorrectable).

204 Correctable ECC Errors The total number of correctable ECC errors that have occurred.

229 Erase Count 0-100An estimate of the remaining card life as a percentage of the number of flash block erases compared to the target number of erase cycles per block.

232 Total Number of Reads 0-100 The total number of flash read commands the drive received.

Table 19: Identify Device Information

Identify Device Information

Word(s) Data Description

0045Ah General configuration, bit-significant information True-IDE mode

848Ah General configuration, bit-significant information PCMCIA mode

1 See Note Number of cylinders

2 0000h Reserved

3 See Note Number of heads

4 0000h Number of unformatted bytes per track

5 0200h Number of unformatted bytes per sector

6 See Note Number of sectors per track

7-8 See Note Number of sectors per card (Word 7 = MSW, Word 8 = LSW)

9 0000h Reserved

10-19 XXXXh 20-character serial number in ASCII

20 0002h Buffer type (dual-ported multi-sector)

21 0001h Buffer size in 512-byte increments

22 0004h Number of ECC bytes passed on Read/Write Long commands

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August 2010

23-26 XXXXh Firmware revision in ASCII

27-46 [Model Number] SMART

47 8001h Maximum number of sectors on Read/Write Multiple command

48 0000h Reserved

490F00h Capabilities: LBA, IORDY, DMA supported True-IDE mode

0E00h Capabilities: LBA, IORDY supported PCMCIA mode

50 0000h Capabilities

51 0200h PIO data transfer cycle timing mode 2

52 0000h DMA data transfer cycle timing mode not supported

53 0007h Words 54-58 and 64-70 are valid

54 See Note Number of current logical cylinders

55 See Note Number of current logical heads

56 See Note Number of current logical sectors per track

57-58 See Note Current capacity in sectors (Word 57 = LSW, Word 58 = MSW)

59 010Xh Multiple sector setting is valid

60-61 See Note Total number of user addressable LBAs

62 0000h Single word DMA transfer not implemented

630X0Xh Multiword DMA transfer, -mdma preformat option True-IDE mode

0000h Multiword DMA transfer mode not supported PCMCIA mode

64 0003h Advanced PIO modes 3 and 4 supported

650078h Minimum Multiword DMA cycle time True-IDE mode

0000h Minimum Multiword DMA cycle time PCMCIA mode

660078h Recommended Multiword DMA cycle time True-IDE mode

0000h Recommended Multiword DMA cycle time PCMCIA mode

67 0078h Minimum PIO transfer cycle time without flow control

68 0078h Minimum PIO transfer cycle time with flow control

69-79 0000h Reserved

80 0020h Major version number, ATA-5 supported

81 0000h Minor version number, not reported

82 7409h Command set: NOP, READ BUFFER, WRITE BUFFER, host-protected area, power management feature set, S.M.A.R.T. feature set

Table 19: Identify Device Information (Continued)



- 21 -





NOTE: The value is dependent on the total capacity of the specific drive.

83 5004h Command set: FLUSH CACHE, CFA feature set

84 4000h Command set/feature set supported extension

85 740XhCommand set enabled: NOP, READ BUFFER, WRITE BUFFER, host-protected area, power management feature set, S.M.A.R.T. feature set enabled/disabled

86 1004h Command set enabled: FLUSH CACHE, CFA feature set

87 4000h Command set/feature default

88XXXXh UDMA mode, according to -udma preformat option True-IDE mode

0000h PCMCIA mode


93 XXXXh Hardware Reset result


129 XX00h Write protect status; bit 15 = permanent write protect, no more spare blocks available

130-133 XXXXh Firmware date string

134 848Ah General configuration word for PCMCIA mode

135 045Ah General configuration word for True-IDE mode


160 A064h CFA Power Mode: no power level 1, max 100 mA

161 0000h Reserved

162 0000h Key management schemes: CPRM not supported

163XXXXh CFA advanced modes: supported and enabled bits True-IDE mode

0000h CFA advanced modes: not supported PCMCIA mode

164001Bh CFA advanced modes: 80 ns I/O and Memory

supported True-IDE mode

0000h CFA advanced modes: not supported PCMCIA mode


255 XXA5h Integrity word

Table 19: Identify Device Information (Continued)



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August 2010

5.0 CARD INFORMATION STRUCTURE (CIS)Table 20: Card Information Structure

Address Data 7 6 5 4 3 2 1 0 Description of Contents CIS Function

000H 01H CISTPL_DEVICE Device info tuple. Tuple code.

002H 03H TPL_LINK Link length is 3 bytes. Link to next tuple.

004H D9H Device Type W SpeedType=D: I/O deviceWPS=1: no WP switchSpeed=1: 250 nsecs

Device type; WPS speed

006H 01H # address units -1 unit size 2 KBytes of address space Device size

008H FFH CISTPL_END End of CISTPL_DEVICE End marker

00AH 1CH CISTPL_DEVICE_OC Common memory other operat-ing conditions tuple Tuple code

00CH 04H TPL_LINK Link length is 4 bytes Link to next tuple

00EH 02H Ext Reserved 3V M3V=1: dual voltage card, condi-tions for 3.3 V operationM=0: conditions without wait

Other conditions infor-mation

010H D9H Device Type W SpeedType=D: I/O deviceWPS=1: no WP switchSpeed=1: 250 nsecs

Device type; WPS speed

012H 01H # address units - 1 unit size 2 KBytes of address space Device size

014H FFH CISTPL_END End of CISTPL_DEVICE_OC End marker

016H 18H CISTPL_JEDEC_C JEDEC programming info tuple Tuple code

018H 02H TPL_LINK Link length is 2 bytes Link to next tuple

01AH DFH JEDEC ID Device manufacturer ID Manufacturer ID

01CH 01H JEDEC Info Manufacturer-specific info Manufacturer info

01EH 20H CISTPL_MANFID Manufacturer ID tuple Tuple code


022H 7FHTPLMID_MANF SMART JEDEC manufacturer

code Manufacturer ID024H 94H

026H 07HTPLMID_CARD Manufacturer-specific info Manufacturer info

Product code028H 00H

02AH 21H CISTPL_FUNCID Function ID tuple Tuple code

02CH 02H CISTPL_LINK Link length is two bytes Link to next tuple

02EH 04H TPLFID_FUNCTION FIxed disk drive Function code

030H 01H Reserved R P R=0: no expansion ROMP=1: configure at POST

System init byte TPLFID_SYSINIT

032H 22H CISTPL_FUNCE Function extension tuple Tuple code

- 23 -





034H 02H CISTPL_LINK Link length is 2 bytes Link to next tuple

036H 01H Disk function extension tuple Disk interface information TPLFE_TYPE

038H 01H Disk interface type PC card ATA interface TPLFE_DATA

03AH 22H CISTPLE_FUNCE Function extension tuple Tuple code

03CH 03H CISTPL_LINK Link length is 3 bytes Link to next tuple

03EH 02H DIsk function extension tuple PC card ATA basic features TPLFE_TYPE

040H 04H Reserved D U S V

D=0: single drive on cardU=0: no unique serial numberS=1: silicon deviceV=0: no VPP required

TPLFE_TYPE

042H 07H R I E N P

I=0: twin IOIS16# unspecifiedE=0: index bit not emulatedN=0: I/O includes 0x3F7P=7: sleep, standby, idle sup-ported

TPLEF_TYPE

044H 1AH CISTPL_CONFIG Configuration tuple Tuple code


048H 01H RFS RMS RASRFS: reservedRMS: 1 byte register maskRAS: 2 bytes base address

Size of fieldsTPCC_SZ

04AH 07H TPCC_LAST Last configuration entry is 07H Last entry index

04CH 00H TPCC_RADR (LSB) Configuration registers are located at 0200H

Configuration register location04EH 02H TPCC_RADR (MSB)

050H 0FH TPCC_RMSK Configuration registers 0 to 3 are present

Configuration register present mask

052H 1BH CISTPL_CFTABLE_ENTRY Configuration tuple Tuple code

054H 0BH CISTPL_LINK Link length is 11 bytes Link to next tuple

056H C0H I D Configuration Index

I=1: interface byte followsD=1: default entryIndex=0:Memory-mapped config-uration

Configuration tableIndex byteTPCE_INDX

058H C0H W R P B Interface Type

W=1: wait requiredR=1: ready/busy activeP=0: WP not usedB=0: BVD1, BVD2 not usedType=0: memory interface

Interface descriptionTPCE_IF

Table 20: Card Information Structure (Continued)


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August 2010

05AH A1H M MS IR IO T Power

M=1: misc info presentMS=1: 2-byte memory lengthIR=0: no interrupt is usedIO=0: no I/O space is usedT=0: no timing info specifiedPower=1: VCC info, no VPP

Feature selection byteTPCE_FS

05CH 27H R DI PI AI SI HV LV NV

R=reservedDI=0: no power-down currentPI=1: peak current infoAI=0: no average current infoSI=0: no static current infoHV=1: max voltage infoLV=1: min voltage infoNV=1: nominal voltage info

Power description struc-tureParameter selection byteTPCE_PD

05EH 55H X Mantissa Exponent Nominal voltage 5.0 V

060H 4DH X Mantissa Exponent Nominal voltage 4.5 V

062H 5DH X Mantissa Exponent Nominal voltage 5.5 V

064H 75H X Mantissa Exponent Peak current 80 mA

066H 08H Length in 256-byte units (LSB) Length of memory space is 2 KBytes

Memory space descrip-tionTPCE_MS068H 00H Length in 256-byte units (MSB)

06AH 21H X R P RO A T

X=0: no more misc fieldsR=reservedP=1: power-down supportedRO=0: read/write mediaA=0: audio not supportedT=1: max twins is 1

Miscellaneous featuresTPCE_MI

06CH 1BH CISTPL_CFTABLE_ENTRY Configuration tuple Tuple code

06EH 06H CISTPL_LINK Link length is 6 bytes Link to next tuple

070H 00H I D Configuration Index

I=1: interface byte followsD=1: default entryIndex=0:Memory-mapped config-uration

TPCE_INDX

072H 01H M MS IR IO T Power

M=1: misc info presentMS=1: 2-byte memory lengthIR=0: no interrupt is usedIO=0: no I/O space is usedT=0: no timing info specifiedPower=1: VCC info, no VPP

TPCE_FS



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074H 21H R DI PI AI SI HV LV NV

R=reservedDI=0: no power-down currentPI=1: peak current infoAI=0: no average current infoSI=0: no static current infoHV=1: max voltage infoLV=1: min voltage infoNV=1: nominal voltage info

TPCE_PD

076H B5H X Mantissa Exponent X=1: extension byte present

078H 1EH X Extension Nominal voltage 3.3 V

07AH 4DH X Mantissa Exponent Peak current 45 mA

07CH 1BH CISTPL_CFTABLE_ENTRY Configuration tuple Tuple code

07EH 0DH CISTPL_LINK Link length is 13 bytes Link to next tuple

080H C1H I D Configuration IndexI=1: interface byte followsD=1: default entryIndex=1: I/O mapped

TPCE_INDX

082H 41H W R P B Interface Type

W=0: wait not requiredR=1: read/busy activeP=0: WP not usedB=0: BVD1, BVD2 not usedType=1: I/O interface

TPCE_IF

084H 99H M MS IR IO T Power

M=1: misc info presentMS=0: no memory space infoIR=1: interrupt is not usedT=0: no timing info specifiedPower=1: VCC info, no VPP

TPCE_FS

086H 27H R DI PI AI SI HV LV NV

DI=0: no power-down currentPI=1: peak current infoAI=0: no average current infoSI=0: no static current infoHV=1: max voltage infoLV=1: min voltage infoNV=1: nominal voltage info

TPCE_PD

088H 55H X Mantissa Exponent Nominal voltage 5.0 V

08AH 4DH X Mantissa Exponent Nominal voltage 4.5 V

08CH 5DH X Mantissa Exponent Nominal voltage 5.5 V

08EH 75H X Mantissa Exponent Peak current 80 mA

090H 64H R S E IOS=1: support 16-bit hostsE=1: support 8-bit hostsIO=4: 4 address lines decoded

TPCE_IO



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August 2010

092H F0H S P L M V B I N

S=1: interrupt sharing logicP=1: pulse mode supportedL=1: level mode supportedM=1: masks V...N presentV=0: no vendor-unique IRQB=0: no bus error IRQI=0: no I/O check IRQN=0: no NMI

TPCE_IR

094H FFH IRQ7..0 Interrupt signal may be assigned to any host IRQ096H FFH IRQ15..8

098H 21H X R P RO A T

X=0: no more misc fieldsP=1: power-down supportedRO=0: read/write mediaA=0: audio not supportedT=1: max twins is 1

TPCE_MI

09AH 1BH CISTPL_CFTALE_ENTRY Configuration tuple Tuple code


09EH 01H I D Configuration Index Index=1: I/O mapped TPCE_INDX

0A0H 01H M MS IR IO T Power Power=1: VCC info, no VPP TPCE_FS

0A2H 21H R DI PI AI SI HV LV NV PI=1: peak current infoNV=1: nominal voltage info TPCE_PD

0A4H B5H X Mantissa Exponent X=1: extension byte present

0A6H 1EH X Extension Nominal voltage 3.3 V

0A8H 4DH X Mantissa Exponent Peak current 45 mA

0AAH 1BH CISTPL_CFTABLE_ENTRY Configuration tuple Tuple code

0ACH 12H CISTPL_LINK Link length is 18 bytes Link to next tuple

0AEH C2H I D Configuration IndexI=1: interface byte followsD=1: default entryIndex=2: I/O mapped

TPCE_INDX

0B0H 41H W R P B Interface Type

W=0: wait not requiredR=1: read/busy activeP=0: WP not usedB=0: BVD1, BVD2 not usedType=1: I/O interface

TPCE_IF

0B2H 99H M MS IR IO T Power

M=1: misc info presentMS=0: no memory space infoIR=1: interrupt is usedIO=1: I/O space is usedT=0: no timing info specifiedPower=1: VCC info, no VPP

TPCE_FS



- 27 -





0B4H 27H R DI PI AI SI HV LV NV

DI=0: no power-down currentPI=1: peak current infoSI=0: no static current infoHV=1: max voltage infoLV=1: min voltage infoNV=1: nominal voltage info

TPCE_PD

0B6H 55H X Mantissa Exponent Nominal voltage 5.0 V

0B8H 4DH X Mantissa Exponent Nominal voltage 4.5 V

0BAH 5DH X Mantissa Exponent Nominal voltage 5.5 V

0BCH 75H X Mantissa Exponent Peak current 80 mA

0BEH EAH R S E IO

R=1: range followsS=1: support 16-bit hostsE=1: support 8-bit hostsIO=10: ten lines decoded

TPCE_10

0C0H 61H LS AS NRLS=1: 1 byte lengthAS=2: 2-byte addressNR=1: 2 address ranges

0C2H F0H Base Address 1 (LSB)

Address range 1 0x1F0 to 0x1F70C4H 01H Base Address 1 (MSB)

0C6H 07H Address Range 1 Length

0C8H F6H Base Address 2 (LSB)

Address range 2 0x3F6 to 0x3F70CAH 03H Base Address 2 (MSB)

0CCH 01H Address Range 2 Length

0CEH EEH S P L M IRQN

S=1: interrupt sharing logicP=1: pulse mode supportedL=1: level mode supportedM=0: masks V..N not presentIRQN=14: use interrupt 14

TPCE_IR

0D0H 21H X R P RO A T


TPCE_MI

0D2H 1BH CISTPL_CFTABLE_ENTRY Configuration tuple Tuple code

0D4H 06H CISTPL_LINK Link length is 6 bytes Link to next tuple

0D6H 02H I D Configuration Index Index=2: I/O mapped TPCE_INDX

0D8H 01H M MS IR IO T Power Power=1: VCC info, no VPP TPCE_FS

0DAH 21H R DI PI AI SI HV LV NV PI=1: peak current infoNV=1: nominal voltage info TPCE_PD



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August 2010

0DCH B5H X Mantissa Exponent X=1: extension byte present

0DEH 1EH X Extension Nominal voltage 3.3 V

0E0H 4DH X Mantissa Exponent Peak current 45 mA

0E2H 1BH CISTPL_CFTABLE_ENTRY Configuration tuple Tuple code

0E4H 12H CISTPL_LINK Link length is 18 bytes Link to next tuple

0E6H C3H I D Configuration IndexIndex=1: I/O mappedI=1: interface byte followsD=1: default entry

TPCE_INDX

0E8H 41H W R P B Interface Type

W=0: wait not requiredR=1: ready/busy activeP=0: WP not usedB=0: BVD1, BVD2 not usedType=1: I/O interface

TPCE_IF

0EAH 99H M MS IR IO T Power

M=1: misc info presentMS=0: no memory space infoIR=1: interrupt is usedIO=1: I/O space is usedT=0: no timing info specifiedPower=1: VCC info, no VPP

TPCE_FS

0ECH 27H R DI PI AI SI HV LV NV

DI=0: no power-down currentPI=1: peak current infoSI=0: no static current infoHV=1: max voltage infoLV=1: min voltage infoNV=1: nominal voltage info

TPCE_RD

0EEH 55H X Mantissa Exponent Nominal voltage 5.0 V

0F0H 4DH X Mantissa Exponent Nominal voltage 4.5 V

0F2H 5DH X Mantissa Exponent Nominal voltage 5.5 V

0F4H 75H X Mantissa Exponent Peak current 80 mA

0F6H EAH R S E IO

R=1: range followsS=1: support 16-bit hostsE=1: support 8-bit hostsIO=10: 10 lines decoded

TCE_10

0F8H 61H LS AS NRLS=1: 1 byte lengthAS=2: 2-byte addressNR=1: 2 address ranges

0FAH 70H Base Address 1 (LSB)

Address range 1 0x170 to 0x1770FCH 01H Base Address 1 (MSB)

0FEH 07H Address Range 1 Length



- 29 -





100H 76H Base Address 2 (LSB)

Address range 2 0x376 to 0x377102H 03H Base Address 2 (MSB)

104H 01H Address Range 2 Length

106H EEH S P L M IRQN

S=1: interrupt sharing logicP=1: pulse mode supportedL=1: level mode supportedM=0: masks VCC note presentIRQN=14: use interrupt 14

TPCE_IR

108H 21H X R P RO A T


TPCE_MI

10AH 1BH CISTPL_CFTABLE_ENTRY Configuration tuple Tuple code


10EH 06H I D Configuration Index I/O mapped, index =3 TPCE_INDX

110H 01H M MS IR IO T Power Power=1: VCC info, no VPP TPCE_FS

112H 21H R DI PI AI SI HV LV NV PI=1: peak current infoNV=1: nominal voltage info TPCE_PD

114H B5H X Mantissa Exponent X=1: extension byte present

116H 1EH X Extension Nominal Voltage 3.30 V

118H 4DH X Mantissa Exponent Peak current 45 mA

11AH 1BH CISTPL_CFTABLE_ENTRY Configuration tuple Tuple code


11EH 07H I D Configuration Index I/O mapped, index=7 TPCE_INDX

120H 00H M MS IR IO T Power No feature descriptions follow TPCE_FS

122H 28H Hyperstone-specific data

124H D3H Hyperstone-specific data

126H 14H CISTPL_NO_LINK No link control tuple Tuple code

128H 00H CISTPL_LINK Link length is 0 bytes Link to next tuple

12AH 15H CISTPL_VERS_1 Level 1 version/product info Tuple code

12CH 1EH CISTPL_LINK Link length is 30 bytes Link to next tuple

12EH 04H TPPLV1_MAJOR PCMCIA2.0/JEIDA4.1 Major version

130H 01H TPPLV1_MINOR PCMCIA2.0/JEIDA4.1 Minor version

132H... 53H... SMART Modular Tech. Info string 1



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August 2010

6.0 TIMING

6.1 Memory Mode

6.1.1 Attribute Memory

158H 00H Null terminator

15AH... 48H... HYB CF Info string 2

166H 00H Null terminator

168H FFH CISTPL_END End of CISTPL_VERS_1 End marker

16AH FFH CISTPL_END End of CIS Tuple code

Table 21: Attribute Memory Timing

Symbol Parameter Min Max Units

tcR Ready Cycle Time 250 nsecs

ta(A) Address Access Time 250 nsecs

ta(CE) Card Enable Access Time 250 nsecs

ta(OE) Output Enable Access Time 125 nsecs

tdis(CD) Output Disable Time from CE 100 nsecs

tdis(OE) Output Disable Time from OE 100 nsecs

ten(CE) Output Enable Time from CE 5 nsecs

ten(OE) Output Enable Time from OE 5 nsecs

ty(A) Data Valid Time from Address Change 0 nsecs

tsuA Address Setup Time 30 nsecs

th(A) Address Hold Time 20 nsecs

tsu(CE) Card Enable Setup Time 0 nsecs

th(CE) Card Enable Hold Time 20 nsecs

tcW Write Cycle Time 250 nsecs

tw(WE) Write Pulse Time 150 nsecs

tsu(A) Address Setup Time for WE 30 nsecs

tsu(CE) Card Enable Setup Time for WE 30 nsecs

tsu(D-WEH) Data Setup Time for WE 80 nsecs

th(D) Data Hold Time 30 nsecs

tdis(WE) Output DIsable Time from WE 100 nsecs



- 31 -





6.1.2 Common Memory

ten(WE) Output Enable Time from WE 5 nsecs

tsu(OE-WE) Output Enable Setup Time for WE 10 nsecs

th(OE-WE) Output Enable Hold Time for WE 10 nsecs

Table 22: Common Memory Timing


tcR Ready Cycle Time 80 nsecs

ta(A) Address Access Time 55 nsecs

ta(CE) Card Enable Access Time 55 nsecs

ta(OE) Output Enable Access Time 45 nsecs

tdis(CD) Output Disable Time from CE 45 nsecs

tdis(OE) Output Disable Time from OE 45 nsecs

ten(CE) Output Enable Time from CE 5 nsecs

ten(OE) Output Enable Time from OE 5 nsecs

ty(A) Data Valid Time from Address Change 0 nsecs

tsu(A) Address Setup Time 10 nsecs

th(A) Address Hold Time 10 nsecs

tsu(CE) Card Enable Setup Time 0 nsecs

th(CE) Card Enable Hold Time 10 nsecs

tcW Write Cycle Time 80 nsecs

tw(WE) Write Pulse Time 55 nsecs

tsu(A) Address Setup Time for WE 10 nsecs

tsu(CE) Card Enable Setup Time for WE 0 nsecs

tsu(D-WEH) Data Setup Time for WE 30 nsecs

th(D) Data Hold Time 10 nsecs

trec(WE) Write Recover Time 15 nsecs

tdis(WE) Output DIsable Time from WE 45 nsecs

ten(WE) Output Enable Time from WE 5 nsecs

tsu(OE-WE) Output Enable Setup Time for WE 10 nsecs

th(OE-WE) Output Enable Hold Time for WE 10 nsecs

Table 21: Attribute Memory Timing (Continued)


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August 2010

6.2 I/O Mode

Table 23: I/O Mode Timing


td(IORD) Data Delay after IORD 45 nsecs

th(IORD) Data Hold following IORD 5 nsecs

tw(IORD) IORD Pulse Width 55 nsecs

tsuA(IORD) Address Setup Time for IORD 15 nsecs

thA(IORD) Address Hold Time for IORD 10 nsecs

tsuCE(IORD) Card Enable Setup Time for IORD 5 nsecs

thCE(IORD) Card Enable HOld Time for IORD 10 nsecs

tsuREG(IORD) REG Setup Time for IORD 5 nsecs

thREG(IORD) REG Hold Time for IORD 0 nsecs

tdfINP(IORD) INPACK Delay Falling from IORD 0 45 nsecs

tdrINP(IORD) INPACK Delay Rising from IORD 45 nsecs

tdfIO16(IORD) IOIS16 Delay Falling from Address 35 nsecs

tdrIO16(IORD) IOIS16 Delay Rising from Address 35 nsecs

tsu(IOWR) Data Setup Time for IOWR 15 nsecs

th(IOWR) Data Hold Time for IOWR 5 nsecs

tw(IOWR) IOWR Pulse Width 55 nsecs

tsuA(IOWR) Address Setup TIme for IOWR 15 nsecs

thA(IOWR) Address Hold Time for IOWR 10 nsecs

tsuCE(IOWR) Card Enable Setup Time for IOWR 5 nsecs

thCE(IOWR) Card Enable Hold Time for IOWR 10 nsecs

tsuREG(IOWR) REG Setup Time for IOWR 5 nsecs

thREG(IOWR) REG Hold Time for IOWR 0 nsecs

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6.3 True IDE Mode (PIO)

6.4 True IDE Mode (MWDMA)

Table 24: True IDE Mode (PIO) Timing


t0 Cycle Time 80 nsecs

t1 Address Setup Time for IORD/IOWR 10 nsecs

t9 Address Hold Time for IORD/IOWR 10 nsecs

t2 IORD/IOWR Pulse Width 55 nsecs

t2i IORD/IOWR Recovery Time 20 nsecs

t5 Data Setup Time for IORD 10 nsecs

t6 Data Hold Following IORD 5 nsecs

t6z Output Disable Time from IORD 20 nsecs

t3 Data Setup Time for IOWR 15 nsecs

t4 Data Hold Time Following IOWR 5 nsecs

Table 25: True IDE Mode (MWDMA) Timing


tO Cycle Time 80 nsecs

tD IORD/IOWR Pulse Width 55 nsecs

tE IORD Data Access 45 nsecs

tF Data Hold Following IORD 5 nsecs

tG Data Setup Time for IORD/IOWR 10 nsecs

tH Data Hold Following IOWR 0 nsecs

tI DMACK Setup Time for IORD/IOWR 5 nsecs

tKR, tKW IORD/IOWR Recovery Time 20 nsecs

tLR, tLW IORD/IOWR to DMARQ Delay 35 nsecs

tM CS0, CS1 Setup for IORD/IOWR 5 nsecs

tN CS0, CS1 Hold Following IORD/IOWR 10 nsecs

tZ Output Disable Time from DMACK 25 nsecs

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August 2010

6.5 UDMA Timing

Table 26: UDMA Burst Timing

Symbol ParameterUDMA 0

(ns)UDMA 1

(ns)UDMA 2

(ns)UDMA 3

(ns)UDMA 4

(ns)

Min Max Min Max Min Max Min Max Min Max

t2CYCTYP Typical sustained average two cycle time 240 160 120 90 60

tCYCCycle time allowing for asymmetry and clock variations 112 73 54 39 25

t2CYCTwo cycle time allowing for clock varia-tions 230 153 115 86 57

tDS Data setup time at recipient 15.0 10.0 7.0 7.0 5.0

tDH Data hold time at recipient 5.0 5.0 5.0 5.0 5.0

tDVS Data valid hold time at sender 70.0 48.0 31.0 20.0 6.7

tCS CRC word setup time at device 15.0 10.0 7.0 7.0 7.0

tCH CRC word hold time at device 5.0 5.0 5.0 5.0 5.0

tCVS CRC word valid setup time at host 70.0 48.0 31.0 20.0 6.7

tCVH CRC word valid hold time at sender 6.2 6.2 6.2 6.2 6.2

tDZFS

Time from STROBE output released-to-driving until the first transition of critical timing

0 0 0 0 0

tFS Final STROBE time 230 200 170 130 120

tLI Limited interlock time 0 150 0 150 0 150 0 100 0 100

tMLI Interlock time with minimum 20 20 20 20 20

tULI Unlimited interlock time 0 0 0 0 0

tAZMaximum time allowed for output drivers to release 10 10 10 10 10

tZAH Minimum delay time required for output 20 20 20 20 20

tZAD Drivers to assert or negate 0 0 0 0 0

tENV Envelope time 20 70 20 70 20 70 20 55 20 55

tRFS Ready-to-final STROBE time 75 70 60 60 60

tRP Ready-to-pause time 160 125 100 100 100

tIORDYZ Maximum time before releasing IORDY 20 20 20 20 20

tZIORDY Minimum time before driving IORDY 0 0 0 0 0

tACK Setup and hold times for DMACK# 20 20 20 20 20

tSSTime from STROBE edge to negation of DMARQ or assertion of STOP 50 50 50 50 50

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7.0 PART NUMBERS

7.1 Part Numbering Information

7.2 Part Number Decoder

Table 27: Part Numbering Information

SMART Part Number Capacity

Unformatted Storage Capacity

(Bytes)

Sectors/Drive Cylinders Heads Sectors/

Track

SG9SCDS128HYB1x 128 MBytes 128,450,560 250,880 980 8 32

SG9SCDS256HYB2x 256 MBytes 256,901,120 501,760 980 16 32

SG9SCDS512HYB4x 512 MBytes 512,483,328 1,000,944 993 16 63

SG9SCDS1GHYB9x 1 GByte 1,024,966,656 2,001,888 1,986 16 63

SG9SCDS2GHYBAx 2 GBytes 2,048,901,120 4,001,760 3,970 16 63

SG9SCDS4GHYBBx 4 GBytes 4,097,802,240 8,003,520 7,940 16 63

SG 9 SCD XXX HYB

Device Density/Page Size

Capacity

Single Channel

Flash MemorySMART RoHS

XS

1 = 1 Gbit/2K

Optionblank = UDMA + MWDMA + PIO

256 = 256 MBytes128 = 128 MBytes

2 = 2 Gbit/2K

512 = 1512 MBytes1G = 1 GByte

Single-Chip Disk Drive

4 = 4 Gbit/2K

X X

D = PIO + MWDMA (No UDMA)P = PIO Only

Operating Temperatureblank = CommercialI = Industrial

9 = 8 Gbit/2KA = 16 Gbit/2KB = 32 Gbit/4K

ATA ControllerHYB = F3-LCT05

2G = 2 GBytes4G = 4 GBytes

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August 2010

7.3 Packaging Material

The SCDDs are packaged in a film-style carrier tape, with each SCDD occupying an individual slot. The tape isrolled onto a 13-inch diameter reel for shipping, and each reel can hold a maximum of 420 chips. See the follow-ing figure for the dimensions of the packing material.

Figure 4: Packaging Material and Dimensions

44.30 [1.74]

20.30[0.80] 1.85 [0.073]

28.10[1.10]

1.60[0.063]

21.40[0.84]

23.60[0.93]

2.10 [0.083]

4.10 [0.16]

4.75 [0.19]0.45 [0.018]

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7.4 Evaluation Boards

SMART Modular Technologies produces evaluation boards that essentially convert the SCDD to a CompactFlash(CF) card. These boards contain a CF housing and an exposed printed circuit board (PCB) to which the SCDD issoldered. Once connected, insert the board into any CF socket for evaluation purposes. See the following figurefor an illustration of an evaluation board, and Table 27 for a list of available part numbers.

Figure 5: Evaluation Board

Table 28: Evaluation Board Part Numbers

Evaluation Board Part Number SCDD Capacity

SGSCDS-128HYB 128 MBytes



SGSCDS-1GHYB 1 GByte

SGSCDS-2GHYB 2 GBytes

SGSCDS-4GHYB 4 GBytes

SCDD

CF Housing

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August 2010

Disclaimer:

No part of this document may be copied or reproduced in any form or by any means, or transferred to anythird party, without the prior written consent of an authorized representative of SMART Modular Technolo-gies, Inc. (“SMART”). The information in this document is subject to change without notice. SMARTassumes no responsibility for any errors or omissions that may appear in this document, and disclaimsresponsibility for any consequences resulting from the use of the information set forth herein. SMARTmakes no commitments to update or to keep current information contained in this document. The productslisted in this document are not suitable for use in applications such as, but not limited to, aircraft controlsystems, aerospace equipment, submarine cables, nuclear reactor control systems and life support sys-tems. Moreover, SMART does not recommend or approve the use of any of its products in life supportdevices or systems or in any application where failure could result in injury or death. If a customer wishesto use SMART products in applications not intended by SMART, said customer must contact an authorizedSMART representative to determine SMART's willingness to support a given application. The informationset forth in this document does not convey any license under the copyrights, patent rights, trademarks orother intellectual property rights claimed and owned by SMART. The information set forth in this documentis considered to be “Proprietary” and “Confidential” property owned by SMART.

ALL PRODUCTS SOLD BY SMART ARE COVERED BY THE PROVISIONS APPEARING IN SMART'STERMS AND CONDITIONS OF SALE ONLY, INCLUDING THE LIMITATIONS OF LIABILITY, WARRANTYAND INFRINGEMENT PROVISIONS. SMART MAKES NO WARRANTIES OF ANY KIND, EXPRESS,STATUTORY, IMPLIED OR OTHERWISE, REGARDING INFORMATION SET FORTH HEREIN ORREGARDING THE FREEDOM OF THE DESCRIBED PRODUCTS FROM INTELLECTUAL PROPERTYINFRINGEMENT, AND EXPRESSLY DISCLAIMS ANY SUCH WARRANTIES INCLUDING WITHOUTLIMITATION ANY EXPRESS, STATUTORY OR IMPLIED WARRANTIES OF MERCHANTABILITY ORFITNESS FOR A PARTICULAR PURPOSE.

©2010 SMART Modular Technologies, Inc. All rights reserved.

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Documents

SMART Modular Industrial-Grade Single-Chip Disk Drive (SCDD)c1170156.r56.cf3.rackcdn.com/UK_SMO_SG9SCDD2GHYB9_DS.pdf · ©2010 SMART Modular Technologies 2.0 PRODUCT DESCRIPTION The