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ISIS Sensorial Material Scientific Centre Wiener Str 12 28359 Bremen Germany University of Bremen Department 3 Workgroup Robotics Robert Hooke Str. 5 28359 Bremen Germany Stefan Bosse email [email protected] Tel. (49)421-178454103 www.isis.uni-bremen.de SMART ENERGY MANAGEMENT AND LOW-POWER DESIGN OF EMBEDDED SYSTEMS ON ALGORITHMIC LEVEL FOR SELF-POWERED SENSORIAL MATERI- ALS AND ROBOTICS A Contribution from Behavioural High-Level Synthesis and Advanced Ar- tificial Intelligence Algorithms Stefan Bosse (1,2) , Thomas Behrmann (2) , Frank Kirchner (1) University of Bremen, Department Computer Science, Workgroup Robotics, Germany (1) , ISIS Sensorial Materials Scientific Centre, Germany (2) ENERGY-AWARE DESIGN FLOW FOR EMBEDDED SYSTEMS + Today there is an increasing demand for miniaturized smart sensors embedded in sensorial materials. + With increasing miniaturization and sensor-actuator density, decentralized network and data-processing architectures are preferred, but energy supply is still centralized. Advanced smart low-power design methodologies and applications are required. + A new design methodology focuses on 1. smart energy man- agement at runtime and 2. application-specific System-On-Chip (SoC) design at design time contributing to low-power systems on both algorithmic and technological level. Figure 1. Composition and modelling of a feedback-controlled system with signal flow dia- grams. This example implements a PID controller used for example in actuator position control, consisting of sensor signal acquisition (ADC), filtering, and an error controller with a proportional, integral, and differential sub-controller [3]. ä Data processing systems are modelled using signal flow diagrams (see Figure 1.) [2]. ä This initial specification is used to derive 1. a multi-process program- ming model, and 2. a hardware model for a System-On-Chip design on Register-Transfer level. ä The signal flow diagram is first transformed into a S/T Petri Net repre- sentation (Figure 2.). The Petri Net is used 1. to derive the commu- nication architecture, and 2. to determine an initial configuration for the communication network. ä The Petri Net is mapped to sequential processes performing func- tional operations and channels providing the inter-process communi- cation. ä Finally, a RTL SoC design is synthesized [1] and the circuit activity is analyzed regarding different algorithms and complexity (Figure 4.). Figure 2. Mapping of the signal flow diagram to a Petri Net and mapping of Petri Net to com- munication channels and sequential processes using the ConPro programming language. ENERGY MANAGEMENT AT RUNTIME + Smart energy management is performed spatially at runtime by a behaviour-based or state-action-driven selection from a set of different (implemented) algorithms classified by their demand of computation power, and temporally by varying data-processing rates (based on previous activity analysis). Definition 1. Constraints net relations satisfying quality of service and minimizing power consumption to be fulfilled at runtime. Some values are derived from circuit activity analy- sis. VARS = {Runtime,Rate,Level,Energy,Power,Error} Runtime = {LOW=1,MED=2,HIGH=3}, Error = {0,5,10,100}, Lev- el = {LOW=1,HIGH=1.5} , Rate = {1,5,10,50,100} , ... Runtime > 0, Energy > 0, Rate > 0 Energy (Power*Runtime)/2 Power (Level*Rate)/4 Error (Level+Rate)/2 Figure 3. System simulation (from Figure 1.) with different runtime behaviours using a deci- sion tree which can be retrieved by machine learning methods. Parameters: Data-process- ing rate={1,5,10,20,100}, Algorithmic level={P:1,PID:2} ä Using advanced methods from the artificial intelligence area enables dynamic adaption of smart sensors and actuators at runtime. ä Definition 1 shows a constraints net approach performing energy managament at runtime. ä Figure 3. shows simulation results of a system using decision tree and machine learning approaches to optimize the runtime behaviour. Figure 4. SoC cell activity correlates strongly with computation and signal/data flow. The first five results are computed only with the P controller; after obtaining the fifth result val- ue U, the I and D computational blocks are switched on. REFERENCES [1] S. Bosse, Hardware Synthesis of Complex System-on-Chip-Designs for Embedded Systems Using a Behavioural Programming and Multi-Process Model, Proceedings of the 55th IWK - Internation- ales Wissenschaftliches Kolloquium, Session C4, Ilmenau, 13 - 17 Sept. 2010 [2] T. Behrmann, C. Zschippig, M. Lemmel, S. Bosse, Toolbox for Energy Analysis and Simulation of self-powered Sensor Nodes, Proceedings of the 55th IWK - Internationales Wissenschaftli- ches Kolloquium, Session A3, Ilmenau, 13 - 17 Sept. 2010 [3] R. Isermann, Digital Control Systems, Springer, 1989 ADC DAC PID K K I Z -1 Z -1 1 - Z -1 (1- ) K D S S' U -1 K Z -1 Z -1 Z -1 K I K D K D X A 1 Z -1 S A 2 E U F UD UI UK E E U S X F X E P I D channel c_x:int[12] with model=buffered; channel c_s:int[12] with model=buffered; channel c_e1,c_e2,c_e3:int[12] ... channel c_u1,c_u2,c_u3:int[12] ... process p_i: begin reg t1,t2,z1,z2: int[DATAWIDTH4]; always do begin t1 <- c_e2; t1 <- z1, z1 <- t1; t1 <- t1 * KI; t1 <- t1 asr 4; t2 <- t1 + z2, z2 <- t2; c_u2 <- t2; end; end; U Runtime Power Error Level Rate Energy <= <= * + >= >= * >= >= 500 1000 1500 2000 200 000 400 000 600 000 800 000 1. x 10 6 Energy [Arb. Units] Time [Arb. Units] Dynamic Run Using Decision Tree Parameter Optimization Static Parameter Run Rate=20, Level=1 Rate=10, Level=1 Rate=20, Level=2 Rate=100, Level=1 Quality Quality L=2 R=5 Error L=2 R=10 L=2 R=10 L=2 R=20 L=1 R=100 <=5 >=0.0003 <0.0003 >= 0.0003 <0.0003 >5 >30 0 200 400 600 800 1000 Clock Cycles 0 20 40 60 80 100 120 140 Cell Activity Clock Cycle Digcon1 Processing of a data set with simplified algorithm Processing of a data set with different algorithm +50% activity Universität Bremen Proceedings of the Smart Systems Integration Conference 2011, Session 4, Dresden, 22 - 23 Mar. 2011, ISBN 978-3-8007-3324-8

SMART ENERGY MANAGEMENT AND LOW-POWER DESIGN … fileagement at runtime and 2. application-specific System-On-Chip (SoC) design at design time contributing to low-power systems on

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ISISSensorial MaterialScientific Centre

Wiener Str 1228359 BremenGermany

University of BremenDepartment 3Workgroup Robotics

Robert Hooke Str. 528359 BremenGermany

Stefan Bosseemail [email protected]. (49)421-178454103 www.isis.uni-bremen.de

SMART ENERGY MANAGEMENT AND LOW-POWERDESIGN OF EMBEDDED SYSTEMS ON ALGORITHMICLEVEL FOR SELF-POWERED SENSORIAL MATERI-ALS AND ROBOTICSA Contribution from Behavioural High-Level Synthesis and Advanced Ar-tificial Intelligence Algorithms

Stefan Bosse(1,2), Thomas Behrmann(2), Frank Kirchner(1)

University of Bremen, Department Computer Science, Workgroup Robotics, Germany(1), ISIS Sensorial Materials Scientific Centre, Germany(2)

ENERGY-AWARE DESIGN FLOW FOR EMBEDDED SYSTEMS

+ Today there is an increasing demand for miniaturized smartsensors embedded in sensorial materials.

+ With increasing miniaturization and sensor-actuator density,decentralized network and data-processing architectures arepreferred, but energy supply is still centralized. Advanced smartlow-power design methodologies and applications are required.

+ A new design methodology focuses on 1. smart energy man-agement at runtime and 2. application-specific System-On-Chip(SoC) design at design time contributing to low-power systemson both algorithmic and technological level.

Figure 1. Composition and modelling of a feedback-controlled system with signal flow dia-grams. This example implements a PID controller used for example in actuator positioncontrol, consisting of sensor signal acquisition (ADC), filtering, and an error controller witha proportional, integral, and differential sub-controller [3].

ä Data processing systems are modelled using signal flow diagrams(see Figure 1.) [2].

ä This initial specification is used to derive 1. a multi-process program-ming model, and 2. a hardware model for a System-On-Chip designon Register-Transfer level.

ä The signal flow diagram is first transformed into a S/T Petri Net repre-sentation (Figure 2.). The Petri Net is used 1. to derive the commu-nication architecture, and 2. to determine an initial configuration forthe communication network.

ä The Petri Net is mapped to sequential processes performing func-tional operations and channels providing the inter-process communi-cation.

ä Finally, a RTL SoC design is synthesized [1] and the circuit activity isanalyzed regarding different algorithms and complexity (Figure 4.).

Figure 2. Mapping of the signal flow diagram to a Petri Net and mapping of Petri Net to com-munication channels and sequential processes using the ConPro programming language.

ENERGY MANAGEMENT AT RUNTIME

+ Smart energy management is performed spatially at runtime bya behaviour-based or state-action-driven selection from a set ofdifferent (implemented) algorithms classified by their demand ofcomputation power, and temporally by varying data-processingrates (based on previous activity analysis).

Definition 1. Constraints net relations satisfying quality of service and minimizing powerconsumption to be fulfilled at runtime. Some values are derived from circuit activity analy-sis.

VARS = {Runtime,Rate,Level,Energy,Power,Error}Runtime = {LOW=1,MED=2,HIGH=3}, Error = {0,5,10,100}, Lev-el = {LOW=1,HIGH=1.5} , Rate = {1,5,10,50,100} , ...Runtime > 0, Energy > 0, Rate > 0Energy ≥ (Power*Runtime)/2Power ≥ (Level*Rate)/4Error ≤ (Level+Rate)/2

Figure 3. System simulation (from Figure 1.) with different runtime behaviours using a deci-sion tree which can be retrieved by machine learning methods. Parameters: Data-process-ing rate={1,5,10,20,100}, Algorithmic level={P:1,PID:2}

ä Using advanced methods from the artificial intelligence areaenables dynamic adaption of smart sensors and actuators at runtime.

ä Definition 1 shows a constraints net approach performing energymanagament at runtime.

ä Figure 3. shows simulation results of a system using decision treeand machine learning approaches to optimize the runtime behaviour.

Figure 4. SoC cell activity correlates strongly with computation and signal/data flow. Thefirst five results are computed only with the P controller; after obtaining the fifth result val-ue U, the I and D computational blocks are switched on.

REFERENCES[1] S. Bosse, Hardware Synthesis of Complex System-on-Chip-Designs for Embedded Systems Using a

Behavioural Programming and Multi-Process Model, Proceedings of the 55th IWK - Internation-ales Wissenschaftliches Kolloquium, Session C4, Ilmenau, 13 - 17 Sept. 2010

[2] T. Behrmann, C. Zschippig, M. Lemmel, S. Bosse, Toolbox for Energy Analysis and Simulationof self-powered Sensor Nodes, Proceedings of the 55th IWK - Internationales Wissenschaftli-ches Kolloquium, Session A3, Ilmenau, 13 - 17 Sept. 2010

[3] R. Isermann, Digital Control Systems, Springer, 1989

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process p_i:begin reg t1,t2,z1,z2: int[DATAWIDTH4]; always do begin t1 <- c_e2; t1 <- z1, z1 <- t1; t1 <- t1 * KI; t1 <- t1 asr 4; t2 <- t1 + z2, z2 <- t2; c_u2 <- t2; end; end;

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Universität Bremen

Proceedings of the Smart Systems Integration Conference 2011, Session 4, Dresden, 22 - 23 Mar. 2011, ISBN 978-3-8007-3324-8