Low Power Vlsi Design Qns

8/13/2019 Low Power Vlsi Design Qns

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Reg.No.:

Question Paper Code :

Time : Three hours

esti$atotsr.'". ,,Larggimprovements in power dissipation are possible only at higher levelsofd""inf straction.Why?

-Whatt'r61't the objectives of power minimization techniques related. torneg.rory that can be achieved using software?

'=e.,#(Regulation 009) "1r",r,,t:4.- Maximum : 1oo marksjr '*+.**Answer Al,ft'.luestfri4q,' tt *" tr ..PARTA - $0,a


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(b) (il

PARf B - (5 " 16 ='80 marks)

OrDiscuss the dynamic logic and staticrespect to power dissipation. k#-"ts with(6)

13.

(ir) Explain h a94t about operation reduction and operationsubstitution with examples.u*" (E+ S)il *"""u'(a) Explain any two techniquesfrviB, "trtq"-pre for reducing powerconsumption in memories. '$#"t. o -ot, 'S*tf*"u''. "%*f(b) Draw the resonantari$erffiq ifu g"r"r.ting supplycrockandcompare it with other nqetHo$;*[ls$ sive the imporLnce of clockgeneration with reSppt topowei disfpation

f l ' " t ' " , - ' t ' ' t - o"(a) (il Draw tfie fl"F"t q[] :f MEhte-Cartobasedestimationof glitchingpower or secigent$"it"F and expLain.S ,"i (8)(ir) write a note d'iqpow-g;fbsumation ased.o"i"iilror*"tion theoryapproach.\*^ . , , , , ' lAtt UL-*- Or

L4.

15.

(b) Explairr'..lhe method of estirnating average power in combinationalan$se3rr"Cn#atcircuits using sta.tisticaltechniques., .S ", . ""l:,Efllr"'' i.... pe.":(a) .D,iseuqp-ifaetairi trre.various revels of abstraction at which power.i

tt":'Fte-*ot"*"" estimatedJsoftware'*", "(b) ',Larsif r*p.1o1r"*.rrts in power dissipation are possibreat higher levels", on'{gqign"'abstraction. JustiS the above statement and discuss the". o-t'dgqlgn"'bbstraction.ustiS the-abovestatlment and discuss the, '' teoftniques sed. \ I r.^lii,li "::1 i.L lt

i."1111,i'

77907


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Reg. No. :

QuestionPaper Code 98081M.E. DEGREEEXAMINATION,NOVEMBERID

ElectiueVLSI Design

YL9252 - LOW POWERVLSI DESIGN(Commono M.E. AppliedElectronics)

(RegulationTime : Three hours 100 Marks

Answer ALLPARTA

Definesubthresholdswing.2. What is body effect?3.4.o.

What is meant by tra

Draw a 6 transistor SRAM ceILDefine intrinsic delav.

6. Com R type row decoderand NAND type row decoder n memories.computing?

nction A* + BX + C using two multipliers and two ad.ders.

1.

7.

9.

Imn"lemenittu.De

'-' ,, "-%," *rffliO***Wdffi?f*o an algorithm to compute signal probabilities._%,u


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PARTB-(5x 16=80Marks)11. (a) ( t - ' Derive an expression or short circuit power dissipationinverter. ff i(ii) write a short note on drain induced barrier roweri

Or(i) "'rFxplain basic principles of low power design.(iip Discuss the various sources of power ddevices. (8)

(8)12. (a) (, Discuss the various features of technologyJpower(8)Or(b) (il Explain the conceptof state assignment for finite state machine toreducepower dissipation wi 5ample. (10)(ii) Factoring out a common n can achieve power saving.Justi$r. (6)

circuits and sense(10)(6)

13. (a) (t How can power be redamplifier circuits?

rchniques o, Jdissipation.

(b)

(ii)

(b) (il(ii)

14. (a) (t,. ".fl.* L"l f,;'o ' (ii)

0 t l\_, , ,

Differentiate MT

Explain theDesign aHow dodiagrams?Discuss mcircuits.

the-principle of pre-computation logic for reducing powerdtable example. /o\

ff levetconverter. .t'ttt.: (10)logic. *-*. jTu'* i * : (6)probability using binary decision(s)average power in combinational(8)

(8)

??*er15. (a )

tingOr

Explain in detail about Monte carlo method for estimating glitch power.

l 1..*tl Orthe

b-i&ws"

st t*t}': i,+

@mpuW*-,awds 5f

(b) E*fr tion.


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,,:.

evel


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33Reg.No.:

Q 0205D.A{.Tech. EGRESSXAh{INATION,NtryJULY2009

THIRDSEMESTFRVLSIDESIGN

VL5OO2LOWPOWERW.,SIDESIGN(Commono AppliedSiectronics)

Tlrroehor:re(REGUI"ATION 007)

AnswerALL questions:PARTA -..,-10x 2 = h}marks)Frequency nfluencps tbe Power

Maximum100narks

Dissipationw the $witching in a logic

Whatare bgsources f FowerDissipation"?lltirat is a G.ateDela;'podel.?Whqt s Bus nvert Encoding?What s O-MOS loatingNode? iI)raw the Adiabatic ogic nverter for for:r phaseoperation..What s GlitchingPower?Write the eguation or CapacitivePowerDissipationof a bircuit.


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f, .: PART s (Ex tr6= g0marks)l1' .(a) State aud explain the basic principles and figure-of-meritsoj'LowDesign.

'(b) I)erive an expressionfor the dyeanric Power Dissipatinn in aInverter. --F,Ot

72. 'Discussin detail various imits of l-,owpowerDesign..i13. ' Explsin i.r:. etail aboutp^.ecornpuLationlogr. optimization:

Crt1,,'Explain the variou.e ircrujt"ecl.rnliies- or reclucingp^orv*rConsumpMuitipliers. A* r IPL, DpL DevJ(,SDJr-rRDl-r"edpu

Wwer in V/riter Driver circuits andi l ,

lo.

tT.

Explain tbe methodsof reduci.gAmplifier eircuits"

1*) RfP how a Sigual hohsbility ie calculated singBio"ry DeDiagram.(b) Exptain n dei;ulhow :lr', :o$#;ri T:i) verstimatio:lffiqY.*"r*.$":s"s$35Bo-slt

L8.1rr.

Ptga,ttr[*lffi***"W*r?$/\E-TIEAGu*t u.,r"tos ooo*.":$*;;':5Iogc Simrrlation anM.iftr)f,rchitldture L,evel' nalysie.Or

Software )enignCptimizationmethods.. Ifo0**"'oY

(a) Discussn detail the Poweroptinization usingoperation Reductio'oprrn.til:: . ubgti.tu.;:.i.,)::;.(b) . what is meantby TechnororyMapping?Exprainwith an exampre.

s{t?->t t .20. Iixllain in detgil

9$thn

a gJ,wd, wc* Atchr:fadh^'tal


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' .. "',, / our.xo.,'

N 0036M'E'&r'Tech')l:"GREIIEXAMINATI'NN''TEMBER,,E'EMBER2008.

THIRDSEME:STERAPPI,IEDELECTRONICS

]./I,'OA}I,OWPOWER SI DESIGN(CommontoVLSIcl.esign,l

(REGUI,ATION2OO7)15me Threehours Maximum 100noarks

AnswerALL questions.' I'}ARTA - (10 { =.e.{'trarks) tru,,J**'nho\ .ai od*,1.' Listheiveevers"ofiglarchvffjpit, g-lqrpDissipation.,^

t#;s:lij*:* qtou'srdso).o'-sl/t


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\r ' t ' rd: 11*,'."'Explainrrdetail hePhysics fPowerDissipationn Submicron OSfnf.

OrL2. [a]' Derivean expressionor the shortcircuitpowerdissipationn a CM

Inverter.G) Derive he expressionor powerdissipatedn a \ILSI circuitd-u: parasitic apacitor. WSt.i 13. ,.Explainn detail heCircuitLevelLowpow -"6' -l

r;;::;;:ffb) iixplain 'iheDeiayBalance,j-.l'{ultiplier ell and ts impacton the pgconsumption f a parallelsrray multiplierExplain he techniques f reducing owerconsumption.Or\Discussn detail hesourcesfsoftware owerDissipatioo.[ss.AExplainn detailCod+signorLowpower. (

. 1K n Mernories.t)16'9 (a) V/hat s Adiabaticcgtcnverter?Drawandexplaints operation.(b). How rloes he Cor.nplernenfarycliahstieCon:,putaticn if,br frr--:n

static cMos Gate rrpowerDissipation?xplain n detail.,n. ^ Explain n detail.the ogicpowerEBtimation echnioues.r Soqrcg f ;n*u? dlsxtption, prob"trrn 'lnk-rng,td.nqru,r-nd, . tgu\ Cs4zm?ottl t"twtah'rl, Spa*rOtc.*91-$F0h,gpd#io "lo*pr"",fCsryroJtirn;"*Utgl bi Tith the flowchartexplain ;heMonteCarlobased ecLiriqueo estim"/' the average ower.n sequeutial ircuits

J) Explain n detail about he powerEstimatior.rsingEntropy.19 Frplain in^dct'ail' lic i.cila','icr.=.ievel Traiisfcunsfo. irnpr',rvirrg o'Dissipation.l,H\ ) fb"a" &fteyar.n,ndondenolt(a,a* j #roiar, t /nnga.l+wdtfv\-wa.e Sor,&"1.cerr>siu ^ ,t f{"auOr20. (a)

' (b)


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Reg.No.:

fime: Three hoursAnswerALL

PARTA

2.3.

1.

4.

D.

What is punch through?

What is meantby ReveWhat is multilevelWhat are thealgorithm?How is

marks)

nnel effect?

of performance driven circuit optimization

reduced by using clock gating?t'" /*i I6. What are"ttib sHlidnt eaturesof adiabatic ogic circuit?

-\***ts'

7.

M.E./lVLTech.EGREEXAMINATION,lJfiffi\e"fu1i t*F 1Common o M.E. Applied Electronics M.E. fhsl #.d""'"..^*./

Electiue


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11. (a) (r)PARTB-(bx16=80marks)

Derive the expression for subthreshold currentMOSFET.Explain the MIS structure and derive theof depletionregion. forii) #--h"or f# -.1\ i"Jl(b) . ' (0 Deduce the expression for short circuit noiunloaded nverter.

(ii) Explain the circuit limits of low12. (a) Explain the power dissipationalgorithm. Apply the samefollowing function F = {fr, fr}

f i=ad+bcd and z=a+bc+

(i)"-"'"Explain circuitexample.(ii)'- Write short

13. (a) (t Explain

gn.

(b)

logic optimizationthe power for the

for CMOS gate with an(10)(6)

method in sense amplifier circuits oforganization of SRAM.

Or

(10)(6)

reduced swing clock technique for power reduction in(8)

SRAM.(ii) D

(b) (')

(ii) the power reduction effrciency of Adiabatic logic. (8)L4. (? _ A)"*"ryphin the transition Density signal model and propagation oft-'" ""a jfiansition density. - (f 0)

d--"=J-/ calculate the transition density and static probability of y = ab+ c ,\"- i j i f P(o)=o.2,P(b)=0.3,P(c)=0.a, D(a)=r, D(b)=2 and D(")=3.(6)'o*hu"*'riT "*l,#"Y\= #J'"--*-"

I "\"4 fc/\Unel(8)

depth(8)

of an(8)(8)

rhiltkl. \lY ,t'"1

Or

31143


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lSrb) (il Explain Monte Carlopowersimulation.(ii) Write short notes on Gate-levelpoweranalysis. (8)

15. (a) Write short noteson:(1) Power optimization using operation reductj{\*\o/ (8)(ii) Architecture rivenvoltage caling. \ #l (8)w

or/\ th,(b) (r) Explain the first-order differedps--."ptff#h- for low power\ fdissipation. l**-\- {f (8)rssrpaf,ron d*\ {"f (n,f f l \ \(ii) Write short notes on conskahed} l$ast square technique for

nonadaptive rlters. f"*t3'*/ (8)

'j

i''{*o..1*t t."".i i.,/..'''"L....:\-/> =;f \ / i". l*l iaq"i i*,. I

. r'

d' \ui =-*./*}L-ot,\ ,,t" '" Lrf l ' \- , \o"- ti i' ".,"\""n'-b-*t'""

t31148


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Reg. No. :

u 0046M.E /M.Tech:DEGREEEXAMINATION, NOVEMBER/DEOEMBERz010

. THIRD SEMESTERAPPLIEDELECTRONICS

VL5OO2OWPOWERVLSI DESIGN

(REGULATION2007)fime : Threehours Maximum : 100marks

AnswerALL questions..a

1.' What is short channel effeet?2' Give the expression for the energy transferred out of the power-supply duringa low-to-high transition, at the gate output.3' What are the four componentg of performance driven circuit optimizationalgorithms?4. What is transistor reordering?5. What is clock gating? "6. Draw the Boolgan decision diagram for the logic expression y =ffi. :7. List the three steps invorved in Monte carro power simulation.8. Defi.neTtansition Density.9. what is the use of DCM technique in the realization of FIR frrters?10. List the four practices that minimize ^"*o"y bandwidth reguirements.

g D & o t 5 7 t o t ,q


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OrL2. (a) Derive an expression for the power dissipation due to the charging and

-t'o'11.,"5tplain the physicsof powerfieeipation in(a) Iong channelMOSFET.(b) SubmicronMOSFET.

discharging of a capacitance in a CMOS Inverter.(b},t"'Di""use the basic principles of Inw Power d,esign.

(8)(8)

(8)(8)

techniques for , reducing power

13. (a) , What is Factoring?What is its effect n powersaving?Explain. (10)(b) Write a note onTechnologyMapping. (g)

Orl14;"'e"l)i"" ss in 'detail' about the rcircuit level

circuits(8)(8)

#. eonsumption.

15.)(a) Explain the concept of red.ucingemployed for SRAM circuits.

Or

power in sense amplifi.er(b) How low core voltiges are achibved from a single supply?

16. Explain in d.etail about:, (a) Low SwingBus.

O) Charge Recycling Bus.17. (a) Defrneetaticprobability.Brplain the propagationrof tatic probability inlogic'circuits. (8)

(b) Compute he transition density and static probabilityof y = ab +c givenP(o)= o.z, P(b)= 0.3 P(c)= s.4D(a)=l, D(b)= , D(e)=s '

':

ff'here P(a) P(b) PG) are the inpur sraric rprobabitities andO(") A(a) A(c) are the transition densityof the inputs). (g)

one additional degree of freedomitul-t "m*J

, (8)

Or18. Prove that Lag-one signal Model providesover the memoryless'signal model.


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19. Explain the first.order differencegalgorithm and second-order differencesalgorithm for improvement n powerdissipation argeted or digital filters. (1.6)

20. Explain in detail about,(a) Software Power Estimation.,(b) ,SoftwarePower Optimization.. : ,

3


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Reg.No.:

Question Paper Code 9L852M.E. DEGREE EXAMINATION, JANUARY 2012,

Elective\T,SI Design

YL 9252 LOW POWERVLSI DESIGN(Regulation2009)

Time : Three hours Maximum : 100 marksAnswer ALL questions.

PARTA-(10 x2=20 marks)1. Why is power dissipation consideredas the most critical factor in developmentof microelectronics echnology?2. What is DIBL?3. Minimum area is not always associated with minimum power dissipation for

CMOScircuits.Justifv this statement.4. Name two techniques or reduction of power in multipliers.5. Define Gate reorsanization.6. What is clockgating?7 List the steps nvolved to estimate maximum and minimum averagepower of icircuit.8. What are glitches?How does t affectpower requirement?9. Name the various levels of design abstraction where power dissipation can bereduced.10. Comparegate evel and architecture level power estimation.


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PARTB-(5x16=80marks)11. (a) Elaborate on the various factors that contribute to power dissipation inCMOS circuits.

Or(b) Discuss the different limits that are to be applied at various levels fordesign of low power VLSI circuits.

L2. (a) Explain the optimization techniques for reduced power consumption inmuitiplier circuits.Or

(b) Explain the muitilevel, logic optimization procedure or low power.13. (a) Describe in detail the various techniques used for reducing powerconsumption n memories.

Or(b) With circuit schematic compare the circuit performance and powerdissipation of ratioed logic, DCVS logic, pass transistor logic, Dominologic and DCSL logic.

14. (a) Discuss the Monte Carlo based method for power estimation ofcombinational and sequential ogic circuits.Or

(b) Explain the simuiation based approach for determining maximumdynamic power in static CMOS.15. (a) With an example, enumerate power optimization using operationreduction, operationsubstitution and precomputation.

Or(b) (i) What are the various sourcesof power dissipation in a CPU thatcan be influencedby sofbware? xplain. (8)

(ii) Discuss how the memory access costs can be minimized usingsoftware techniqueswith example. (8)

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Low Power Vlsi Design Qns