Small Signal Amplifiers - Lesson 9 - JFET Amplifier Biasing

7/31/2019 Small Signal Amplifiers - Lesson 9 - JFET Amplifier Biasing

1/20

2012 Mladen HruskaThis work is licensed under a CreativeCommons Attribution-ShareAlike 2.5 Canada License.

Background image courtesy of[anankkml]/FreeDigitalPhotos.net

Analog Electronic Circuits

Lesson 9 JFET Amplifier


2/20



Outline

JFET Amplifier Biasing Conditions

Self Biased JFET

JFET Load Line

Amplifier Biasing


3/20

2012 Mladen HruskaThis work is licensed under a Creative

Commons Attribution-ShareAlike 2.5 Canada License.Background image courtesy of[anankkml]/FreeDigitalPhotos.net

JFET Biasing Conditions

VGS

is Reverse Biased!

JFET used in Saturation for amplifier

Therefore VDS > VP

Commonly IDS

set to approximately 0.5IDSS

When VGS

= VP

/3.4 then IDS

= 0.5IDSS


4/20



JFET Fixed Bias


5/20



JFET Fixed Bias

RG

sets input impedance - rgs

very high

Separate negative supply on Gate

Impractical in most cases

Used at times

Common at low VDD

supply voltages

Self Biased config provides -ve VGS


6/20



Self Biased Configuration

Add resistor between Source and Ground

VDD

must be higher than Fixed Bias

ID through RS elevates VS above GroundV

Gheld at Gnd through R

G

Sets up a -ive VGS

Thus VGS

= - ID

x RS


7/20



Self Biased Configuration


8/20



JFET Load Line Self Bias

Provides a graphical method to visualizebiasing characteristics and Q point

Transfer curve at saturation is quadratic

JFET operation predictable given VGS(OFF)

and IDSS

(datasheet)

Drawing Load-Line identifies Q point


9/20




ID

VGS

ID= I

DSS(1

VGS

VP

)2

VGS(OFF)

VGS(OFF)

2

IDSS

IDSS

2

IDSS

4

VGS(OFF)

3.4


10/20




ID

VGS

IDSS

VGS

= IDR

D

ID

Q point IDQ

VGSQ


11/20



Load Line Changing RS

ID

VGS

IDSS

VGS

= IDR

D2

ID

IDQ

VGSQ


12/20



Load Line Changing RS

ID

VGS

IDSS

VGS

= IDR

D3

ID

IDQ

VGSQ


13/20



Amplifier Biasing

Quadratic curve tricky biasing, take yourtime with the math...

Useful shortcuts:

Solving: use substitution and quadratic formula

Designing: IDS

= 0.5IDSS

when VGS

= VP

/3.4

Amplifier in saturation Ensure VDS

> VP

Remember RS

sets Q point for Self Bias!


14/20

Amplifier Biasing

ID = IDSS(1 VGS

VP)2

VGS = VP(1 ID

IDSS)

VGS = IDR S

substitute ID = IDSS(1 IDRS

VP)2


15/20

Amplifier Biasing

ID = IDSS(1 VGS

VP)2

VGS = IDR S

ID =bb24ac

2awhere 0 = aID

2 + bID + c

substitute ID = IDSS(1 IDRS

VP)2


16/20

Amplifier Biasing

ID = IDSS(1 VGS

VP)2

VGS = IDR S

substitute ID = IDSS(1 ID RSVP)

2

= IDSS(1 IDR SVP)(1 ID RSVP

)

therefore ID = IDSS 2 IDSS RS

VP

ID + IDSS(RS

VP

)2

ID2

and 0 = IDSS(RS

VP)2

ID2 (

2 IDSS RS

VP1)ID + IDSS


17/20

Amplifier Biasing

ID = IDSS(1 VGS

VP)2

VGS = IDR S

substitute ID = IDSS(1 ID RSVP )

2

= IDSS(1 IDR SVP )(1 ID RSVP )

therefore ID = IDSS 2 IDSS RS

VP

ID + IDSS(RS

VP

)2

ID2

and 0 = IDSS(RS

VP)2

ID2 (

2 IDSS RS

VP1)ID + IDSS

a b c


18/20

Amplifier Biasing

ID = IDSS(1 VGS

VP)2

VGS = VP(1 ID

IDSS)

VGS = IDR S

KVL : 0 = VDDIDRDVDSIDRS

therefore : VDS = VDDID(RD+RS)saturation... ensure that VDS > VP


19/20



Credits and Attributions

Reference Texts:

Boylestad, R.L., Nashelsky, L., (2009). Electronic Devicesand Circuit Theory (10th ed.)

Floyd, T.L., (2012). Electronic Devices: conventional currentversion (9th ed.)

Images:

All images as individually attributed courtesy of

FreeDigitalPhotos.net user(s); anankkml listed in order ofaperance.


20/20



Copyright (c) 2012 by Mladen Hruska. This work is made availableunder the terms of the Creative Commons Attribution-ShareAlike 2.5Canada license

All images, diagrams, charts, etc. are the copyright work of MladenHruska if not immediately attributed otherwise

For more information:

http://creativecommons.org/licenses/by-sa/2.5/ca/
http://creativecommons.org/licenses/by-sa/2.5/ca/http://creativecommons.org/licenses/by-sa/2.5/ca/

Documents

Small Signal Amplifiers - Lesson 9 - JFET Amplifier Biasing