IEEE TRANSACTIONS ON COMMUNICATIONS, VOL. 43, NO. 2/3/4, FEBRUARY/MARCH/APRIL 1995 743

Simplified Designs for AAPP Soft Decision Threshold Decoders

Franqois Gagnon, Member, IEEE, NaTm Batani, Member, IEEE, and Tam Q. Dam, Member, IEEE,

Abstrac t - New designs for soft-decision threshold decoders are developed to significantly reduce the complexity and increase the coding gain as compared to previously proposed architectures. The Approximate A Posteriori Probability (AAPP) decoder considered here is a digital approximation of the A Posteriori Probability (APP) decoder introduced by Massey. These designs are useful for high-rate self- orthogonal convolutional codes with a long constraint length. The study case considered in this paper is for a rate 23/24, constraint length 4056 code used in a typical microwave digital radio. The new decoder architecture provides a four-fold decrease in complexity and an additional 0.3 dB coding gain as compared to previous designs.

I. INTRODUCTION

Soft decision threshold decoders permit an additional coding gain of up to 2 dB as compared to their hard decision counterpart [ I , p. 4831. This improvement is possible at the cost of a significant increase in complexity of the decoder architecture. In this paper, we propose architectures which significantly reduce this complexity.

For example a rate R=23/24 , memory m=168, constraint length n,=4056, convolutional self orthogonal code (CSOC) with hard decision decoding is currently used by Harris Farinon Canada. The decoder operates at over 50 Mbits/s and uses about 4 thousand gates and 4 K bits of RAM. Two-bit and three-bit soft decision decoder architectures for this code were developed wluch use 26 thousand and 61 thousand gates and provide gains of 0.9 and 1.2 dB respectively over hard decision decoding. It is thus possible to simply replace the existing decoder, without changing the code and thereby obtain meaningful performance improvements.

In this paper, we propose three techniques developed to simplify the design of CSOC decoders for any high rate code. They are particularly interesting for complex, high rate and fast decoders. Much of the previous work on the subject has been published by Massey [2], Wu [3, 41, Tanaka et al. [ 5 ] , Yu et al. [6] and more recently two papers by Lavoie et al. [7, 81 have

explored specific VLSI architectures for fast soft decision decoders. Whereas in [8] a shortening of the code was proposed to implement soft decision decoding, we now present architectures with the same code and a moderate complexity increase to replace existing hard decision decoders.

11. HARD AND SOFT DECISION DECODERS

The use of convolutional codes to improve the reliability of communication links is a relatively mature technology. Many good texts on the subject are available ([9] for example). In thls paper, the notation introduced by Massey [2] is used.

For hard decision decoding, the type I decoder is presented on Figure 1 and the type I1 decoder on Figure 2. The type I decoder uses extensive pipelining, whereas the type I1 decoder memorizes the necessary received information and past decisions. The type I decoder simply corrects the syndromes as they were computed by the encoder (or reencoder) combined with the received parity. With the type I1 decoder, the received information is replaced with the decoded information bits. The type I decoder complexity advantage also grows as the rate and constraint length increase. Furthermore both decoders use past decisions to correct the received information.

For soft decision decoding, the optimal APP decoder introduced by Massey [2] and improved by Wu [3], requires the use of complex operations which are not easily implemented with digital VLSI technology. Sub-optimal decoders which use simple binary operations were thus developed to reduce the implementation complexity. Hence, the term AAPP for Approximate A Posteriori Probability decoders was coined in [8] for the realization of simple soft decision decoders with the add-min operator described below. It is to be noted that this simplification involves a moderate coding gain degradation of about 0.6 dB as compared to the optimal APP decoder [8] for rates 1/2 and 3/4 CSOC.

AAPP soft decision decoding is performed with the type I1 decoder by replacing each single bit operation by q bit operations. The received coded symbols are quantized with Q=2q levels for q bits quantization. With a signed magnitude

Paper approved by C.-p, Jeremy Tzeng, the Editor for VLSI in representation, the most significant bit represents the Communications of the IEEE Communication Society. Manuscript received January 3, 1993; revised January 5, 1994. This research was supported in part by Harris Farinon Canada.

F, Gagnon and N. Batani are with the Department of Electrical Engineering, h o l e de technologie suptrieure, 4750, Henri-Julien, MontrBal, Qutbec, Canada,. H2T 2C8.

T. Q. Dam is with Harris Farinon Canada, 3, H6tel-de-Ville. Dollard-des- Ormeaux, QuBbec, Canada, H9B 3G4

IEEE Log Number 9410865

information or parity bit as it would have been demodulated with hard quantization. The (4-1) other bits represent the reliability of this most significant bit. To obtain a soft decision decoder, we may simply replace all the 1-bit delays in the hard decision decoder by q parallel 1-bit delays and all the modulo 2 additions by add-min operators. This add-min operator consists

0090-6778/95$4.00 0 1995 IEEE

144 IEEE TRANSACTIONS ON COMMUNICATIONS, VOL. 43, NO. 2/3/4, FEBRUARY/MARCH/APRIL 1995

il -b- ( 1 - R) na

stage encoder

12'

13.

. i2* . Memory 12' TB.0

i3* . (na bits) i3* TC.0

P' -

Syndrome I register I

I I 1

I

Figure 1 Hard Decision Type 1 Decoder

BB.2 00.3 00.4 BA.2 BA.3 BA.4 BC.2 BC.3 BC.4

P PA I LEGEND TA I. 1 B I. 1 C I (IS In Figure I P I I SBC I PII~IIDI i.wI1 lmm the 11' r.glslu I B ) golng lo 0.1 7 C I

P c I Port la1 r..ult lrom Ih. P' r.pld.r golnl lo Q a1 1C I P A l P B 4 P I S P A 3 P C 4 PCJ P I ? P C l P A 1 P C I

l'ipure 2 Hard Decision Type 2 and AAPP Soft Decision Decoder

IEEE TRANSACTIONS ON COMMUNICATIONS, VOL. 43, NO. 2/3/4, FEBRUARY/MARCH/APRIL 1995

TABLE 1 COMPLEXITY OF THE HOLD-UP AAPP DECODER

ARC"

Cell count

Transistor/ cell

Gate countkell

R=3/4 SPADE

Cell count

Transistor count

Gate count

R=23/24

Cell count

Transistor count

Gate count

Binary delay

mb

8

- -

10

-

57

456

570 =

3864

30912

38640 -

BASIC CELLS

:$t I8-ary I2-input delay add-min

72 I76 I72

Total

4440

4434

!50611

!47664

in a modulo 2 addition for the most significant bits and a minimum operation for the (q-1) remaining reliability bits. Furthermore, the thresholds or majority computations are replaced by signed magnitude additions of the parity check results.

The complexity of the AAPP decoder has been thoroughly examined in [8]. The least complex architecture uses a hold-up technique, it has the same complexity as the architecture on Figure 2. For a rate R=b/b+l , memory m, convolutional code with J parity check equations the complexity of such an architecture with 3-bit quantization is presented in Table 1. Because of its large complexity, the implementation of the rate 23/24 AAPP decoder is noteworthy. Transistor count is used for full custom Application Specific Integrated Circuit (ASIC) implementation and gate count is used to evaluate the complexity of a gate array implementation. It is to be noted that throughout this paper the evaluation of complexity follows [8] and some optimization in speed or in chip area could lead to different complexities.

In. SIMPLIFICATION OF THE HIGH RATE SOIT DECISION DECODER

In this section, a three step simplification of the AAPP decoder is presented. It involves a) feedback modification, b) the

745

separation of the information bits and reliability bits processing and c) the use of partial reencoding. These three successive reduction techniques will be explicitly described and the three resulting circuits for the rate 3/4 SPADE CSOC will be illustrated.

A . Feedback Modification

The first simplification consists in inserting the decoded information bits directly in the parity register thereby eliminating b registers using m 1-bit delays. With this simplification, we obtain the decoder architecture of Figure 3. This modification does not change the parity check equations, therefore the performance is not affected. The feedback modification may be viewed as a partial syndrome computation accounting for the received parity and the decoded bits. The parity register thus becomes akin to the syndrome register of the type I decoder (Figure 1) without the reencoded parity.

Using the notation of Appendix A, an explicit algebraic description of the feedback modificatiy may be presented as follows. In equation (A.6), if the term ikj was not excluded, the double sum would consist in recomputing a parity. Since this sum involves some decoded bits, when (hb-hml) is smaller than 0, we could include a partial sum as a recomputation of parity. Specifically, when feedback is included in the parity register each cell of this register contains the parity added to the appropriate previously decoded bits:

where P F (k, j ) stands for the contents of the kth cell from the right of the parity register when the j f h information bits are decoded, as in Figure 3.

By combining this last equation with equation (A.6), we obtain:

which is equal to eq. (A.6) but uses the contents of the parity register with feedback explicitly.

The simplification does not only reduce the size of the circuit, it also provides economical means for the inclusion of soft quantized feedback. This simplification eliminates most components of the first and second columns of Table 1 (the binary delay and 2-input Exclusive OR cells) and adds Jb add- min operators.

746 IEEE TRANSACTIONS O N COMMUNICATIONS, VOL. 43, NO. 2/3/4, FEBRUARY/MARCH/APRIL 1995

B. Separation of the Information Bits and Reliability Bits Processing

The second simplification comes about by noting that before the threshold, all the operations on the information bits and the reliability bits are independent. Indeed, the only operator that is used, the add-min, treats the information bits (with a minimum operation). This means that 2 independent "decoders" without threshold may be used as shown in Figure 4. The received information and parity bits may thus be treated with the architecture of the hard decision decoder, thereby obtaining all the desired hardquantized syndromes. The reliability bits, for which the minimum operation is irreversible, are treated with the usual AAPP architecture and the desired reliabilities of the syndromes are obtained.

This modification provides an important reduction of the number of modulo 2 additions. Instead of using 0.5 J2b2 add- min, we now have 2 Jb modulo-2 additions and 0.5 J2b2 minimum operations. Another beneficial effect is permitted by

the replacement of the b m-bit length shift registers by random access memory, RAM.

C. Partial Reencoding and Replacing Shi@ Registers by RAM At this point, the most complex part of the decoder is the

reliability bits AAPP architecture. In particular we are still left with 0.5 J2b2 minimum operations. These operators are needed to compute the part of the syndromes that depend on the undecoded reliability. At the cost of using more shift registers, one may replace part of these operations by pipelining. As can be seen on Figure 3, many of the operations involving the same value are repeated during different clock intervals. For example the first two operations from the left needed for SAA.3, SAA.4, SAB.2, SAB.3 ... involve the received reliability of i, separated by 3 time intervals. This operation can be accomplished once and then stored appropriately. This pipelining technique may be viewed as a partial reencoding using the (I-R)n, stage encoder architecture.

SAB.1 S A C . 1

SBA. 1 SBC.1

SBB.2 SBB.3 SBB.4

S B A . 2 SBA.3 SBA.4 SBC.2 SBC.3 SBC.4

SBB.O-A

PB.2 SAB.3

SBB.3

PB.3 SAB.4

'3'

P'

I 1 1

- S C A . 1 SCB. 1

scc.0 SBC.1 TC.l

Figure 3 Simplified AAPP Soft Decision Decoder

-

IEEE TRANSACTIONS ON COMMUNICATIONS, VOL. 43, NO. 2/3/4, FEBRUARY/MARCH/APRIL 1995

i3:7 p - l M decision decode r

without thresholds

(Decoded bits)

(4- 1) TA. 0 Reliability bit AAPP TA.4

decoder without p A . 3 thresholds

TB.0 TB. l

-

I I ".C

78.3 18.4

TC.0 TC.1 TC.2 TC.3 TC.4 .

Figure 4 Hybrid Soft Decision Decoder

Partial reencoding consists in keeping parts of the double sums in eq. (2) readily available, by computing them with the (1-R)n, stage encoder architecture. Basically, the sums in eq. (2) may be partially computed with L reencoders (L < 4:

m=I 1=0

Here, all of the i* are received (non-decoded) information bits and RE,, (k, j ) represents the contents of the nth reencoder, k cells from the right when the j f h information bits are decoded. Combining equations (2) and (3) we may now rewrite the syndromes as:

b

s, (kJ j ) = C ii, ( j+hb -hmn) + ~ ~ ( h h , j ) (4) m=l m#k

hW'hmJ

where the last sums are needed if and only if L < J-1. For each of the syndrome calculation, we now need only

- b 2 ( J - L ) J for the b2J computations for the first sum, 2 2

double sum, bL computations for the L reencoders (eq. 3 ) and b (J-1) computations for the feedback in the parity (eq. 1). If a hybrid decoder is used all the additions in the above equations

141

represent minimum operations. Furthermore, mL 1 -bit memory cells are needed to implement the partial reencoders.

The number of reencoders, L, is not strictly linked to the number of parity check equations of the information bits. One could partition the sums in eq. (2) to have an arbitrary number of reencoders. In the limit, we could have one reencoder for each parity check equation of each bit and one operation would then be needed for each of the Jb reencoders. Unfortunately, we would significantly increase the size of memory being used. For the sake of simplicity, assume that the partition of the sum is accomplished as in eq. (3). This partition is possible, if the following conditions are met:

For all i, j , k, n where i Ib, n < k < L,

we must have hik > hjn . (5)

The amount of memory that may be implemented with RAM instead of flip-flops depends on the greatest difference (hkn-hmn) or (hkn-hml) in eq. ( 3 ) . Specifically if K b is the amount of memory implemented in RAM, the following condition must be met:

m-K 2 l t ~ x ( h h - hml) = m-K,, 1 = I ... L; m, k = l ... b; n=l ... J

As an example of this technique, two partial reencoding registers have been used for the architecture of Figure 5. The results of the complexity analysis are summarized in Table 2.

For the SPADE system, one might readily compute from this table the complexity of the soft decision decoder circuit with a 3-bit quantization: 200 binary delays, 24 2-input XOR, 51 2-input minimum operator and 126-bit RAM.

748 IEEE TRANSACTIONS ON COMMUNICATIONS, VOL. 43, NO. 2/3/4, FEBRUARY/MARCH/APRIL 1995

BASIC CELLS Binary k- b- BAM kotal Loding

Transistorlcell gatelcell q=1 cells

- belay input input without gain

XOR Min RAM at 10-6 8 4118 --- __ -- 6

5 --- lo 2117* -- -- 336 184 -- 3864 2dB

w

Feedback simplifi- cation

Hybrid simplifi- cation

Reen- coding

m+qm 0.5 J2b2 (b+l) +Jb

(4-1)mb 2 Jb +(q+l) m

(q-1) [(m-K) 2 Jb b+mL] +(q+l) m

trans. gates

q=2 cells I i 3 trans.

2688 1104 --- 3792

3361 184 1196 5543 2.9dB 26888 1104 7176 35204

3360 920 --- 4280 .

r e 7 3 gates q=3 cells

33610 920 2392 36922 6050 184 1196 7222 3.2dB

Y S A A . 0 SAB.l SAA.0

s . ww b S A B . 2 PA.2 r SAA.4

PA.4

I SAB.4

PB.4

Lf6ENO. 1A.I. 78.1. TC.1: aa In Flpuro 1. S8C.I: Partlol result from the iz' regtrtor @) going to @ a t 1C.t.

PCJ: partial rorutt trom tho P' reptrter point to 0 at 1c.i. - ""I."

PC.4 PA.4 PB.4 PB.3 PA.3 PC.4 PC.3 PB.2 PC.2 PA.2 PA.1 PB. 1 PC.1

Figure 5 AAPP Soft Decision Decoder with Partial Reencoding

TABLE 2 COMPLEXITY OF EACH SUBSEQUENT SIMPLIFICATION

TABLE 3 SUMMARY OF SIMPLIFIED AAPP DECODER COMPLEXITIES

AND BIT ERROR PERFORMANCES Binary 2-input delay * XOR

2-input min.

RAM (bits)

~ ~~~

(0.5) J2b2 --

( O S ) J2b2 +(J-1) b

(0.5) J2b2 +(J- 1) b

mb

(0.5) b2 J (J-L) +Lb + (J-1) b

mb +(q-1) Kb

* The 8-ary delay has been converted into parallel binary delays.

* q=2lq=3 * * K>Kmax=73, strictly speaking this is not an AAPP decoder

IEEE TRANSACTIONS ON COMMUNICATIONS, VOL. 43, NO. 2/3/4, FEBRUARY/MARCH/APRIL 1995

~

149

Pe

I ! I I 1 I I

0 01

0 ml

I. IO+

I. 10-

P10+

I \I \ \ I\ \ I I I I & \\ I \ \ I I I

I I n u I \ \I I

m i \ U I\ \ \ h I \ \ \ I \

L I I l \ L I L I I \ l 5 6 7 8 9 I O I 1

* Hardquant. Eb/No (dB) + 3-bilAAF'P[8] * 2-bil soh (quant. feedback) * 3-bil soft (quanl. feedback) - UKded PSK

Figure 6 Simulated Bit Error Probability of Soft Decision Decoding for the Rate 23/24, Constraint Length 4056 CSOC with the Decoder Architecture in [8] and the New 2-bitI3-bit Soft Quantized Hybrid Architectures.

IV. DESIGN AND PERFORMANCE CONSIDERATIONS FOR A RATE 23/24 CSOC

In this section, we consider the design of a soft decision AAPP decoder for a rate 23/24 double error correction convolutional code. In the following, we discuss the performance and complexity tradeoff for one, two and three-bit quantization.

Let us first recall that the straightforward implementation of the 3-bit soft quantized AAPP decoder in accordance with Lavoie et al. [8] involves the use of about 250 000 transistors (or gates). Furthermore, extensive computer simulations have been run for Bit Error Rates (BER) of lo-* to they show that only 0.9 dB is gained with such a decoder as compared with a hard decision decoder. Such an architecture is clearly not suitable for the code under consideration.

The proposed new architecture complexity may be computed from the equations in Table 2. Detailed results for 1, 2 and 3 bit quantization of the received signals are shown in Table 3. For example a 2-bit quantization (q=2) with three reencoders (L=3) and 73 stages of information registers stored in RAM (K=73). Such a system would need 3 361 binary delays, 184 XOR's, 1 196 minimum operators and 5 543 bit RAM. The overall complexity would be 35 204 transistors or 36 922 gates with 5.5 K bit RAM. Figure 6 shows BER vs.

E f l o for the AAPP original scheme [7, 81 and for different quantization of the AAPP decoding presented here.

It is to be noted that the K parameter, which determines the number of received information reliabilities stored in RAM, has been set to two values: the maximum value in a strict sense, K=Km,=73 and a value exceeding this K=118. The maximum value of K corresponds to the largest value of K to implement the original AAPP decoding algorithm. When K exceeds this value, some reliability bits are not taken into account for the computing of the syndromes. This should thus introduce a performance degradation. But with K=118 , only 1% of these reliability bits are not used and simulation results show no noticeable performance degradation.

Our best 3 bit quantized scheme uses 54 472 transistors with 9 K bits of RAM and improves the coding gain by 1.2 dB as compared to hard quantized decoders. This roughly corresponds to a four fold complexity simplification with a 0.3 dB coding gain improvement as compared to the original AAPP scheme. Of particular interest is the 2-bit quantized decoder, with a much reduced complexity, 26 888 transistors and 6.6 K bits of RAM, it improves the coding gain by 0.9 dB as compared to the hard quantized case which uses 3 792 transistors and 3.8 K bits of RAM. With the advent of very dense gate array technologies this 0.9 dB improvement may be easily implemented in most systems using threshold decoders.

APPENDIX A

ALGEBRAIC NOTATION FOR THRESHOLD DECODING

A high rate b/b+ I systematic convolutional self-orthogonal code may be specified by b polynomials used to compute the parity. These polynomials have the following form:

k = l ... b

For notation purposes, we may also write the equations by explicitly writing only the J non-zero terms:

k = l ... b

Where h,, = 0 for n = I , 2, ..., b. To represent the encoding procedure, let us specify the b information bit sequences as:

m

= C ikj DJ , j = O

The encoded parity is thus: 3 P ( D ) = po + p1 D + p2 D2 + p 3 D + .. .

m b

= c P j DJ = c ( G k ( D ) Ik (D) ) j = O k=I

(A.4)

750 IEEE TRANSACTIONS ON COMMUNICATIONS, VOL. 43, NO. 2/3/4, FEBRUARY/MARCH/APRIL 1995

and each pj may be written explicitly as a function of the past information bits (ik, = 0 if j < 0):

k = l 1=0 Denoting received symbols with a star (*), if i; and p; are

received information and parity bits, the decoding process consists ip computing the following syndromes1 for each received ikj :

excluding iky, n = l . . . ( J - I ) (A.6)

As can be seen, for the computation of each syndrome, bJ operations are needed with a type I1 decoder. Since there are bJ syndromes for each group of b information bits, a total of b2 J2 operations are needed to compute the syndromes in a type I1 decoder.

171

[91

REFERENCES

J. G. Proakis, Digital Communications, 2nd ed., New York: McGraw- Hill, 1989. J. L. Massey, Threshold Decoding, Cambridge, MA: MIT Press, 1963. W. W. Wu, “New Convolutional Codes - Part II”, IEEE Trans. Commun., vol. COM-24, pp. 19-33, Jan. 1976. W. W. Wu, “New Crinvolutional Codes - Part I l l” , IEEE Trans. Commun., vol. COM-24, pp. 946-955, Sept. 1976. H. Tanaka, K. Furusawa, and S. Kaneku, “A Novel Approach to Soft Decision Decoding of Threshold Decodable Codes”, IEEE Trans. Injbrm. Theory, vol. IT-26, pp. 244-246, Mar. 1980. C. C. H. Yu and D. J. Costello, Jr., “Generalized Minimum Distance Decoding Algorithm for Q-ary Output Channels”, lEEE Trans. Infi,rm. Theory, vol. IT-26, pp. 238-243, Mar. 1980. D. Haccoun, P. Lavoie, and Y. Savaria, “New Architectures for Fast Convolutional Encoders and Threshold Decoders”, IEEE J. Select. Areas Commun., vol SAC-6, no. 3, pp. 547-557, Apr. 1988. P. Lavoie, D. Haccoun, and Y. Savaria, “New VLSI Architectures for Fast Soft-Decision Threshold Decoders”, IEEE Trans. Commun., vol. COM-39, pp. 200-207, Feb. 1991. S. Lin and D. J. Costello, Jr., Error Control Coding: Fundamentals and Applications, Englewood Cliffs, NJ: Prentice-Hall, 1983.

These are not the usual syndromes as in [2], we use this term to lighten the text. The real syndromes are S, (k , j ) + i d .