Lloyd Dixon

margin. Thus a phase lag of 117° at fc correspondsto a 63° phase margin.

Fig. 1 shows the gain -phase plots of two aver-age current mode control loops and their transientresponse to a step change in load current. Bothloops cross over at 10 kHz.

Bode plots are simplified gain -phase plots thatare convenient for depicting the frequency charac-teristics of a feedback loop.

The 1 POLE loop has one active pole from 10Hzto over lookHz. Thus the phase lag atfc is 90° andthe phase margin is also 90°. Note that with the -1slope associated with a single pole, the gain doesnot rise rapidly at lower frequencies. The lower

Summary:This paper surveys many practical aspects of

control circuit design. Topics include: differentapproaches for achieving Nyquist stability criteria,transient response vs. phase margin, low frequencyaccuracy vs. the shape of the Bode plot, why it isdangerous to depend on conditional stability,achieving the maximum crossover frequency of aswitched loop., other factors which may limit loopbandwidth, sources of error, and where to place thegain needed for correction.

Other practical aspects include large signalbehavior and how to minimize offset error delays ofcompensation capacitors in the feedback path.

Control Loop BasicsThe control loop in a high perfonnance switching

power supply requires high gain, to achieve goodregulation, and high bandwidth, to achieve rapidresponse to sudden changes of line or load.

Control loop gain inevitably declines at highfrequency, limiting bandwidth. The frequency atwhich the loop gain crosses through 1 (OdB) isdefined as the crossover frequency,fc. The declin-ing loop gain at high frequency is accompanied byphase lag (in addition to the nonnal 180° phaseshift associated with negative feedback). Theamount of additional phase lag is a function of howrapidly the gain drops with frequency. According toNyquist' stability criteria, the loop will be unstableif the additional phase lag exceeds 180° at thecrossover frequency.

If the excess phase lag atfc is very close to the180° limit, the loop will be stable but the transientresponse will exhibit under-damped oscillations(ringing). A clean transient response requiresconsiderably less than 180° excess phase lag atfc.The amount less than 180° is referred to as phase

Fig. 1 -Gain -Phase Plot and Transient Response

Control Loop Design

gain/bandwidth will hurt power supply characteris-tics such as regulation and audio susceptibility.Note also that the transient response is slower. Thearea between the [LOAD step change and the 1POLE response curve represents a charge deficit inthe output capacitor that is never made up, exceptby the output voltage ultimately sagging and callingfor more current,

In the 2 POLE loop, if the two poles were activethrough and well abovefc (IOkHz), the phase lag atfc would approach 180°-almost zero phase margin.The transient response would exhibit severe ringing.But the 2 poles are not active above SkHz. A zeroin the control amplifier causes a -2 to -1 slopetransition at fc/2, This results in 117° phase lag, ora phase margin of 63°, Below SkHz (fc/2), the -2slope causes the gain to rise rapidly at lowerfrequencies, optimizing gain-bandwidth, With the-1/-2 zero transition at fc!2, transient response iscritically damped-see Figure 1. The initial chargedeficit is not only smaller, the slight overshootcompensates precisely for the initial deficit. This ischaracteristic of a critically damped system.

At frequencies well below the zero atfc!2, phaselag does approach 1800 , and the phase marginvanishes. This is desirable because it is associatedwith the -2 slope which rises rapidly at lowerfrequencies, improving gain-bandwidth. 180° phaselag is also acceptable. Adequate phase margin isrequired only at fc. The circuit will not misbehavewith 180° phase lag at frequencies below fc , as longas there is adequate phase margin at fc .

Two poles are shown occurring near 10Hz: thepower circuit inductance with its series resistance,and the control circuit operational amplifier reach-ing its gain limit. Loop gain flattens out, and excessphase lag diminishes toward 0°.

Conditional Stability: The criteria for loopstability pennits the phase shift to actually exceed180° (negative phase margin) at frequencies below

fc. This is called "conditional" stability because itdepends upon the strict requirement that the phaseshift be 1800 (preferably much less) at the unitygain crossover frequency. Thus, the 180° limitationapplies only at fc where the gain is 1, not at anylower frequency even though the gain may be high.

It is usually not wise to depend upon conditional

stability. Under conditions such as startup or largerapid load changes, operational amplifiers in theloop may be driven "into the stops". This is equiva-lent to a temporary reduction in loop gain andcrossover frequency. If phase shift exceeds 1800 atthe temporarily lower fc, the circuit will likelycommence a large signal oscillation from which itcannot recover .

In summary , the gain characteristic should havea -I ( I pole) slope as it traverses the unity gaincrossover frequency. A zero at fc/2 will result in a-2 (2 pole) slope at lower frequencies. This willprovide optimum bandwidth and critically dampedtransient response. The phase lag approaches 180°at lower frequencies, but this is quite acceptable.However, it is unwise to go beyond 180° anddepend on conditional stability .

With inadequate phase margin, the ringing fre-quency will be at or near fc.

Crossover frequency: The unity gain crossoverfrequency,fc, is usually the best starting point foroptimum control loop design, working back towardlower frequencies to obtain the best possible gain-bandwidth.

Theoretically, fc of a linear closed loop systemcould be at any frequency, provided the criteria foradequate phase margin are fulfilled. In practice, itbecomes necessary to cross over the linear systemwhen cumulative phase shifts of various loopcomponents become too great to compensate. Thisproblem is compounded when gain and phase shiftof various loop elements change, sometimes unpre-dictably, due to tolerances and temperature effects.

Switching power supplies control loops haveadditional complications that can limitfc. The righthalf-plane zero encountered in the output of contin-uous mode boost and flyback topologies is not onlynear-impossible to compensate, it moves in frequen-cy as a function of load. With voltage mode con-trol, loop gain varies as a function of input voltage.With discontinuous operation or with current modecontrol, voltage loop gain varies with load. All ofthis can make it extremely difficult to achieve ahighfc while adhering to Nyquist' stability criteriaunder all conditions of operation.

One reason current mode control can providebetter control loop performance is that the current

7-2 UNITRODE CORPORATION

Control Loop Design Examples

Definitions:

Rt: "transresistance"-the translation of inductorcurrent to a voltage, Vi' In its simplest form,Rt = current sense resistor Rs. With a currenttransformer, Rt = RsIN.

Vs Sawtooth voltage, peak-peak

Is Switching frequency

Ici Current loop crossover frequencyIcv Voltage loop crossover frequency

loop and the outer voltage control loop are bothsimplified, making it much easier to achieve highcrossover frequency in both loops. For example, ina buck-derived regulator, the current loop has todeal only with the inductor pole, while the outputloop deals only with the output capacitor and itsvariable ESR zero.

Slope limitations: Buck derived topologies arerelatively easy to compensate, especially if currentmode control is used. A high Ic could be realizedunder Nyquist' criteria alone, but another limitationis encountered that is unique to switched loops:After the waveforms applied to the PWM compar-ator inputs converge, (causing the power switch toturn oft), the waveforms should then cross over anddiverge (or at a minimum coincide). Otherwise,subharmonic oscillation will occur under certainoperating conditions. With peak current modecontrol, slope compensation corrects this problem(and reduces the loop gain). This problem exists inany switched loop, but it is more likely to be thelimiting factor in buck-derived circuits. The solutionrequires limiting the control amplifier gain at theswitching frequency, which indirectly limits Ic to1/3 to 1/10 of Is.

Other phase margin considerations: The mostusual method of assuring adequate phase marginand clean transient response with minimum loss ofgain-bandwidth is to put a control amplifier zero atIc/2, making a loop gain slope transition from -2below Icf2 to -I above. To attenuate switchingnoise, a control amplifier pole is sometimes addedat a frequency above Ic. This pole converts the -Islope at Ic to a -2 slope at higher frequencies. Itshould be I decade above the previously placedzero, and also above 2. Ic, to maintain adequatephase margin. (Be carefuHhis high frequency polemay impair response for peak current limiting.)

A completely unique situation arises in the volt-age loop of a high power factor preregulator. Theloop gain must be very low at 2. JUNE (120Hz) tominimize 2nd harmonic distortion feedback. Thecrossover frequency, although well below JUNE,must be as high as possible to obtain reasonableloop dynamics. The optimum solution is to use a -2slope above Ic up to 2. ftJNE, with a pole slightlyabove Ic to transition to a -1 slope below Ic.

A verage Current Mode Control Loop

Fig. 2 is the circuit diagram of a buck regulatorwith an average current mode control loop. Fig. 3is the small signal equivalent circuit. Fig. 4 is theBode gain plot of the PWM/power circuit, thecurrent amplifier, and the overall current loop gain.

Conditions:

Vi = 7-14V Vo = 5V L = IOpHC = 5000pF Rc = .02 10 = 15 ~ 20A

Rt = .05.0 Vs = 5V Is = lookHz

Description: Referring to Fig. 2, Inductor currentI L is sensed and converted into equivalent voltageVi by transresistance Rt. Current amplifier (CA)amplifies the differential between vi and currentprogramming voltage V SET. The amplified errorapplied to the PWM comparator controls the dutycycle of the power switch. This in turn controls theaverage inductor input voltage, changing currentuntil vi equals V SET. IL then equals VsETIRt.

Goal: Obtain the highest crossover frequency,fci, consistent with equal slopes at the PWMcomparator inputs during the OFF time, and with asingle active pole (-1 slope) at crossover.

Strategy: The PWM/power section has a 1-poleslope above resonance (from the filter inductor).For the overall -1 slope required at crossover, theCA gain must be flat from below Ici to above Is. Azero in the CA makes the transition from -1 to -2slope below Ici/2 to achieve low frequency boost,with critically damped transient response.

7-3Control Loop Design

Implementation:

Sawtooth slope:dvs/dt = Vs/Ts = 5V/IOpsec = O.5V/psec

Inductor current downslope (during OFF time),

converted into an equivalent voltage downslope by

transimpedance Rt:

di/dt = Vo/L = 5V/IOpH = O.5A/psec

dvj/dt = Rtdi/dt = .O5xO.5 = .025V/psec

Fig. 2- Average Current Mode Current Loop

60 "!S;; CA ~aln

G = v./v = Vin Rt --j159Vinp I CA ---

Vs roL Is

40

Set Gain = 1 and Vin=7V to fmd fci mill.:

fci = 2385Vin = 16.7kHz mill at Vin=7V

20

'"""00-0"-'~ 0

<x:~

-20

Z xc

Z=RL

IJPwrGai =~Vs Z

-40

1 10 100 1K 10K 100K

Fig. 4- Current Loop Bode Plot

PWflCurrent Amp. compensation: Zero atfci!2 (8kHz)

1 1Cfi= = = 260pF

21tf Rfi 6.28'8kHz '75k

When the current loop is closed, its gain is atransconductance: iLIVSEJ' = I/Rt. The closed loopgain is flat until it rolls off at the open loop cross-over frequency, fci. This characteristic makes iteasy to include in the outer voltage loop.

7-4 UNITRODE CORPORATION

Demonstration: Fig. 5 showsthe stability and transient response 7 .of the current loop with compen-sation as calculated above. Thebottom two curves are the current 4 ,

programming voltage, VSEf, and Vi'which equals ILxRt, The top twocurves are the two PWM compar-ator inputs: sawtooth voltage Vs, D ,and the current amplifier output, 1 .

VCA.At the beginning of the demon- 1. D~

stration, I L has been regulating at15A (0.75V across Rt). At time 0,VSEf changes instantaneously from D, B~

0.75V to IV. This new demand for20A cannot possibly be fulfilled by Dus 20us 40us 60us

any con,trol ~ircuit ac~ion. The, C.A Fi , 5 -Current Loop Waveforms with Current Changeoutput IS driven to Its 7V limit, 9

calling for the power switch to be fully ON. But ittakes 25psec (several switching periods) for IL toreach 20A at its max. slew rate of (Vin-Vo)IL =

0.2Npsec. The control loop is temporarily open.While IL is slewing from 15A to 20A, the error

input to the CA causes feedback capacitor Cfi tocharge, developing a voltage offset. When ILreaches 20A, the Cfi offset holds the CA output outof the normal PWM input range (see Fig. 5). ThusI L rises above 20A until the Cfi offset is dischargedback to normal. This is not an operational flaw-itis actually beneficial. During the initial 25psecwhile I L is low, the output filter capacitor has acharge deficit. The excess current after 25psecrapidly restores this charge deficit. If this overshootdid not occur, Vout would sag. The charge deficitwould then be restored over a longer time by actionof the voltage loop in an actual power supply. Theovershoot results in better performance. Note thatthis is not the same as the overshoot associatedwith critical damping of the current loop. Thecurrent loop is in fact open during this time-this isa large signal phenomenon.

BOus 100us

Adding the Voltage Loop

Fig. 6 is the circuit diagram of a buck regulatorwith a voltage control loop added to the averageCUlTent mode control loop previously discussed.Fig. 7 is the voltage loop small signal equivalentcircuit. Fig. 8 is the Bode gain plot of the powercircuit (including the closed CUlTent loop), thevoltage amplifier, and the overall voltage loop gain.

Conditions:

Vi = 7 ~ 14V Vo = 5V L = IOpHC = 5000pF Rc = .01-.02 10 = 15 ~ 20A

Rt = .05.0, Vs = 5V Is = lOOkHz

Description: Referring to Fig. 6, a voltage erroramplifier (V A) replaces V SET in Fig. 2. The V Aamplifies the elTor between Vo and the 5V refer-ence. The V A output, VVA' programs a constantinductor current according to the transconductanceI/Rt of the closed CUlTent loop.

Goal: Obtain the highest crossover frequency,Icv, consistent with equal slopes at the PWMcomparator inputs during the OFF time, and with asingle active pole (-I slope) at crossover.

Strategy: Referring to Fig. 8, the power circuitgain equals the current loop transconductance I/Rttimes output impedance Zo which varies with

7-5Control Loop Design

Fig. 7- Voltage Loop Small Signal Equiv. Ckt

the higher voltage capacitor has the same ESR butlower capacitance, thus higher ESR zero frequency .)The penalty is a lower output surge impedance lesscapable of standing up to a large signal incidentsuch as a sudden large load change.

Implementation:

Inductor current downslope (during OFF time),converted into an equivalent voltage downslope byRc, the output capacitor ESR:

di/dt = Vo/L = SV/lOpH = O.SA/psec

dvv/dt = ESRdi/dt = .O2xO.S = .OlV/psec

frequency. Current loop transconductance is flat upto tci (16.7kHz), where it rolls off with a -I slope.

The biggest problem is with variation of Rc, theoutput capacitor ESR, and the zero it places in theloop. In this example it is assumed that Rc varieswithin a 2:1 range (.01 to .020). The zero, tESRranges between 1.6 and 3.2kHz, which is below thedesired crossover frequency,tcv. The power circuitgain is flat fromtESR throughtcv up to mintci, thecurrent loop gain roll-off at 16.7kHz.

The V A gain is made flat at switching frequencyts. Inductor ripple current flowing through ESR Rcgenerates a sawtooth waveform which is amplifiedand inverted by the V A and applied to the CA non-inverting input. This sawtooth is in phase with thesawtooth across Rt at the other CA input. Thus theOFF-time slope at the PWM comparator input isworsened. An allowance was made for this in theCA gain, but the V A output slope must be limitedto 112 the slope across Rt, limiting V A gain atts,

The V A gain has a zero attci (16.7kHz), belowwhich it has a -I slope. Thus the overall voltageloop gain has a -I slope from tc down to t ESR'Crossover tcv varies with Rc from 4 to 8kHz,Below tESR' the overall voltage loop gain has a -2slope. This boosts the voltage loop gain at lowerfrequencies, but also makes it important that maxtESR is below minimum tcv.

There are two other alternatives:I. Wide ESR zero range. If maxtESR is closer tomintci than the above example, it will be impossi-ble to safely cross over anywhere above tESR. V Again must be very low and flat from well belowtESR all the way up tots. Overall gain rises only asthe power circuit gain rises below mintEsR' result-ing in tcv way below min tESR' This is a mostundesirable situation.2. Min ESR zero above desiredfcv. (this might bethe case with ceramic output fIlter capacitors,) Thepower circuit gain has a -I slope from the RL Cpole (127Hz) all the way up to tci. The V A gainmust be flat above tcvf2, and is limited by slopeconsiderations, A zero in the V A gain gives theoverall gain a -2 slope below tcvl2, This desirablesituation can be created with electrolytic outputfilter capacitors by using a much higher voltagerating than necessary .(For the same size and cost,

Because of slope limitations at the PWM com-parator, the sawtooth slope at the V A output mustbe limited to 1/2 the slope across Rt (dvi/dt). Thusthe voltage amplifier g~ atfs is:

G = vVA 7~ = ~\= 1.2VA / 2dvv/dt 2x.O2 \

\!4'

(iyRiv = 10k, R.fv = 12k

, (j~flIJ .1(,,0. (

7-6 UNITRODE CORPORATION

A zero is put in the V A gain where current loop

transconductance rolls off at minfci (16.7kHz):

1 1Cfv= = = 800pF27tf ZERORfv 6.28-16.7kHz-l2/c;

The V A gain below this zero is:

VVA -j1.2fzERO -j20,()()()GVA = -= =Vo f f

The power circuit gain between the ESR zero

frequency and fci (16.7kHz) is:

~ = !!.:.. = .!!!. ='0.4vVA Rf .05

Overall voltage loop gain, and crossover freq.,

fcv:Fig. 8 -Voltage Loop Bode Plot

Gv= ~.0.4 = ~ ;

f f

fcv = 8kHz

Demonstration: Fig. 9 shows the stability andtransient response of the voltage loop. The bottomtwo curves are the voltage eror amplifier output,VVA' and vi' which equals ILxRt. The top two curvesare the two PWM comparator inputs: sawtooth volt-age Vs, and the current amplifier output, VCA. Theoutput voltage is not shown. (The charge deficit vs.time revealed in the current waveform causes a maxVout deviation of only l3mV.)

This demonstration is identical to the earlierCUlTent loop demonstration, except that the voltageat the CA input which programs the cUlTent is theoutput of the voltage error amplifier, vVA. Duringthe time the control circuit is "in the stops" whilethe inductor CUlTent slews to its new value, thefeedback capacitor Cfv around the V A also chargesto a voltage offset. This further increases the ILovershoot, which now almost exactly cancels the

earlier charge deficit.After the CUlTent transition from

lSA to 20A load has been complet-ed, a 2:1 line voltage change isdemonstrated. At lOOpsec, the inputvoltage is changed instantaneouslyfrom 7V to 14V. Note how theduty cycle is reduced in the veryflfSt switching cycle. The longerOFF time increases inductor rippleCUlTent and the V CA ripple, but theslopes at the PWM input remainnearly coincident as seen in theupper waveforms.41.0'

Vin=N --0 Vin = 14VO.8~

I I I I I I I I

OuS 2Ous ~Ous 6Ous BOus 1OOus 12Ous 1~Ous

Fig. 9- Waveforms with Load and Line Changes

7-7Control Loop Design

Powe

80 I -J ! ,

i Circuit 1aln = .241 l

60

40fainv

20

=--E!Q.,

-20 10 100 1K 10K 100K 1M

Fig. 11 -Flyback Bode Plot

fz=x~'

,

,,"

'"""'CD-0'--'

~<x:~

1(1-0j0Go

higher crossover frequency.There are two unique considerations in the design

of the average current mode control loop for theflyback circuit. First, the diode current is beingsensed, averaged and controlled, not the inductorcurrent. The diode current is a large amplitudeessentially rectangular waveshape. It is necessary tointegrate this waveform to obtain its average cur-rent. The integrating capacitor, Cpi, added to theCA feedback network must be small or it wouldhurt the loop bandwidth. The CA output has asawtooth ripple component from the integration,analogous to the sawtooth inductor ripple cun-ent.

Second, the sawtooth waveform at the CA output

Flyback with A verage Current Mode

Control

Fig. 10 is the circuit diagram of a flyback regula-tor operating in the continuous inductor currentmode. Fig. II is the corresponding Bode gain plot.

Conditions:

Vi = 6 ~ 12V Vo = 5V L = 1.375pHC = 50,000pF Rc = .002 /0 = 20A

Rt = .05.0. Vs = 5V Is = 100kHz

Description: The flyback topology is popularbecause of its simplicity , having one magneticdevice which is also capable of providing isolation.Discontinuous flyback operation is simple, butsuffers from high peak secondary current-80A fora 20A output. When the power switch turns off,80A peak is suddenly delivered to the output,putting a tremendous burden on the output filtercapacitors. Continuous mode operation can almosthalve this peak current, easing the burden on the

output capacitors.The big problem with continuous mode flyback

circuits is the right half-plane (RHP) zero whichappears in the loop gain characteristic. The cross-over frequency, fc must be well below the RHPzero frequency. This is more difficult because theRHP zero moves considerably with load and withVin. The designer's dilemma is that if the inductoris made large to remain in continuous conduction atlight loads, the RHP zero frequency is very low. Ifthe inductor is made small, the circuit cannot beoperated with light loads, because the loop gaindrops too much when the mode boundary iscrossed.

Average current mode control helps solve thisproblem in several ways: (I) It controls averageoutput (diode) current, thus the RHP zero is dealtwith and "buried" in the current loop. (Conventionalcurrent mode control controls the wrong current-inductor current-and does not deal with the RHPzero. (2) Because of the gain provided by thecurrent error amplifier, the current loop can operateacross the mode boundary and maintain acceptableregulation. This allows the inductor to be smaller(limited only by higher peak current considerations),which raises the RHP zero frequency permitting a

7-8 UNITRODE CORPORATION

A pole at fc/2 (2500Hz) provides a -2 slope for

low frequency gain boost:

1Cfi = = 1768pf21tfRfi

is 180° out of phase with the sawtooth waveformseen in the buck regulator. Rather than concernabout too much slope during the OFF time, theconcern now is with the ON-time slope. Theworst-(;ase ON-time slope should be 1/2 the slopeof sawtooth voltage Vs.

Implementation:

Sawtooth slope:dvs/dt = Vs/Ts = 5V/IOpsec = 0.5V/psec

= lOOpFCpi =

The minimum RHP zero frequency occurs withmin Vin and min load resistance. (D = Vol(Vi+Vo»

(I-DfRLfDUD7 = = 14.5kHz

Some Practical Control Loop Problems

Compensation Capacitor Problems: It isusually essential to use capacitors in compensationnetworks around the error amplifiers in the controlloop. Compensation capacitors which break the DCpath between op-amp input and output operate witha DC bias voltage. This is not a problem understrictly small-signal operating conditions. But whenline or load changes occur, or during startup, theamplifier output voltage must change. This requiresa change in the DC bias across the series compen-sation capacitors. The charging current required cancause significant errors or delays in the transientresponse of the power supply.

Small capacitors with short time constants whichprovide high frequency compensation (such asadequate phase margin at crossover) don't usuallycause problems. The problem is with larger capaci-tors (with long time constants) which are put inseries with the feedback path around the amplifierfor two reasons: (1) To break open a DC patharound the amplifier which is causing a DC offseterror, or (2) To boost the low frequency gain to

obtain near-perfect regulation.Transient behavior: What is the good of im-

proving the DC regulation if the transient responseis hurt? (The answer might be that your customeronly looks at DC regulation.) Consider what hap-pens with a significant and rapid load change.Without the series capacitor, there will be a DCpath around the amplifier and finite DC gain.Assume that the output voltage changes from 5.1Vwith light load to 5.0 volts at full load. A seriescapacitor provides a low frequency zero whichgreatly improves regulation. Assume perfect regula-tion: 5.0V at light and at full load. But when theload suddenly decreases, Vout will swing momen-tarily to 5.1 V, then return precisely to 5.0V. Later,when the load suddenly increases, Vout will swing

v.I .39=VCA

The CA gain must be flat from fc/2 to wellabove crossover to maintain an overall -1 slope. Tocross over at SkHz, the CA gain must be thereciprocal of t~ PWM/power circuit gain:

~ = 1/1.39 = 0.719v.

I

Rfi = O.719Rii = O.719x SOK = 36K

7-9Control Loop Design

During the ON time, the voltage across trans-resistance Rt is zero, so V SET is across the SOKintegrator input resistor Rii. The integrator is set upfor dvCA!dt = 1!2dVs!dt under worst case conditionof V smmax = 1.2V (corresponding to current limit).

D L

Since there is so much -excess phase shift associ-ated with the RHP zero, we will steer clear of itand cross over at S kHz. The PWM/power circuitgain at SkHz is:

a problem. One such problem area is the cwrentamplifier in an average cwrent mode control loop.In order to minimize power dissipation in thecwrent sense resistor, it is desirable to use a verysmall resistance value. Although the op-amp inputoffset spec may be low enough to permit a verysmall sense voltage with reasonable accuracy, thesmall sense voltage will require more op-amp gain-bandwidth than nay be available..

Noise filtering: High frequency poles are oftenadded in a control loop to attenuate noise spikesthat might otherwise propagate through the loop,causing spurious turn-on and unpredictable opera-tion. In general the pole frequencies should be atleast 2-3 times Is, to avoid signal distortion andimpaired response to sudden overloads, for exam-pie. This is especially important with conventionalpeak cwrent mode control, which is very noisesensitive, but also sensitive to the effects of wave-form distortion caused by over-ftltering.

References:

[1] R. D. Middlebrook, "Topics in Multiple-LoopRegulators and Current-Mode Programming,"IEEE PESC, June, 1985

momentarily to 4.9V, then return precisely to 5.0V.The output voltage envelope is twice as great withthe capacitor as without it.

So think twice about adding a low frequencyzero just for the sake of DC regulation. If the gainis too low without the boost capacitor, look forways to optimize the loop gain by some othermethod, such as optimizing the compensationscheme.

If a series capacitor is essential, make sure theoutput voltage swing of the op-amp is restricted insome way. Otherwise, the series capacitor cancharge to a large offset voltage during startup orother transient conditions, thus taking a longer timeto recover. If the op-amp output is not internallyclamped. apply an external clamp. A transconduct-ance amplifier is easy to clamp directly across theoutput. Any amplifier can be clamped with a Zenerdiode from output to inverting input. Leave lor 2Volts headroom for AC components riding on thecontrol signal.

DC current offsets: When there is DC resistancebetween op-amp input and output, there will inevi-tably be DC error caused by current flow throughthis resistance. In exercising control throughout thefull range of operating conditions, the op-ampoutput must swing over a range of voltages. Thecurrent offset error is minimized by biasing the OP-amp inputs at a DC voltage exactly in the middle ofthis output voltage range. There will be no currentoffset error when the output is in the middle of thisrange, but there will be .t; regulation error at theoperating extremes.

.For example, if the control IC permits, dividedown the reference voltage applied to the non-inverting op-amp input so that its voltage is at themid-range of the output swing. This is a goodpractice even when a series boost capacitor is used,because the capacitor bias voltage will be close tozero, requiring no time to charge at start-up.

If the op-amp voltage is fIXed internally, considercanceling the mid-range DC offset current byproviding a compensating current to the op-amp

input.Amplifier bandwidth limits: Needless to say, if

the compensation scheme requires more gain athigh frequency than the op-amp can provide, there's

UNITRODE CORPORATION7-10

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