Section 4

Sequential Logic, RTLChapters 3, 6.3

Sequential Logic

● Combinational logic – The output signals are determined by the current state of the input signals.

● Sequential logic – The output signals are determined by the current state of the input signals and the history of the circuit. A sequential circuit has memory.

Sequential Logic

● Consider the following circuit:

Basic SR Latch

● Replace the inverters from the previous slide with NOR gates.

● Write a truth table for the circuit.

Level-Sensitive SR Latch

● Add an extra level of AND gates to provide a control signal.

● The control signal allows the S and R inputs to change without changing the outputs.

D-type Latch

● The output follows the D input while the control signal is high. The latch freezes the output when the control signal goes low.

Edge-Triggered D-type Flip-Flop● Uses a master-slave set of D latches.● The output changes to the value of the D

input only when the Clk input changes from a low to high.

● This is the building block for most digital systems.

Register

● A set of D-type Flip-Flops using a common clock.

● The number of Flip-Flops is the number of bits in the word.

● Used to create a pipeline of operations.

Finite State Machine FSM

● A general FSM has:– Inputs

– Outputs

– Flip-Flops holding the current state

– Combinational logic to create the next state

– Combinational logic for the output

FSM Design

● From a written description draw a state diagram.

● Create the state table (truth table)● Determine the flip-flop inputs for the next

state and output.● Optimize the combinational logic● Draw the circuit

FSM Design

● Two FSM models● Mealy model – The outputs change as the

input changes.● Moore model – The outputs change only on

clock edges.● A more general model could be both.

Mealy Model

● Design a Mealy Model FSM that detects the bit pattern 1010111 (least significant bit first) in a serial bit stream. The bit pattern may appear anywhere in the stream (it can overlap).

Moore Model

● Design a Moore Model FSM that detects the bit pattern 1010111 (least significant bit first) in a serial bit stream. The bit pattern may appear anywhere in the stream (it can overlap).

Specialized Registers

● Useful types of registers– Parallel load

– Shift

– Rotate

– Multifunction

Parallel Load Register

● Adds an additional signal called LOAD● Selects between the current state or the

data in.● Uses a 2-to-1 Mux to select.

Shift Register

● Has a serial in and serial out signal.● The amount of shift depends on the number

of flip-flops.

Rotate Register

● Specialized Shift register where the output is feed back into the input.

● Need a way to initialize the register or select an external input.

Multi-function register

● A register with multiple inputs and operations.

● Controlled by select lines.● Two select lines uses 4-to-1 Muxes.

Counters

● Counters increment (or decrement) the binary value by 1 each clock cycle.

● Use the design procedure to design a 4-bit counter.

● Counters have an extra output signal to indicate the count has reached its terminal count.

● Counters may have a Count Enable input signal.

Modulo Counter

● Design a 4-bit counter that counts to 9 and starts over at 0.

Ripple Counter

● A counter that can divide a clock frequency by 2, 4, 8, etc.

Register Files

● An array of registers.● A register is selected using decoders and

Muxes.● May use Three State Buffers instead of a

Mux.● Acts like an array of memory