8/11/2019 Schober Susan
1/1
This research is funded by DARPA REMIND, USC BMES ERC, and Texas
Instruments/National Semiconductor
Patented with assistance from the USC Stevens Institute for
Innovation
For more information, please contact: [email protected]
Phase-Lock ed Loop s (PLLs) synthesize high-f requency clocks
for radios, processors, and imp lants
PLL output generated by Voltage-Controlled Oscillator
(VCO) or Current-Controlled Oscillator (ICO)
VCO output is compared to a Reference Clock
(usually crystal-based)
Charge Pumps use Phase/Frequency Detector (PFD)
error signals to generate VCO control input
M1
M2
Vdd
UP1
DOWN1
M4
M3
M6
M5
TGATE_UP
TGATE_DOWN
Pinit
Ninit
UP2
UP2
DOWN2
DOWN2
CP_Output
C_LoopFilter
Equivalent
Capacitive Load of
the Loop Filter
C_Pump
Switch_PositveINIT
Switch_NegativeINIT
CMOS Implementation of the Charge Pump
Charge Pump Challenges
PLL Overview
Phase/Frequency
Detector(PFD)
UPChargePump
(CP)DOWN
Loop
Filter(LF)
CP OutputReference Clock
VCO FeedbackClock
Frequency
Divider
VoltageControlled
Oscillator
(VCO)VCO Control
PLL System Diagram
VCO Output
Approach
PFD/CP Performance Summary
PFD/CP Waveforms
PFD/CP Schematics and Layout
VCO Clock Lags
Reference Clock
Up Signal
Down Signal
VCO Control
VCO Clock Leads
Reference Clock
Up Signal
Down Signal
VCO Control
Charge Down Mode
at 28.5MHz
Zoom in of the Charge Up and Down
CP outputs at 28.5MHz for a frequency
error of 10ns (0.1)
This new approach to PLL ChargePump design is based on the
concept of charge transfer in
switched capacitors unlikeconventional current based
designs.
Zoom in of the Charge Up and Down CP
outputs at 28.5MHz for a phase error of
1ns (0.01), and when in phase lock (0
error shown in Green)
Step Size is
8mV for bothCharge Up
and ChargeDown CP
OutputSignals
0 Phase Error CP Output Signal
US Provisional
Patent
# 61/394,908
6 Charge PumpTransistors
Input Buffers
Crystal ReferenceClock
PFD DFF for
Crystal ReferenceClock
4 matched 125fF
Caps in Parallelfor
C_Pump=500fF
Input Buffers VCO
Divided Clock
Outside Dummy
Caps tied toground for
reducing processvariation
Input Buffers
Phase FrequencyDetector
Charge Pump
Charge Up Mode
at 28.5MHz
Fast and accurate response mandatory to minimizePLL dead
zone
and output errors
Switching noise near equilibrium point (frequency
lock) causes undesired VCO jitter
State of the art designs traditionally use current
mirrors which have these pitfalls:
Large area due to many transistors
Current always on: high power (i.e. 0.5-1.5mW)
High sensitivity to process variation
Difficulty switching current sources ON/OFF
Eliminate continuous current consumption
Replace current source with flying capacitor
Changes voltage by transferring charge
Minimize number of active components
Ultra Low Power (e.g. 250pW)
106im provement over conv ent ional CPs
Insensitive to parametric process variations (e.g.threshold
voltage); transistors can also operate in
weak to moderate inversion if desired
Excellent auto-management of VCO control voltage
step size:
C_Pump and C_LoopFilter capacitor size ratio for
large frequency errors
Very precise in reaching phase lock
Extremely low (
