Scan Path Design (1)

7/25/2019 Scan Path Design (1)

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07/03/16Based on text by S. Mourad

"Priciples of Electronic Systes"

Digital Testing: Scan-Path Design


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Outline

Problems with sequential testing

What is scan Types of scan

Types of storage devices

Scan Architectures

Cost of Scan

Partial Scan


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Problems with Sequential Machine Testing

Complexity of testing sequential circuits

due to

feedback loopsplacement of the circuit in a known state

high chance for haard! essential haard

Timing problems


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The Scan-path Technique

Scan!pat desi#nis to reduce test #eneration

coplexity for circuit containin# stora#e de$icesand feedbac% pat &it cobinational lo#ic

'e pilosopy is to di$ide ( con)uer&it te

purpose to *1. Set any internal stateeasily+. ,bser$e any state trou# a distin#uisin#

se)uence


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What is Scan DesignThis "#T technique is used mainly for testable

synchronous circuit

We assume the use of "$%ip$%ops onlyA mux is placed at the input of each %ip$%op

in such a way that all %ip$%ops can be

connected in a shift register for one mux

selection and to work in a normal mode in the

other


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Adding Scan Structure

SFF

SFF

SFF

Combinational

logic

PI PO

SCANOUT

SCANIN

TC or TCK SFFs (scan Flip-flops)

Not shown CK

Connect the S## in a shift register and test

them


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Testing strategyPrincipl! of scan path

&ach input to the

## is considered

an output of the

combinatorialcircuit

each output of the

## is an input to

the circuit


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Testing strategy

Exaple*

- realiation for te double!tro&s&itc

nternal state can be deterined $ia te scan!out

output.


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1. Set c 1 to s&itc te circuit to sift re#isterode

+. ec% operation as a sift re#isterby usin#

scan!in inputs 2 scan!out output and te cloc%3. Set te initial stateof te sift re#ister

. Set c 0 to return to noral ode

4. -pply test input patternto te cobinational lo#ic

6. Set c1 to return to sift re#ister ode7. Sift outte final state &ile settin# te startin#

state for te next test

5. o to step .

'e procedure for circuit testin# *


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Testing the ombinational PartRepeat until all patterns are applied.

' a( Set S& ) *! shift in the initial values on the %ip$%ops(

+These are the signals at the output of thelatches for the ,rst test pattern(-

' b( S& ) .! apply a pattern at the primary inputs(

' c( Clock the circuit once and observe the resultsat the primary outputs(

' d( Clock the circuit / times(

End repeat.


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An !"ample

Clk

Combinational Circuit

l%

7+

71

8

9 :

1

l%

9 :

+

y1

8 ;

y+

616+

63


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#nserting the Mu"es

l%

Combinational Circuit

l%

7 +7

1

8

9 :

1

l%

9 :

+

y1

8 ;

y+

1

0

1

01

0

Scan!in

Scan!out

61 6+ 63


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Types o$ Storage De%ices

/ultiplexed input %ip$%op

Two$port %ip$%op works with twononoverlapping clocks

0atch$based Scan "esign1 requires

2$latches clocked with non$overlapping clocks

3$latch clocked with three phases


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Scan Design ArchitecturesSeveral architectures1/ultiplexed %ip$%ops design

0evel$sensitive scan designScan set scan design

"erivative of scan design1

Parallel scan chainsPartial scan


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&e%el Sensiti%e Scan Design &SSD '#(M)

Scanis ability to sift into or out of any state

-ll internal stora#e is ipleented usin# aard

freepolarity!old s&itces


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&e%el-sensiti%e &atchThe latch works with the 3

phases A! 4 and C

#or normal operation!clocks 4 and C

#or shift operation! clocks

4 and A

Two$port %ip$%op works

with two non$overlapping

clocks


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Polarity *old &atch '#(M)

9


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&SSD design rulesStorage is implemented by haard freepolarity$hold latches

latches controlled by non$overlapping clocksclock inputs to S50s must be easily controlled

clock feeds clock inputs only

all S50 must be connected into shift registers

input sensitiing conditions


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&e%el-Sensiti%e Scan-Design &atch

"

S"

#CK

$

$

" flip-flop

#ast!r latch Sla%! latch

t

SCK

TCK

SCK

#CK

TCK No

rmal

m

o&!

#CK

TCK Scan

mo&!

'ogico%!rh!a&


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&SSD: TestingRepeat until all patterns are applied.a( Apply a pattern at the primary inputs(

b( Clock C6 then clock B once and observe the results at

the primary outputs(c( Shift out the response

Apply the initialiation for the next pattern at S7(

ClockA! then clock B, Mtimes(

8bserve at the primary outputs and the S8 pins(


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Multiple Scan hains7nstead of stringing all the %ip$%ops or thelatches in one shift register

Partition them is several chains

The advantages are1

compatible with multiple clock designs

Shorten test application time

Simplify the stitching of the %ip$%ops

4ut! may require extra pins


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The ost o$ Scan Design

Area +muxes! extra routing-

Additional 798s

Performance! delays within the %ip$%ops

:eat when testing at speed


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Multiple Scan +egisters

Scan flip-flops can be distributed among any number

of shift registers, each having a separate scaninandscanoutpin.

Test sequence length is determined by the longestscan shift register.

Just onetest control

(TC) pin is essential.

SFFSFF

SFF

Combinational

logic

PISCANIN PO

SCANOUT#U

CK

TC


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Scan O%erhead

78 pins1 8ne pin necessary(Area overhead1

Gate overhead) ;< n=9+ng>*.n=-? x *..@!

where ng) comb. gates6 n=) fip-fops6

' &xample

' ng) *..k gates! n=) 2k fip-fops! overhead ) (B@(

/ore accurate estimate must consider scan wiringand layout area(

Performance overhead1/ultiplexer delay added in combinational path6approx( two gate$delays(

#lip$%op output loading due to one additionalfanout6 approx( $@(


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*ierarchical Scan

Scan %ip$%ops are chained withinsubnetworks before chaining subnetworks(

Advantages1' Automatic scan insertion in netlist

' Circuit hierarchy preserved D helps in debugging and

design changes

"isadvantage1 Eon$optimum chip layout(

SFF*

SFF+ SFF,

SFF

SFF,SFF*

SFF+SFF

Scanin Scano.t

Scanin

Scano.t

/i!rarchical n!tlist Flat la0o.t


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Scan Area O%erhead

inear dimensions of active area!

" # (C $ S) % r

"& # (C $ S $ aS) % r

'& # ' $ ry # ' $ '(--b) % T

rea overhead "&'&--"'

# -------------- * ++

"'

--b

# ($as)($ -------) /*++

T

--b

# (as $ ------- )* ++T

y # trac0 dimension, 1ire

1idth$separation

C # total comb. cell 1idth

S # total non-scan 22 cell

1idth

s # fractional 22 cell area # S%(C$S)

a# S22 cell 1idth fractional

increase

r # number of cell ro1s

or routing channels

b# routing fraction in active

area

T # cell height in trac0

dimension y


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!"ample: Scan &ayout

2!...$gate C/8S chip

#ractional area under %ip$%op cells! s ) .(


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ATP, !"ample: S./0Original

+;:9*

*:7

4

4548 ;64,

,


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Automated Scan Design

?!ha%ior; @T'; an& logic"!sign an& %!rification

=at!-l!%!l

n!tlist

Scan &!sign

r.l! a.&its

Combinational

ATP=

Scan har&war!

ins!rtion

Chip la0o.t Scan-

chain optimi1ation;timing %!rification

Scan s!>.!nc!

an& t!st programg!n!ration

"!sign an& t!st

&ata for

man.fact.ring

@.l!

%iolations

Scan

n!tlist

Combinational

%!ctors

Scan chain or&!r

#as2 &ataT!st program

9e$elop desi#n

9e$elop test


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Timing and PowerSmall delays in scan path and clock skewcan cause race condition(

0arge delays in scan path require slowerscan clock(

"ynamic multiplexers1 Skew between TCand TC signals can cause momentary

shorting of " and S" inputs(5andom signal activity in combinationalcircuit during scan can cause excessivepower dissipation(


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Scan Summary

Scan is the most popular "#T technique1' 5ule$based design

' Automated "#T hardware insertion

' Combinational ATPG

Advantages1' "esign automation

' :igh fault coverage6 helpful in diagnosis

' :ierarchical D scan$testable modules are easily combinedinto large scan$testable systems

' /oderate area +H*.@- and speed +H@- overhead"isadvantages1

' 0arge test data volume and long test time

' 4asically a slow speed +"C- test


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O%er%iew: Partial!Scan ( Scan @ariations

"e,nition

Partial-scanarchitecture

Scan %ip$%op selection methods

Cyclic and acyclic structures

Partial$scan by cycle$breaking

Scan variations

can-hold fip-fop+S:##-Summary


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Partial-Scan De$inition

A subset of %ip$%ops is scanned(

8bIectives1/inimie area overhead and scan sequence

length! yet achieve required fault coverage&xclude selected %ip$%ops from scan1' 7mprove performance

' Allow limited scan design rule violations

Allow automation1' 7n scan %ip$%op selection

' 7n test generation

Shorter scan sequences


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Partial-Scan Architecture

FF

FF

SFF

SFF

Combinational

circ.it

PI PO

CK*

CK+ SCANOUT

SCANIN

TC


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What 1 Why Partial Scan DesignTo scan only a subset of the %ip$%opsThe circuit is easier to test by the sequential

ATPG(

The area overhead is minimied(The placement of the %ip$%ops is such that

the interconnects are minimied(

The delays are shortened(


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Partial Scan DesignTo scan only a subset of the %ip$%ops

:ow to select this subsetJ

7t is an EP$complete problem:euristics on graph model to select the

minimum feedback vertex set +/#KS- to

transform the #S/ into an acyclic graph

S 2l 2l S l M h d


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Scan 2lip-2lop Selection Methods

Testability measure based

Lse of SC8AP1 limited success(

Structure based1

Cycle breaking

4alanced structure

'Sometimes requires high scan percentage

ATPG based1Lse of combinational and sequential TG


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ycle (rea3ing

"iMculties in ATPG

S$graph construction and

/#KS problem

Test generation and teststatistics

Partial vs( full scan

Partial$scan %ip$%op


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Di$$iculties in Seq4 ATP,

Poor initialiability(

Poor controllability9observability of statevariables(

Gate count! number of %ip$%ops! and sequentialdepth do not explain the problem(

Cycles are mainly responsible for complexity(An ATPG experiment1

Circ.it N.mb!r of N.mb!r of S!>.!ntial ATP= Fa.lt

gat!s flip-flops &!pth CPU s co%!rag!

T'C ,


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(enchmar3 ircuits

Circuit

34

35

22

6ates

StructureSequential depth

Total faults

7etected faults

3otentially detected faults

8ntestable faults

bandoned faults

2ault coverage ()2ault efficiency ()

9a*. sequence length

Total test vectors

6entest C38 s (Sparc :)

s;

?:;

Cycle-free =

:=:

:@;

+

@

+

;;.> ++.+

@

@@

+

s:@>

=

=

>

?+>

Cycle-free =

@??

:>@

+

A:

+

;=.A ++.+

@

@+>

?

s=>>

>

;

*vectors +dseqis the sequential depth-(

ATPG complexity1 To determine that a fault is

untestable in a cyclic circuit! an ATPG programusing nine$valued logic may have to analyeNE=time$frames! where E=is the number of%ip$%ops in the circuit(


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ycle-2ree !"ample

F*

F+

F,

'!%!l *

+

F*

F+

F,

'!%!l *

+

,

,

&s!> ,

s - graph

Circ.it

All fa.lts ar! t!stabl!5 S!! DBampl! 9565


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A Partial-Scan MethodSelect a minimal set of %ip$%ops forscan to eliminate all cycles(

Alternatively! to keep the overhead lowonly long cycles may be eliminated(

7n some circuits with a large number ofself$loops! all cycles other than self$

loops may be eliminated(


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The M25S Problem#or a directed graph ,nd a set of vertices with

smallest cardinality such that the deletion of thisvertex$set makes the graph acyclic(

The minimum !eedbac" verte# set+/#KS- problemis EP$complete6 practical solutions use heuristics(

A secondary obIective of minimiing the depth of

acyclic graph is useful(

* +

,

< 6',

* +

,

< 6'+

'*

s-graphA 6-flip-flop circ.it


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Test ,eneration

Scan and non$scan %ip$%ops are controlled fromseparate clock P7s1' Eormal mode D 4oth clocks active

' Scan mode D 8nly scan clock active

Seq( ATPG model1' Scan %ip$%ops replaced by P7 and P8

' Seq( ATPG program used for test generation

' Scan register test sequence! ..**..O! of length ns=> 2- ns=> nATPG> < clocks


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Partial Scan !"ample

Circuit1 T0C3 gates

2* %ip$%ops

Scan #aB5 c0cl! "!pth ATP= Fa.lt sim5 Fa.lt ATP= T!st s!>5

flip-flops l!ngth CPU s CPU s co%5 %!ctors l!ngth

4 * *;+: 6* 9754*8 94< 94

Documents

Scan Path Design (1)