EE 577a VLSI DESIGN I

FALL 2013 INSTRUCTOR: M. PEDRAM

FINAL PROJECT PART #1

Submitted by KARTHIK RAMASAMY 5539 4733 38

HARI PRASANTH GOVINDARAJU 4628 8849 28

OBJECTIVE:

The objective of the Part 1 of the project is to design the Adders. It has two parts. Part 1 is the design of

Static adder of choice and part 2 is to design a Dynamic adder.

SPECIFICATION:

24-bit Static Adder.

4-bit Dynamic Adder.

The Inputs and the outputs have to be registered.

All data and clock transition time is 10ps.

All the inputs are unsigned integers.

Vdd = 1.8V

DESIGN DESCRIPTION:

PART 1:

The chosen design for the Adder is the Tree Adders-Ladner Fischer.

The Tree Adder needs the design of the Gray Cell and Black Cells to implement the group PG

logic.

The initial PGs are generated and the final Sum is calculated using the group PG xor initial P.

The inputs and the outputs are registered.

INPUTS /OUTPUTS:

Inputs A[1:24], B[1:24]

Outputs S[1:24]

The Clock signal is used for the registers.

PART 2:

The design for the Dynamic Adders is the design given in the project description.

The design primarily implements the Carry Look-Ahead that generated the carry from which the

Sum is calculated.

The inputs and the outputs are registered.

INPUTS /OUTPUTS:

Inputs A[1:4], B[1:4]

Outputs S[1:4]

The Clock signal is used for the registers.

The phi signal is used as the pre-charge signal for the dynamic logic.

ATTACHMENTS:

PART 1:

Architecture of the 24-bit Adder design.

SCHEMATIC:

Schematic of Black cell.

Schematic of Gray cell.

Schematic of 24-bit Static Adder.

LAYOUT:

Layout of Black cell.

Layout of Gray cell.

Layout of 24-bit Static Adder.

WAVEFORM:

Schematic output.

Extracted output.

Schematic worst-case delay measurement.

Extracted worst-case delay measurement.

PART 2:

SCHEMATIC:

Schematic of P logic.

Schematic of G logic.

Schematic of Dynamic Carry Generation logic.

Schematic of 4-bit Dynamic Adder.

LAYOUT:

Layout of P logic.

Layout of G logic.

Layout of Dynamic Carry Generation logic.

Layout of 4-bit Dynamic Adder.

WAVEFORM:

Schematic output.

Extracted output.

Schematic worst-case delay measurement.

Extracted worst-case delay measurement.

PERFORMANCE METRICS AND LVS REPORT:

PART 1: STATIC ADDER

PERFORMANCE METRICS

Clock Frequency 333.33 MHz

Area 10707.05 Um2

Average Power Consumption 3419 uW

Clock Frequency/Power 0.097 MHz/uW

Clock Frequency/Area 0.0311 MHz/um2

PART 2: DYNAMIC ADDER

PERFORMANCE METRICS

Clock Frequency 1000 MHz

Area 2110.085 Um2

Average Power Consumption 1711 uW

Clock Frequency/Power 0.584MHz/uW

Clock Frequency/Area 0.4739MHz/um2

LVS for 24 bit adder

@(#)$CDS: LVS version 6.1.4-64b 09/21/2011 03:25 (sjfdl054) $

Command line: /usr/local/cadence/IC610/tools.lnx86/dfII/bin/64bit/LVS -dir /home/scf-

04/hgovinda/cds/LVS -l -s -t /home/scf-04/hgovinda/cds/LVS/layout /home/scf-

04/hgovinda/cds/LVS/schematic

Like matching is enabled.

Net swapping is enabled.

Using terminal names as correspondence points.

Compiling Diva LVS rules...

Net-list summary for /home/scf-04/hgovinda/cds/LVS/layout/netlist

count

1697 nets

100 terminals

1692 pmos

1692 nmos

Net-list summary for /home/scf-04/hgovinda/cds/LVS/schematic/netlist

count

1697 nets

100 terminals

1692 pmos

1692 nmos

Terminal correspondence points

N1611 N82 A0

N1609 N63 A1

N1670 N255 A10

N1668 N116 A11

N1667 N254 A12

N1666 N150 A13

N1665 N261 A14

N1663 N149 A15

N1661 N276 A16

N1659 N147 A17

N1657 N275 A18

N1656 N146 A19

N1607 N246 A2

N1655 N274 A20

N1654 N144 A21

N1653 N296 A22

N1652 N143 A23

N1606 N91 A3

N1605 N3 A4

N1604 N89 A5

N1603 N244 A6

N1602 N88 A7

N1600 N256 A8

N1598 N110 A9

N1694 N119 B0

N1692 N316 B1

N1638 N129 B10

N1637 N321 B11

N1634 N130 B12

N1631 N322 B13

N1628 N132 B14

N1625 N323 B15

N1623 N133 B16

N1621 N324 B17

N1619 N135 B18

N1617 N325 B19

N1690 N121 B2

N1614 N138 B20

N1612 N326 B21

N1610 N140 B22

N1608 N327 B23

N1688 N317 B3

N1686 N123 B4

N1684 N318 B5

N1683 N124 B6

N1682 N319 B7

N1681 N127 B8

N1680 N320 B9

N1651 N236 Clock

N1650 N50 Clock_b

N1601 N58 S0

N1599 N10 S1

N1679 N36 S10

N1678 N247 S11

N1677 N40 S12

N1676 N248 S13

N1675 N43 S14

N1674 N234 S15

N1673 N45 S16

N1672 N235 S17

N1671 N41 S18

N1669 N249 S19

N1597 N53 S2

N1664 N44 S20

N1662 N250 S21

N1660 N57 S22

N1658 N251 S23

N1696 N79 S3

N1695 N51 S4

N1693 N81 S5

N1691 N42 S6

N1689 N2 S7

N1687 N46 S8

N1685 N52 S9

N1636 N330 Z0

N1633 N4 Z1

N1648 N70 Z10

N1647 N329 Z11

N1646 N77 Z12

N1645 N8 Z13

N1644 N74 Z14

N1643 N21 Z15

N1642 N117 Z16

N1641 N331 Z17

N1640 N333 Z18

N1639 N9 Z19

N1630 N328 Z2

N1635 N71 Z20

N1632 N78 Z21

N1629 N6 Z22

N1626 N301 Z23

N1627 N5 Z3

N1624 N245 Z4

N1622 N7 Z5

N1620 N332 Z6

N1618 N334 Z7

N1616 N76 Z8

N1615 N80 Z9

N1613 N1 gnd!

N1649 N0 vdd!

Devices in the netlist but not in the rules:

pcapacitor

Devices in the rules but not in the netlist:

cap nfet pfet nmos4 pmos4

The net-lists match.

layout schematic

instances

un-matched 0 0

rewired 0 0

size errors 0 0

pruned 0 0

active 3384 3384

total 3384 3384

nets

un-matched 0 0

merged 0 0

pruned 0 0

active 1697 1697

total 1697 1697

terminals

un-matched 0 0

matched but

different type 4 4

total 100 100

Probe files from /home/scf-04/hgovinda/cds/LVS/schematic

devbad.out:

netbad.out:

mergenet.out:

termbad.out:

prunenet.out:

prunedev.out:

audit.out:

Probe files from /home/scf-04/hgovinda/cds/LVS/layout

devbad.out:

netbad.out:

mergenet.out:

termbad.out:

prunenet.out:

prunedev.out:

audit.out:

hgovinda

Typewritten Text

Layout 24 bit

hgovinda

Typewritten Text

schematic 24 bit

hgovinda

Typewritten Text

grey cell

hgovinda

Typewritten Text

schematic

hgovinda

Typewritten Text

schematic

hgovinda

Typewritten Text

schematic

hgovinda

Typewritten Text

All wave forms for layout

@(#)$CDS: LVS version 6.1.4-64b 09/21/2011 03:25 (sjfdl054) $

Command line: /usr/local/cadence/IC610/tools.lnx86/dfII/bin/64bit/LVS -dir /home/scf-13/kramasam/cds/LVS -l -s -x/home/scf-13/kramasam/cds/LVS/xref.out -t /home/scf-13/kramasam/cds/LVS/layout /home/scf-13/kramasam/cds/LVS/schematic

Like matching is enabled.

Net swapping is enabled.

Creating cross reference file /home/scf-13/kramasam/cds/LVS/xref.out.

Using terminal names as correspondence points.

Compiling Diva LVS rules...

Net-list summary for /home/scf-13/kramasam/cds/LVS/layout/netlist

count

272 nets

21 terminals

265 pmos

271 nmos

Net-list summary for /home/scf-13/kramasam/cds/LVS/schematic/netlist

count

272 nets

21 terminals

265 pmos

271 nmos

Terminal correspondence points

N256 N36 A1

N255 N28 A2

N254 N6 A3

N253 N29 A4

N269 N38 B1

N268 N30 B2

N267 N39 B3

N266 N31 B4

N265 N34 C0

N264 N8 C1

N263 N35 C2

N262 N10 C3

N261 N16 C4

N259 N17 Clock

N252 N15 S1

N251 N33 S2

N271 N3 S3

N270 N32 S4

N257 N1 gnd!

N260 N2 phi

N258 N0 vdd!

Devices in the netlist but not in the rules:

pcapacitor

Devices in the rules but not in the netlist:

cap nfet pfet nmos4 pmos4

The net-lists match.

layout schematic

instances

un-matched 0 0

rewired 0 0

size errors 0 0

pruned 0 0

active 536 536

total 536 536

nets

un-matched 0 0

merged 0 0

pruned 0 0

active 272 272

total 272 272

terminals

un-matched 0 0

matched but

different type 0 0

total 21 21

Probe files from /home/scf-13/kramasam/cds/LVS/schematic

devbad.out:

netbad.out:

mergenet.out:

termbad.out:

prunenet.out:

prunedev.out:

audit.out:

Probe files from /home/scf-13/kramasam/cds/LVS/layout

devbad.out:

netbad.out:

mergenet.out:

termbad.out:

prunenet.out:

prunedev.out:

audit.out:

Area: 41.75 * 50.3 lambda square

Frequency:

Power: 1.492 E-3