SCALABILITY AND RELIABILITY OF PHASE CHANGE MEMORY

A DISSERTATION

SUBMITTED TO THE DEPARTMENT OF ELECTRICAL

ENGINEERING

AND THE COMMITTEE ON GRADUATE STUDIES

OF STANFORD UNIVERSITY

IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE

DEGREE OF

DOCTOR OF PHILOSOPHY

SangBum Kim

Aug 2010

http://creativecommons.org/licenses/by-nc/3.0/us/

This dissertation is online at: http://purl.stanford.edu/kk866zc2173

© 2010 by SangBum Kim. All Rights Reserved.

Re-distributed by Stanford University under license with the author.

This work is licensed under a Creative Commons Attribution-Noncommercial 3.0 United States License.

ii

I certify that I have read this dissertation and that, in my opinion, it is fully adequatein scope and quality as a dissertation for the degree of Doctor of Philosophy.

Philip Wong, Primary Adviser

I certify that I have read this dissertation and that, in my opinion, it is fully adequatein scope and quality as a dissertation for the degree of Doctor of Philosophy.

Yi Cui

I certify that I have read this dissertation and that, in my opinion, it is fully adequatein scope and quality as a dissertation for the degree of Doctor of Philosophy.

Yoshio Nishi

Approved for the Stanford University Committee on Graduate Studies.

Patricia J. Gumport, Vice Provost Graduate Education

This signature page was generated electronically upon submission of this dissertation in electronic format. An original signed hard copy of the signature page is on file inUniversity Archives.

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iv

Abstract

Various memory devices are being widely used for a wide range of applications. There

has not been any universal memory device so far because each memory device has a

unique set of features. Large performance gaps in various dimensions of features

between memory devices and a new set of features required by new electronic systems

such as portable electronics open up new opportunities for new memory devices to

emerge as mainstream memory devices. Besides, the imminent scaling limit for

existing mainstream memory devices also motivates development and research of new

memory devices which can meet the increasing demand for large memory capacity.

Phase change memory (PCM) is one of the most promising emerging memory devices.

It has the potential to combine DRAM-like features such as bit alteration, fast read and

write, and good endurance and Flash-like features such as non-volatility and a simple

structure. PCM is expected to be a highly scalable technology extending beyond

scaling limit of existing memory devices. Prototypical PCM chips have been

developed and are being tested for targeted memory applications. However,

understanding of fundament physics behind PCM operation is still lacking because the

key material in PCM devices, the chalcogenide, is relatively new for use in solid state

devices. Evaluation and development of PCM technology as successful mainstream

memory devices require more study on PCM devices.

This thesis focuses on issues relevant to scalability and reliability of PCM which are

two of the most important qualities that new emerging memory devices should

v

demonstrate. We first study basic scaling rule based on thermoelectric analysis on the

maximum temperature in a PCM cell and show that both isotropic and non-isotropic

scaling result in constant programming voltage. The minimum programming voltage is

determined by material properties such as electrical resistivity and thermal

conductivity regardless of the device size. These results highlight first-order principles

governing scaling rules.

In the first-order scaling rule analysis, we assume that material properties are constant

regardless of its physical size. However, when materials are scaled down to the

nanometer regime, material properties can change because the relative contribution

from the surface property to the overall system property increases compared to that

from the bulk property. We study scaling effect on material property and device

characteristics using a novel device structure – a PCM cell with a pseudo electrode.

With the pseudo electrode PCM cell, we can accurately relate the observed properties

to the amorphous region size. We show that threshold switching voltage scales linearly

with thickness of the amorphous region and threshold switching field drifts in time

after programming. We also show that the drift coefficient for resistance drift stays the

same for scaled devices. These property scaling results provide not only estimates for

scaled device characteristics but also clues for modeling and understanding

mechanisms for threshold switching and drift.

To make scaled memory cells in an array form, not only memory device elements but

also selection devices need to be scaled. PCM requires relatively large programming

current, which makes it challenging to scale down selection devices. We integrate Ge

nanowire diodes as selection devices in search for new candidates for high density

vi

PCM. Ge nanowire diode provides on/off ratio of ~100 and small contact area of 40

nm in diameter which results in programming current below 200 µA. The processing

temperature for Ge nanowire diode is below 400 ºC, which makes Ge nanowire diode

a potential enabler for 3D integration.

As memory devices are scaled down, more serious reliability issues arise. We study

the reliability of PCM using a novel structure – micro-thermal stage (MTS). The high-

resistance-state (RESET) resistance and threshold switching voltage are important

device characteristics for reliable operation of PCM devices. We study the drift

behavior of RESET resistance and threshold switching voltage and its temperature

dependence using the MTS. Results show that the drift coefficient increases

proportionally to annealing temperature until it saturates. The analytical drift model

for time-varying annealing temperature that we derive from existing

phenomenological drift models agrees well with the measurement results. The

analytical drift model can be used to estimate the impact of thermal disturbance

(program disturbance) on RESET resistance and threshold switching voltage.

Thermal disturbance is a unique disturbance mechanism in PCM which is caused by

thermal diffusion from a cell being programmed. The MTS can effectively emulate the

short heat pulse, enabling detailed study on thermal disturbance impact on cell

characteristics. We show that random thermal disturbance can result in at least 25 and

100 % variations in RESET resistance and threshold switching voltage. The existing

model on how to add up the impact of thermal disturbance on crystallization is

experimentally verified using the MTS. Based on measurement and modeling results,

vii

we propose a new programming scheme to improve stability of PCM with a short-time

annealing pulse.

viii

Acknowledgments

The work presented in this dissertation is made possible by eager support from various

people and close and productive collaboration with numerous researchers. I deeply

appreciate the fact that I was able to meet these professors, advisors, colleagues,

friends, and companions while I was pursuing the Ph.D. degree at Stanford University.

First of all, I feel deeply grateful to my academic advisor, Prof. H.-S. Philip Wong for

his support and leadership. He has been guiding me to the right direction to find

answers for complicated problems and provided valuable and essential resources

required for the in-depth research. Especially, he encouraged me and devoted himself

to participate in a multidisciplinary collaborative research. This was extremely

beneficial for research projects on phase change memory, which is the main subject of

this dissertation because the phase change memory research requires a broad range of

knowledge spanning electrical engineering, material science, and thermal physics. I

am very proud of myself for being one of his first seven students since he had

launched the Nanoelectronics group at Stanford University in 2004.

I also would like to acknowledge Prof. Yoshio Nishi for not only being on my

dissertation reading committee but also helping me to begin my research in the

semiconductor device area. During my first summer quarter in Stanford, he generously

allowed me, who had no experience in the device fabrication at the time, to work on

the plasma-activated wafer bonding project, which lead me to learn the nature of

semiconductor research and generated more interest in me to be determined for the

ix

semiconductor device research. Since then, he has been very willing to provide many

valuable ideas and advise on the projects that I worked on.

I would like to thank Prof. Yi Cui and Prof. Kenneth Goodson for enlightening me on

important aspects of phase change memory which were little known to me at the

beginning. Their knowledge and expertise in thermal transport and material science

were crucial for understanding all the details of phase change memory.

I wish to acknowledge the significant contribution and collaboration of various

scientists and researchers on work presented in this dissertation. Dr. Mehdi Asheghi

introduced the importance and usefulness of the micro-thermal stage in the phase

change memory research and provided constructive suggestions in designing the

micro-thermal stage. Dr. Byoung-Jae Bae proposed the novel idea for 1D thickness

scaling study and collaborated on the project. Yuan Zhang collaborated on fabrication

and characterization of the phase change memory cell with a nanowire diode. As the

closest colleague in the same research group, intellectual interaction with her was an

indispensable resource for most of the projects that I worked on. Dr. Fred Hurkx

offered valuable PCM cells for the micro thermal stage fabrication on behalf of NXP

semiconductors and helpful suggestions on the project.

I am grateful to Dr. James McVittie and Dr. Peter Griffin for their help with the

deposition tool and useful suggestions related to the design and fabrication of devices.

I also thank fellow student volunteers, Aaron Gibby, Mihir Tendulkar, Byoungil Lee,

and Wanki Kim for volunteering their time to maintain the critical deposition tool

which enabled many pioneering non-volatile projects.

x

I would like to thank the group of people who worked together on the phase change

project – John Reifenberg, Rakesh Gnana Jeyasingh, Jeaho Lee, Eric Pop, Zijian Lee,

Elah Bozorg-Grayeli, and Lewis Hom. Stefan Meister and Marissa Anne Caldwell

also worked on projects related to phase change memory and interaction with them

always provoked new and novel ideas.

My former and present research group members created a favorable environment

which facilitated my research and made my life at Stanford more memorable. I cherish

the time that I shared with Saeroonter Oh, Li-Wen Chang, Jenny Hu, Lan Wei, Lan

Wei, Soogine Chong, Arash Hazeghi, Jie Deng, Duygu Kuzum, Jiale Liang, Yi Wu,

Shimeng Yu, Kyeongran You, Gael Close, Deji Akinwande, Jason Parker, Helen Chen,

Albert Lin, Cara Beasley, Jie Deng, Crystal Kenny, Kokab Baghbani Parizi, Jieying

Luo, Hong-Yu Chen, Xinyu Bao, Sunae Seo, Ximeng Guan, Gordon Wan, Kerem

Akarvardar, Jeong-Hyong yi, Hae-Taek Kim, Rainer Bruchhaus, Eiji Yoshida, and

Christoph Eggimann.

I would like to give special thanks to Fely Barrera and Miho Nishi, who took care of

all administrative needs in a professional and timely manner.

Most of my research projects were conducted in Stanford Nanofabrication Facility

(SNF). I would like to thank all of SNF staff members and colleagues who supported

SNF and kindly shared their ideas to solve any fabrication issues that I had. Special

thanks are due to Dr. Ed Meyers who actively helped me for my first project in SNF.

I would like to acknowledge various funding sources for tuition, stipends, and projects

including the Korea Foundation for Advanced Studies (KFAS), the Samsung

Scholarship, NXP semiconductors, the National Science Foundation, the Global

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Research Collaboration (GRC) of the Semiconductor Research Corporation (SRC), the

member companies of the Stanford Non-Volatile Memory Technology Research

Initiative (NMTRI), and the MSD Focus Center, one of six research centers funded

under the Focus Center Research Program (FCRP), a Semiconductor Research

Corporation entity, and Intel Corporation.

I am truly indebted to my loving parents for everything I achieved. They showed me

what a true unconditional love is and nourished a small boy to become an engineer

who loves what he does.

During my Ph.D., I was lucky enough to find the true love of my life, Suon Choi. Her

love and support helped and motivated me to get through all difficulties in completing

all of requirements for Ph.D. I enjoy sharing my research and engineering experience

with my wife. I dedicate this dissertation to my beloved lovely wife, Suon.

xii

Contents

Chapter 1 Introduction ................................................................................................ 1

1.1 Motivation ........................................................................................................ 1

1.2 Basic Operation and Scaling Limits of Various Memory Technologies ......... 5

1.2.1 Floating Gate Memory ........................................................................... 5

1.2.2 Charge-Trapping Memory ...................................................................... 6

1.2.3 Nanocrystal Memory .............................................................................. 7

1.2.4 Phase Change Memory ........................................................................... 7

1.2.5 Ferroelectric Random Access Memory (FRAM) ................................... 9

1.2.6 Magnetic Random Access Memory (MRAM) ..................................... 10

1.2.7 Resistance Change Memory (RRAM) .................................................. 11

1.2.8 Summary ............................................................................................... 11

1.3 Phase Change Memory .................................................................................. 12

1.3.1 Device Structure and Basic Operation ................................................. 12

1.3.2 Threshold Switching ............................................................................. 14

1.3.3 Scalability – Selection Device and Material Property Scaling ............. 16

1.3.4 Reliability – Retention, Thermal Disturbance, and Resistance Drift

(Multi-Bit) .............................................................................................................. 18

1.4 Thesis Overview ............................................................................................ 20

Bibliography ................................................................................................................. 23

xiii

Chapter 2 Analysis of Temperature in Phase Change Memory Scaling .................. 35

2.1 Introduction .................................................................................................... 35

2.2 Scaling Rule Requirement and General Assumptions ................................... 35

2.3 Constant-Voltage Isotropic Scaling and Proximity Disturbance ................... 36

2.4 Constant-Voltage Non-Isotropic Scaling and Minimum Programming

Voltage ...................................................................................................................... 38

2.5 Conclusion ..................................................................................................... 43

Bibliography ................................................................................................................. 44

Chapter 3 Integrating Phase Change Memory Cell with Ge Nanowire Didoe for

Cross-Point Memory – Experimental Demonstration and Analysis ............................ 46

3.1 Introduction .................................................................................................... 46

3.2 Device Fabrication ......................................................................................... 48

3.3 Germanium Nanowire Diode Selection Device ............................................. 50

3.3.1 Germanium Nanowire Synthesis .......................................................... 50

3.3.2 Germanium Nanowire Diode Characteristic ........................................ 51

3.4 Phase Change Memory Cell Characteristics .................................................. 52

3.5 Discussion ...................................................................................................... 58

3.6 Conclusion ..................................................................................................... 61

Bibliography ................................................................................................................. 62

Chapter 4 1D Thickness Scaling Study of Phase Change Material (Ge2Sb2Te5) using

a Pseudo 3-Terminal Device ........................................................................................ 66

4.1 Introduction .................................................................................................... 66

4.2 Device Operation ........................................................................................... 68

xiv

4.3 Threshold Switching Voltage ........................................................................ 72

4.4 RESET Resistance Drift ................................................................................ 77

4.5 Crystallization Temperature .......................................................................... 78

4.6 Conclusions .................................................................................................... 80

Bibliography ................................................................................................................. 82

Chapter 5 Resistance and Threshold Switching Voltage Drift Behavior in Phase-

Change Memory and Their Temperature Dependence at Microsecond Time Scales .. 87

5.1 Introduction .................................................................................................... 87

5.2 The Drift Model and its Temperature Dependence ....................................... 89

5.3 Micro-Thermal Stage (MTS) ......................................................................... 92

5.4 Experimental Results and Discussion ............................................................ 97

5.4.1 RESET Resistance Drift for Constant Annealing Temperature ........... 98

5.4.2 RESET Resistance Drift for Time-Varying Annealing Temperature 100

5.4.3 Threshold Switching Voltage Drift and Temperature Dependence ... 107

5.5 The Drift Model Comparison ...................................................................... 108

5.6 Conclusion ................................................................................................... 109

Bibliography ............................................................................................................... 111

Chapter 6 Thermal Disturbance and its Impact on Reliability of Phase-Change

Memory Studied by the Micro-Thermal Stage ........................................................... 115

6.1 Introduction .................................................................................................. 115

6.2 Micro-Thermal Stage ................................................................................... 116

6.3 Experimental Results ................................................................................... 118

xv

6.3.1 Crystallization Time ........................................................................... 118

6.3.2 RESET Resistance and Threshold Switching Voltage Drift .............. 122

6.3.3 Multi-Bit Operation ............................................................................ 127

6.4 Conclusion ................................................................................................... 128

Bibliography ............................................................................................................... 129

Chapter 7 Conclusion ............................................................................................. 131

7.1 Summary of Contributions ........................................................................... 131

7.2 Recommendations for future work .............................................................. 133

7.2.1 Toward 3D Integration of PCM cells with Ge Nanowire Diodes as

Selection Devices ................................................................................................. 133

7.2.2 Modeling the Drift Behavior of RESET Resistance and Threshold

Switching Voltage Based on New Findings of its Thickness Dependence ......... 134

7.2.3 Statistical Analysis on Drift Behavior ................................................ 134

7.2.4 Thermal Disturbance Effect on the Array and Chip level .................. 135

Appendix A Pulse Measurement Design ................................................................. 136

A.1. Theoretical Background ............................................................................... 136

A.2. Pulse Test Setup Design .............................................................................. 139

A.3. Resistance Measurement of the RESET State Using Short Time Pulse ...... 141

List of Publications ..................................................................................................... 143

Author’s Biography .................................................................................................... 147

xvi

List of Tables

Table 1-1: Characteristics of memory devices for electronic systems.. ......................... 2

Table 2-1: Constant-voltage isotropic scaling rule for PCM ........................................ 37

xvii

List of Figures

Figure 1-1: Basic cell structures of (a) floating gate memory, (b) charge-trapping

memory, and (C) nanocrystal memory. .......................................................................... 4

Figure 1-2: Atomic strucuture of ferroelectric material characteristics. ........................ 9

Figure 1-3: A basic cell structure of MRAM. .............................................................. 10

Figure 1-4: (a) The cross-section schematic of the conventional phase change memory

cell. (b) PCM cells are programmed and read by applying electrical pulses which

change temperature accordingly. .................................................................................. 12

Figure 1-5: I-V characteristics of SET and RESET states. ......................................... 13

Figure 1-6: Conductivity in the amorphous and crystalline phase of Ge2Sb2Te5 as a

function of time. ........................................................................................................... 19

Figure 2-1: A general memory-cell structure between two boundaries, bd1 and bd2. .. 38

Figure 2-2: Typical PCM structures : structure A and B. The only difference between

A and B is the material for the cylinder which connects top GST and bottom heater

layer. ............................................................................................................................. 39

Figure 2-3: Analytical calculation result with applied voltage of 1V. Temperature

profile along the memory cell for different aspect ratios, s, defined as L/r1. for (a)

structure A and (b) structure B in Figure 2-2. .............................................................. 40

Figure 2-4: ANSYS simulation result with applied voltage of 1V (a) structure A and

(b) structure B. The insets show example image outputs for ANSYS simulation. ...... 42

Figure 3-1: Process flow of device fabrication. ............................................................ 48

xviii

Figure 3-2: A cross-section SEM of Ge nanowires grown from 40nm Au colloid

catalyst (a) without doping; (b) with phosphorus in-situ doping. ................................ 50

Figure 3-3: (a) Schematic test structure for GeNW hetero-junction. (b) IV sweep

characteristics of GeNW diode with different sizes of Au catalyst. The inset figure

magnifies the reverse bias region. ................................................................................ 51

Figure 3-4: IV characteristics of 2µm by 2µm size Au catalyst. The inset figure shows

IV characteristics near turn-on voltage. ........................................................................ 52

Figure 3-5: Current sweep IV characteristics of GeNW PCM cells. ........................... 54

Figure 3-6: Current sweep IV characteristics of the SET and RESET programmed

GeNW PCM cell. .......................................................................................................... 55

Figure 3-7: Circuit simulation results as a function of number of GeNW PCM memory

cells in an array. ............................................................................................................ 56

Figure 3-8: Pulse programming setup. ......................................................................... 58

Figure 3-9: (a) Resistance measured at 3V after each SET/RESET programming. (b)

The pulse is shorter than (a). The pulse width/amplitude is 50ns/8.5V for RESET and

200ns/5.5V for SET. ..................................................................................................... 59

Figure 3-10: Thermoelectric simulation results for temperature rise from 2D axis-

symmetric GeNW PCM cell. (a) shows sample simulation result. (b) shows simulation

results for germanium conductivity (σGe) from 25 to 500 Ω-1cm-1. (c) shows simulation

results as a function of the GeNW height. .................................................................... 60

xix

Figure 4-1: Schematics of (a) a typical T-shape PCM cell and (b) a pseudo 3-terminal

device with an additional top electrode (ATE) layer inserted into Ge2Sb2Te5 (GST)

layer. ............................................................................................................................. 67

Figure 4-2: Schematics of the RESET state of the pseudo 3-terminal device. ............. 68

Figure 4-3: Finite element modeling (FEM) simulation results on the RESET

operation for devices with (a) 6 nm-thick TiN ATE, (b) 6 nm-thick W ATE and (c)

their temperature profile along the center line. ............................................................ 70

Figure 4-4: RESET state current-sweep I-V curves of (a) T-shape and (b) pseudo 3-

terminal devices for various RESET voltages (VRESET). ............................................... 71

Figure 4-5: A cross-sectional TEM image of device with 6 nm-thick GST1 layer. .... 72

Figure 4-6: Resistance-power (R-P) curve for various GST1 thicknesses (dGST1). ...... 73

Figure 4-7: (a) Current sweep I-V curves and (b) Vth for varying GST1 thickness (6 –

23nm). ........................................................................................................................... 74

Figure 4-8: (a) Vth vs GST1 thickness (dGST1) for various sleep times between 100 µs

and 10 s. (b) Threshold switching field (Eth) and extrapolated Vth (Vth0) at dGST1=0 as a

function of sleep time. .................................................................................................. 75

Figure 4-9: Current-sweep I-V curves of device with 6 nm-thick GST1 layer for

varying temperature. ..................................................................................................... 76

Figure 4-10: Bi-logarithmic plot of (a) resistance and (b) normalized resistance ratio as

a function of time for varying GST1 thickness. ........................................................... 77

Figure 4-11: Dependence of resistance on temperature for varying GST1 thickness. 80

xx

Figure 5-1: Microscope image of micro-thermal stage (MTS). The inset 3D figure

shows the Pt heater overlapped region over narrow phase change material

programmed region. ..................................................................................................... 92

Figure 5-2: Micro-thermal stage (MTS) extends temperature control down to

microsecond time scale or below which is not accessible by conventional thermal

stages with large thermal time constants. ..................................................................... 93

Figure 5-3: The resistance of the Pt heater increases linearly as temperature increases.

...................................................................................................................................... 94

Figure 5-4: Electrical pulse and temperature profile for RRESET drift measurement. .... 97

Figure 5-5: (a) RESET resistance as a function of time after RESET programming for

various annealing temperatures (TA). (b) RRESET drift coefficient calculated from the

data in (a). ..................................................................................................................... 99

Figure 5-6: Schematic diagram for derivation of (6) .................................................. 101

Figure 5-7: Electrical pulse and temperature profile for RRESET drift measurement. .. 102

Figure 5-8: (a) RRESET(t) for various delay time for annealing (dA). (b) The percentage

difference of RRESET(t) with respect to RRESET(t) without any annealing. (c) RRESET drift

coefficient calculated from (a). (d) The estimation based on (7) agrees well with

measurement results. .................................................................................................. 104

Figure 5-9: Electrical pulse and temperature profile for Vth drift measurement. ........ 106

Figure 5-10: (a) Vth(t) for various annealing temperatures (TA). (b) Vth drift coefficient

as a function of TA calculated from (a). ...................................................................... 107

Figure 6-1: Microscope image of the micro-thermal stage (MTS). The inset figure

shows the MTS heater overlapped region over PCM programming region. .............. 116

xxi

Figure 6-2: Number of crystallization steps varies between 1 to several. .................. 118

Figure 6-3: Schematic crystallization process for growth dominated material. ......... 119

Figure 6-4: Crystallization time (tcrys) with and without thermal disturbance (TD). .. 120

Figure 6-5: Crystallization time dependence on read bias between 0.1 and 0.4 V. ... 121

Figure 6-6: Pulse input profiles for the phase-change memory cell (top) and micro-

thermal stage heater (bottom). .................................................................................... 122

Figure 6-7: (a) RESET resistance (RRESET) and (b) drift coefficient (γ) for the same

amount of annealing (60 °C for 600 µs) with different delay times for annealing..... 123

Figure 6-8: Threshold switching voltage (Vth) drift dependence on annealing

temperature (TA). ........................................................................................................ 124

Figure 6-9: Threshold switching voltage (Vth) dependence on reading temperature (TR)

for various delay time for read. .................................................................................. 126

Figure 6-10: Larger resistance margin is achieved by annealing the cell. ................. 128

Figure A-1: (a) Typical PCM memory testing setup with one pulse generator. (b) PCM

memory testing setup with two pulse generators. (c) PCM memory testing setup with

one pulse generator and one oscilloscope. ................................................................. 139

Figure A-2: (a) A PCM memory cell with added resistor connected in series with PCM.

(b) A PCM memory cell connected to the virtual ground node of the current-to-voltage

amplifier. The effect of the parasitic capacitor on the quenching time is minimized. 141

1

Chapter 1

Introduction

1.1 Motivation

Memory devices are widely used in electronic systems for multiple purposes. Some

memory devices are used as a cache memory to store data for temporal use during

logic operation while others are used as a storage class memory to store data for long-

term usage. Each purpose demand different requirements for memory devices. For

example, fast write and read speed is required for cache memory devices while low

cost per bit and long retention are required for storage class memory devices. There

has been no single type of memory device which could satisfy various requirements

needed for multiple applications. Therefore, various types of memory devices which

satisfy requirements of specific application are developed and currently being used in

electronic systems.

Complex electronic systems such as personal computers and smart phones use various

types of memory devices in the memory hierarchy to optimize the performance of the

system. Memory devices with fast read/write speed and relatively high cost per bit

such as Static Random Access Memory (SRAM) and Dynamic Random Access

Memory (DRAM) occupy the top of the memory hierarchy while memory devices

with low cost per bit and non-volatility such as NAND Flash and Hard Disk Drives

(HDD) occupy the bottom of the memory hierarchy. Using multiple types of memory

devices in a single system adds complexity to the system design and additional cost.

2

Therefore, there has been incessant interest in finding a “universal memory” which

can outperform and replace all or most of memory devices in the electronic systems

today.

Table 1-1: Characteristics of memory devices for electronic systems [1]. Shaded cell are

referenced from [2].

Baseline Technologies Prototypical Technologies / Research Floating Gate SRAM DRAM NOR NAND HDD Charge

Trapping PCM FRAM MRAM RRAM

Feature Size (nm)

65 50 90 90 NA 50 65 180 130 NA

Cell area 140F2 6F2 10F2 5F2 (2/3)F2 (6-7)F2 16F2 22F2 45F2 6F2 Density NA 8Gb

/chip NA 64Gb

/chip 400Gb

/in2 NA 512Mb/

chip 128Mb/

chip 32Mb /chip

64Kb /chip

Read Time

0.3ns <10ns 10ns 50ns 8.5ms 14ns 60ns 45ns 20ns 20ns

Access Time (W/E)

0.3ns <10ns 1µs /10ms

1 /0.1ms

9.5ms 20µs /20ms

50 /120ns

10ns 20ns 10ns

Endurance >1E16 >1E16 >1E5 >1E5 NA >1E5 1E9 >1E16 >1E16 106 Retention NA 64ms >10yr >10yr NA >10yr >10yr >10yr >10yr 10yr

Write Energy (J/bit)

7E-16 5E-15 >1E-14 >1E-14 NA 1E-13 6E-12 3E-14 1.5E-10 2pJ

Multibit potential

No No Y Y No Y Y No Y Y

However, the dream of finding a “universal memory” seems quite far away from

reality because there are large performance gaps between various memory devices in

use today as can be seen from Table 1-1 which summarizes characteristics of various

memory devices. For example, the memory density of HDD is almost 200 times larger

than that of SRAM. On the other hand, the read/write access time of SRAM is almost

107 times faster than that of HDD. Therefore, a “universal memory” seems to be too

good to be true at this stage. Nevertheless, there has been continuous search for new

type of memory devices because such a large gap in memory device performance

3

opens possibility for another optimization point. A new successful memory device will

either combine a unique set of superior performances or outperform at least one

specific memory type.

Another reason why new memory devices are widely researched is because it is

becoming very difficult to improve the performance and density of current prevailing

memory devices. For decades, the feature size of solid state memory devices has been

continuously shrinking as a result of advancement of lithography technology as

predicted by Moore’s law. The shrinking memory device size not only increases the

memory density but also tends to improve performance of memory devices such as

read/write speed and power consumption. However, memory devices are facing or

very close to the scaling limit where these memory devices can no longer operate

reliably if it is scaled further. Therefore, a new memory technology which can be

further scaled down to smaller features size has a great potential to become a dominant

memory device in the future.

Many interesting new ideas which can be applied to new memory devices have been

proposed and widely researched. These include trapping charge memory, Ferroelectric

Random Access Memory (FeRAM), Magnetic Random Access Memory (MRAM),

Phase Change Memory (PCM), Spin Torque Transfer Magnetic Random Access

Memory (STTMRAM), Resistance Change Random Access Memory (RRAM),

Conductive Bridge Random Access Memory (CBRAM) and etc. Most of them

promises some improvements over current memory technologies among which the

scalability is one of the most important. However, successful development of these

new technologies into mainstream memory devices requires these technologies to be

4

highly reliable to the extent that each memory cell can work within a certain

specification so that hundred-millions or more of them can work as a single memory

chip. The reliability of the new memory technologies is seldom obvious from its basic

operating principle, thus more in-depth study on the reliability of each memory

technology is required.

This thesis focuses on the study of phase change memory (PCM) which is one of the

most promising emerging memory technologies. PCM has a combination of features

that are interesting for new application [3]. PCM is expected to be highly scalable

without any currently identified insurmountable scaling limitation. Large scale

integration of PCM has been demonstrated [4, 5] while further-scaled PCM is already

in the development stage [6]. This thesis identifies and addresses some of unanswered

questions relevant to scalability and reliability of PCM using theoretical analysis and

experimental demonstration and characterization from specially designed structures.

Fig. 1-1 Basic cell structures of (a) floating gate memory, (b) charge-trapping memory, and (C)

nanocrystal memory.

Figure 1-1: Basic cell structures of (a) floating gate memory, (b) charge-trapping memory, and

(C) nanocrystal memory.

5

1.2 Basic Operation and Scaling Limits of Various Memory

Technologies

In this section, the basic operation and scaling challenges of existing and emerging

memory devices will be reviewed.

1.2.1 Floating Gate Memory

Floating gate memory stores charges at the floating gate which is electrically insulated

by insulators – tunnel oxide and interpoly oxide-nitride-oxide (ONO). The schematic

structure of floating gate memory is shown in Figure 1-1(a). Charges are pushed into

or pulled out of the floating gate, by either carrier tunneling in high electric field

across the tunnel oxide or hot electron generation in the Si channel so that they have

large enough energy to overcome the energy barrier of tunnel oxide. The advantage of

floating gate memory is that its simple layout pattern allows not only small cell sizes

in terms of F2, where F is the minimum lithographic feature size but also small F

which results in low cost per pit. Multi-level capability which is achieved by

controlled by number of charges stored in the floating gate further decreases cost per

bit. As a result, NAND floating gate memory has achieved the highest density among

mainstream solid state memory devices. However, floating gate memory is facing

more difficult scaling challenges. Floating gate memory is charge storage type

memory and further scaling of the transistor gate size will decrease the number of

charges in the floating gate [7]. Therefore, for given amount of leakage current the

retention time of stored charges or data will decrease as well. This is more serious for

multi-level cells because the difference in the number of charges stored in each level

6

will be even smaller than that of single-level cells. There are other scaling challenges

specific to each floating gate memory type as well. Specifically, in NOR type floating

gate memory, scaling the channel length is challenging because the tunnel oxide is

unlikely to be scaled below 8-9 nm due to reliability requirement [8]. In addition, the

theoretical drain voltage limit set by the fixed barrier height between tunnel oxide and

the channel is higher than the junction breakdown voltage and the drain disturbance

voltage limit at short channel length [9 ]. In NAND type floating gate memory,

threshold voltage change due to capacitive coupling between adjacent floating gates

will make scaling difficult [9].

1.2.2 Charge-Trapping Memory

The main difference between charge-trapping memory and floating gate memory is

that the charges are stored at charge traps in the nitride film of the charge-trapping

memory cell (Figure 1-1(b)) instead of the floating polysilicon gate of the floating gate

memory cell. One of the most representative gate stacks of charge trapping memory

consists of silicon-oxide-nitride-oxide-silicon, which the name ‘SONOS’ came from.

Since the charges are stored in discrete traps rather than within a conducting film,

charge-trapping memory does not lose all the stored charges even when leakage path

in the tunneling oxide is formed due to stress. Therefore, charge-trapping memory can

have a thinner tunneling oxide than floating gate memory. These characteristics allows

to achieve better endurance, and low voltage operation [10]. With improvement of

retention time and erase speed [11], charge-trapping memory is expected to be further

scaled beyond floating gate memory. Electrically insulated traps along the gate can be

7

utilized to localize stored charges within one cell, which can provide multi-bit

functionality by changing the programming current direction. This can be combined

with multi-level which is common in floating gate to increase the density even further.

However, charge-trapping memory can still suffer from decreasing number of stored

charges as it is scaled down.

1.2.3 Nanocrystal Memory

Nanocrystal memory [12] is also a variation of floating gate memories. Nanocrystals

instead of the floating gate store charges in a floating-gate-memory like structure

(Figure 1-1(c)). By controlling the density of nanocrystals, stored charges in the

nanocrystals can be isolated from each other [13], which makes it possible to use

thinner tunnel oxide and lower programming voltage than a floating gate memory for

the same reason explained in SONOS. Therefore, ideally nanocrystal memory is

expected to be more scalable than floating gate memory. However, due to charge

blockade effect which will raise the energy level of stored charges, retention can be

degraded. Major challenge of nanocrystal memory scaling is controlling the

distribution of nanocrystal size and achieving high enough nanocrystal density for

nanoscale device sizes [14].

1.2.4 Phase Change Memory

Phase change memory (PCM) changes the phase of the material between crystalline

and amorphous phase by using heat generated from Joule heating. The crystalline and

amorphous phases have orders-of-magnitude difference in electrical resistivity at low

electric field and the state of PCM cell can be read by measuring its resistance. The

8

phase changing material, GeTe, nanoparticle as small as 1.8 nm has been shown to be

stable in two phases [15] suggesting its scalability. PCM can be programmed at low

voltages around 3V and programming speed is faster than that of float-gate memory

[1] since the thermal time constant of the cell and crystallization time of the typical

phase change material such as Ge2Sb2Te5 is less than few hundred nanoseconds.

Endurance as high as 1012 cycles has been demonstrated [16]. PCM cells can be

integrated with 2 terminal vertical diodes or vertical bipolar junction transistor instead

of planar MOSFET transistors to achieve high-density cross-point memory [17].

However, PCM requires sizable programming current which makes it difficult to scale

the size of the selection device. Increasing memory cell density can lead to increasing

thermal disturbance effect which is caused by temperature rise in the adjacent cells

during programming of the selected cell. The accumulated effect of temperature rise

can result in a retention failure by crystallizing the amorphous region [18]. Other

scalability and reliability issues that need to be overcome include compositional

instability of phase changing material [19] and resistance drift phenomenon [20]. The

resistance drift makes it difficult to design multi-level phase change memory cell for

lower cost per bit.

9

1.2.5 Ferroelectric Random Access Memory (FRAM)

FRAM stores data by changing the position of an atom in ferroelectric material, which

results in different electric dipole directions that can be sensed electrically (Figure 1-1)

[21]. Capacitor with ferroelectric material inside will conduct displacement currents

only when atoms move according to the external electric field. The advantage of

FRAM over floating memories includes low voltage read/write, fast write/erase, and

better endurance. However, it is unclear whether FRAM can be scaled because scaling

the area of ferroelectric capacitor decrease the signal intensity. In this sense, FRAM is

facing similar scaling challenges as DRAM because both of them are 1-transistor-1-

capacitor structure. Adopting the same ideas from DRAM, FRAM should have 3D

Figure 1-2: Atomic structure of ferroelectric material characteristics. The center atom is moved

according the applied electric field and its movement can be sensed by displacement current due

to charge spike [21].

10

capacitor structures to increase overall capacitance per cell while maintaining small

planar area to continue scaling [22].

1.2.6 Magnetic Random Access Memory (MRAM)

MRAM stores data by changing relative anisotropy directions of two ferromagnetic

layers separated by a thin tunnel barrier layer (Figure 1-3) [23]. The resistance of this

magnetic tunnel junction (MTJ) is small when two directions are parallel and large

when two directions are anti-parallel. The advantage of MRAM is its fast reading and

programming time in tens of nanoseconds, low operating voltage, endurance larger

than 1015, and good retention characteristics. However, large programming current and

power per bit is required and the cell size is relatively large compared to other memory

cells. In terms of scaling, MRAM requires large peripheral circuitry to sense relatively

small resistance different between parallel and anti-parallel states. In addition, MTJ

switching field is inversely proportional to the MTJ size [9]. Spin torque transfer

Figure 1-3: A basic cell structure of MRAM [23]. Write word

line is required to program MTJ with magnetic field.

11

MRAM (STTMRAM) in early research stage is an advanced version of MRAM with

different writing method. Direct current-driven magnetization [24, 25] in STTRAM is

expected to make it possible to decrease the programming current substantially and to

continue scaling of magnetic random access memory.

1.2.7 Resistance Change Memory (RRAM)

These types of memory include various memory material and mechanisms but they

show resistance switch between low and high resistance states by applying voltage,

current, and power. These resistance switching behaviors are typically observed from

metal-insulator-metal (MIM) structures. Many insulators have been reported to show

resistance switching behavior including NiO [26], TiO2 [26], PCMO - (Pr,Ca)MnO3

[27], and STO - SrTiO3:Cr [28, 29]. According to 2007 ITRS emerging research

device section, various mechanisms are responsible for resistance change in these

materials such as thermally induced formation and resolution of a conductive filament

and ion migration combined with redox processes. Memories in this category are in an

early stage of research. Therefore, it is too early to conclude whether these memories

can become mainstream memory devices. However, early research results show that

these have a strong potential to be low voltage and power operable and highly scalable.

1.2.8 Summary

Various current and emerging memory technologies are facing unique challenges for

future performance improvement and scaling. Therefore, no fair comparison about

their future performances and wide adoption in the memory market can be made

simply based on their basic operating principles. The demonstration of the prototypical

12

advanced products is a fair indication that the specific memory technology is ready for

thorough investigation with enough details on its characteristics. It has been reported

that 45 nm 1Gb Phase change memory (PCM) is in the development stage [6] with

prototypical products in smaller capacity. In next chapter, more details on PCM

characteristics will be reviewed.

1.3 Phase Change Memory

1.3.1 Device Structure and Basic Operation

Figure 1-4(a) shows one common phase change memory (PCM) cell structure. PCM

utilizes the large resistivity contrast between crystalline (low resistivity) and

amorphous (high resistivity) phases of the phase change material. There are various

kinds of phase change material. Most of them are chalcogenide compound and

Figure 1-4: (a) The cross-section schematic of the conventional phase

change memory cell. The electrical current passes through the phase

change material between the top electrode and heater. Current crowding

at the “heater” to phase change material contact results in a programmed

region illustrated by the mushroom boundary. This is typically referred to

as the mushroom cell. (b) PCM cells are programmed and read by

applying electrical pulses which change temperature accordingly.

13

Ge2Sb2Te5 is one of the most commonly used phase change material in PCM. SET and

RESET state of PCM refers to low and high resistance state respectively. To RESET-

program the PCM cell into the amorphous phase, the programming region is first melt

and then quenched by applying large electrical current pulse for a short time period.

Doing so leaves a region of amorphous, highly resistive material in the PCM cell. To

SET-program the PCM cell into the crystalline phase, medium electrical current pulse

is applied to anneal the programming region at temperature between crystallization

temperature and melting temperature for a time period long enough to crystallize. To

read the state of the programming region, the resistance of the cell is measured by

passing an electrical current small enough not to disturb the current state. The

schematic pulse shapes are summarized in Figure 1-4(b).

RESET programming consumes the largest power since the cell needs to reach

melting temperature. RESET current is determined by various material properties such

Figure 1-5: I-V characteristics of SET and RESET states [30].

The RESET state shows switching behavior at threshold

switching voltage (Vth).

14

as melting temperature, resistivity, and thermal conductivity. In general, the operating

speed of PCM is limited by SET programming time because it takes finite time to fully

crystallize the amorphous region.

Figure 1-5 shows current-voltage (I-V) curves of the SET and RESET states [30]. The

SET and RESET states have large resistance contrast for voltages below the threshold

switching voltage (Vth). The RESET state is in the high resistance state below Vth (sub-

threshold region) and shows electronic threshold switching behavior at Vth, i.e. a

negative differential resistance. This is reversible if the voltage pulse is removed very

quickly, but if the voltage is applied for longer than the crystallization time it leads to

memory switching as well and the cell is in the low resistance state after an applied

voltage larger than Vth.

1.3.2 Threshold Switching

The SET programming process critically depends on the threshold switching behavior.

When the electric field across the amorphous region reaches a threshold value, the

resistance of the amorphous region goes into a lower resistance state (known as the

dynamic on-state) which has resistivity that is comparable to the crystalline state. This

electronic threshold switching phenomenon is the key to successful SET programming

of the PCM. When the PCM is in the RESET state, the resistance of the PCM cell is

too high to conduct enough current to provide Joule heating to crystallize the PCM

cell. The electronic threshold switching effect lowers the resistance of the RESET

state and enables SET programming.

15

Vth needs to be well characterized to properly operate PCM cells. The read voltage

should be well below Vth to avoid disrupting current state and to have large enough

read margin between SET and RESET state. Therefore, too small Vth can lead to

unreliable and slow read operation. On the other hand, programming pulse should be

able to provide voltage that is larger than Vth to successfully SET program PCM cell

from the RESET state. Vth is not necessarily smaller than SET and RESET

programming voltages because Vth is dependent on the amorphous regions size [31, 32,

33 ] while SET and RESET programming voltages are determined by thermal

efficiency of the PCM cell. Therefore, too large Vth can increase the maximum voltage

required by PCM device.

Even though threshold switching is an important phenomenon in PCM operation, the

physics of threshold switching is not fully understood and several models have been

suggested as a possible mechanism. The thermal instability model attributes threshold

switching to thermal runaway caused by Joule heating [34]. This model is based on a

simple observation that the current through the phase change material increases

exponentially due to temperature-dependent conductivity of the phase change material

as temperature increases. Considering that typical threshold switching speed is faster

than the thermal time constant, electronic mechanisms are favored over purely thermal

mechanisms [35]. An electronic model attributes threshold switching to strong carrier

generation caused by high electric field and large carrier density [36, 37, 38]. In

another electronic model, the threshold switching is attributed to energy gain of

electrons in a high electric field leading to a voltage-current instability [39].

16

The crystallization model attributes threshold switching to the actual crystallization

based on a nucleation model in which the nucleation is facilitated by the electric field

[40]. Reversible characteristic of threshold switching is explained by dissolution of

premature crystalline embryos upon removal of the electric field. Detailed

experimental validation of these models is further required because the internal

parameters of the models cannot be precisely determined. The dominant threshold

switching mechanism can be different for various phase change materials depending

on material properties and a combination of the suggested models may be required to

explain all the observations.

1.3.3 Scalability – Selection Device and Material Property Scaling

The most fundamental question regarding scalability of the PCM is whether the scaled

nanometer-size programmed region can change phases between two stable phases.

Study using GeTe nanoparticle have shown that nanoparticle as small as 1.8 nm can

still change phases between amorphous and crystalline phases [15], which

demonstrated that the phase change capability of the material is not limiting factor for

scaling at forthcoming technology nodes.

However, making PCM devices from scaled phase change material involves many

other considerations. In the nanometer size, the surface or boundary contribution

becomes more dominant than bulk contribution in determining overall system property.

Therefore, material properties which are important for PCM operation such as melting

temperature and crystallization temperature can change as we scale the size of the

programmed region. Various structures such as nanoparticles [15], nanodots [41],

17

nanowires [33, 42, 43, 44], and thin films [45, 46] were utilized to show material

property scaling of phase change material. These studies confirm that material

properties of phase change material change as the size of the material decreases

typically below 10 nm. The crystallization temperature increases for thinner phase

change material films [46] while interfaces also can affect the direction of the change

[45]. Crystallization times and temperatures and activation energies are reduced for

smaller nanowires [42, 43]. The melting temperature of GeTe and In2Se3 nanowires

grown by VLS mechanism has been shown to be smaller than its bulk value [47, 48].

Electrical characteristics of PCM devices also depends on the size of phase change

material. It has been shown that threshold switching behavior occurs when certain

threshold switching field is met [32]. This results in smaller threshold switching

voltage (Vth) as we scale PCM devices. This could be a potential problem for scaling

small Vth results in unstable and slow reading operation. It has been suggested that the

SET and RESET state can show different scaling behavior based on the formation of

percolation conductive path in the amorphous phase in the distributed Poole Frenkel

conduction model [49]. This can result in narrowing of the resistance window in the

isotropic scaling scenario.

Each addressable PCM cell needs to have a selection device with memory element

composed of phase changing material. Therefore, when scaling down PCM cells, not

only the memory element but also the selection device needs to be scaled. The size of

selection devices can be a limiting factor in scaling because the relatively large

programming current requirement of PCM makes requires large selection devices

which can conduct large programming current. Therefore, scalable selection devices

18

for PCM need to be able to provide large current density. The footprint of the selection

device is also important. For example, lateral metal-oxide-semiconductor field effect

transistors (MOSFET) as selection devices will result in large device footprint while

vertical bipolar junction transistors (BJT) or diode stacked with memory element will

result in smaller device footprint [3]. Large on/off ratio with small leakage current is

required for selection devices because large leakage current can cause read and

program disturb in a large array. For possible 3D integration for high memory density,

the processing temperature of selection devices should be within the thermal budge of

the back-end-of-line (BEOL) process. Due to these various requirements for selection

devices for scalable PCM device, new interesting ideas for making selection devices

such as poly-silicon diode [50], Ovonic Threshold Switch (OTS) [51], and Mixed

Ionic Electronic Conduction (MIEC) materials [52] were suggested in addition to

conventional approaches using transistor [53], diode [4], and BJT [5, 6].

1.3.4 Reliability – Retention, Thermal Disturbance, and Resistance

Drift (Multi-Bit)

Another aspect of memory technology as important as scalability is reliability.

Reliability typically involves two aspects – endurance and retention. The endurance

refers to the capability of memory cell to withstand repeated programming while

maintaining required specification. Even though endurance up to 1012 cycles has been

demonstrated for PCM [54], practical endurance of the prototypical PCM in large

array is limited to approximately 109 cycles. It has been suggested that repeated

programming of PCM devices results in gradual change in SET and RESET

19

resistances and eventually fail either in RESET-stuck or SET-stuck [55]. The exact

mechanism of this behavior is not clearly understood. The RESET-stuck is typically

attributed to the void formation or delamination in the active phase change material

region. Various elemental analysis studies linked gradual change in SET and RESET

resistances to compositional changes in the phase changing material after cycling [56,

57 , 58 , 59 , 60 ]. The compositional changes were attributed to several different

mechanisms including thermal interdiffusion, incongruent melting, electromigration,

and hole wind force.

Another reliability issue, retention, refers to the capability of memory cell to maintain

stored data. The amorphous phase of phase change material spontaneously crystallizes

into the crystalline phase even at room temperature. The crystallization time is

exponentially dependent on the temperature. The typical retention criteria require the

amorphous region to retain the data for 10 years at elevated temperature of 85 °C. It

has been demonstrated that PCM cells with phase change materials based on

Figure 1-6: Conductivity in the amorphous and

crystalline phase of Ge2Sb2Te5 as a function of time [70].

20

Ge2Sb2Te5 meets the basic retention criteria [5, 61]. However, thermal disturbance

behavior of PCM needs to be considered to evaluate the retention characteristics. [62].

Thermal disturbance refers to a situation in which the heat diffusion from the

programmed region during RESET programming causes temperature rise in the

adjacent cells. Temperature rise in the adjacent cells can crystallize the cell

unintentionally, resulting in retention failure when the thermal disturbance effect is

accumulated over time [63, 64].

The drift phenomenon of PCM devices is also important with respect to retention. The

drift behavior of PCM is described as the continuous drift of the RESET state after the

material has been melted and quenched [65, 66, 67, 68, 69]. As the RESET state drifts,

the measurable quantities such as RRESET and Vth that represent the RESET state also

drifts (Figure 1-6) [70]. The physics involved in the drift behavior is still debated. In

the past years, several theoretical models have been proposed based on trap decay

which reduces conductivity in the trap-assisted conduction model [66, 67, 68],

generation of the donor/accept defect pairs which reduces conductivity by

repositioning the Fermi level [65, 71], and mechanical stress release which widens the

energy gap between the Fermi level and the mobility edge [69]. It has been shown that

the drift speed is highly dependent on temperature [67, 68, 69, 72, 73].Figure 1-6

1.4 Thesis Overview

This thesis focuses on scalability and reliability issues of phase change memory. From

chapter 2 to chapter 4, various aspects of scalability including scaling rule, selection

device, and device characteristics scaling are addressed using theoretical analysis,

21

experimental demonstration and characterization. In chapter 5 and 6, various aspects

of reliability including resistance drift and thermal disturbance are address using

experimental characterization and modeling.

In chapter 2, scaling rule governing phase change memory is analyzed by

electrothermal modeling. Both isotropic and non-isotropic scaling scenarios are

addressed. The analytical electrothermal model identifies relevant material properties

for scaling and makes predictions for various characteristics of scaled PCM such as

programming voltage and current. Electrothermal modeling also addresses how

thermal disturbance is scaled in the isotropic scaling.

In chapter 3, Ge nanowire diode is introduced as a potential selection device for 3D

cross-point PCM array. A working PCM cell integrated with Ge nanowire diode is

experimentally demonstrated and characterized. Single crystalline Ge nanowires are

grown by vapor-liquid-solid (VLS) mechanism and in-situ doped by dopant gas during

growth. The phase change material is directly contacted by the nanowire, thus small

programming current is achieved by small contact area. Based on the characterization

results of single cells, the performance of PCM cells with Ge nanowire diodes in the

cross point is estimated.

In chapter 4, scaling of PCM cell characteristics is studied using a specially designed

novel structure. A pseudo terminal is inserted in the GST layer of the T-shape PCM

cell. The pseudo terminal enables directly probing the characteristics of the amorphous

region with precisely controlled thickness. 1D thickness scaling of various PCM cell

characteristics such as threshold switching voltage and field, resistance drift speed,

and crystallization temperatures are studied.

22

In chapter 5, temperature dependence of the drift behavior is studied using mirco-

thermal stage (MTS). The MTS is integrated with a later PCM cell to enable precisely

temperature control in microsecond time scale. The drift behavior of both RESET

resistance and threshold switching voltage is studied. Based on the existing

phenomenological drift model, analytical expression which can be used to estimate the

impact of thermal disturbance on the drift is derived and verified with characterization

results down to microsecond resolution.

In chapter 6, various impacts of thermal disturbance on PCM reliability are studied

using the micro-thermal stage (MTS). Drift, threshold switching and retention of a

lateral PCM cell which is thermally disturbed by the MTS are characterized and

modeled. The microsecond resolution in temperature control enables in-depth thermal

disturbance study without building complex memory array.

In chapter 7, the most important results and contributions to the field is summarized.

Future work is proposed.

23

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35

Chapter 2

Analysis of Temperature in Phase Change Memory Scaling

2.1 Introduction

Phase change memory (PCM) based on phase change material such as Ge2Sb2Te5 is

one of the promising candidates to replace flash memory technology. Compared with

other emerging non-volatile memory technologies, superior scalability is specific to

PCM. There have been three important issues concerning PCM scalability, which

includes scaling scenario, proximity disturbance, and minimum size [2] of stable

programming regions. Most scaling analyses suggested the constant-voltage scaling

scenario and provided experiment or simulation results supporting that proximity

disturbance is not a scalability-limiting factor [3, 4]. The theoretical background that

supports constant-voltage scaling is briefly suggested by Lacaita [5] by adopting the

concept of the holding voltage. In this chapter, we will present a thorough theoretical

explanation for the temperature – programming voltage relationship and show why the

proximity disturbance is not a scalability-limiting factor [1]. This conclusion is

supported by analytical calculation and simulation results.

2.2 Scaling Rule Requirement and General Assumptions

PCM stores data in the phase form determined from temperature history of the

region. Assuming that the melting or crystallization temperature shows no dependence

on the size of the programming region, one of the most important requirements for a

valid scaling rule to satisfy is the temperature of the programming region. In the

36

temperature analysis, we can assume the steady-state condition since the typical

programming time for SET and RESET programming is in the range of few or few-

hundreds nanoseconds [6], which is enough to reach the steady state. Therefore, we

will relate the programming voltage to the steady-state temperature and use that

temperature to ascertain the correct operation of PCM. In addition, since the highly

resistive amorphous phase has the similar electrical conductivity as that of crystalline

phase after threshold switching [7-9] and the RESET programming of the cell always

involves threshold switching, we modeled our PCM cell with the electrical and

thermal conductivity of the crystalline phase.

2.3 Constant-Voltage Isotropic Scaling and Proximity Disturbance

First consider a scaling case that scales device dimensions isotropically, i.e. scaling

three dimensions by the same factor, k. To determine the correct functionality of the

scaled device, we need to relate the temperature, T’, of the scaled device to the

temperature, T, of the device which is functional before scaling. If we let V and J to be

voltage and current density before scaling respectively and V’ and J’ to be those after

scaling, the energy conservation theory states that T, V, and J satisfy the following

respectively,

0κρ2

2=

∂∂+∇−

t

TcTJ

r (1)

VJ −∇=rρ (2)

where ρ, κ, and c are the electrical resistivity, thermal conductivity, and voluminal

specific heat. Starting from (2) and constant-voltage scaling that states

37

Table 2-1: Constant-voltage isotropic scaling rule for PCM

Parameter Factor Geometrical Length 1/k Programming Voltage 1 Programming Current 1/k Programming Current Density k SET or RESET Resistance k Electric Field k Time 1/k2

),,(),,(' kzkykxVzyxV = , we express J’ in terms of J as (3). In combination with (3), T’ in

terms of T as (4) satisfies the energy conservation equation as can be seen in (5).

Therefore, (3) and (4) is a unique solution for J’ and T’ expressed by J and T,

respectively.

),,(ρ'),,('ρ kzkykxJkVkVzyxJrr

=⋅∇−=⋅−∇= (3)

),,,(),,,(' 2tkkzkykxTtzyxT = (4)

0)1( eqin left termκρ'

'κρ' 22222

222

=×=∂∂+∇−=

∂∂+∇− k

t

TckTkJk

t

TcTJ

rr (5)

Equation (4) indicates that temperature profile in a scaled device remains the same in a

scaled geometry. Therefore, the scaled device will experience the same crystallization

or amorphization temperature at the same programming voltage. As can be seen from

(4), the temperature changing rate in time is k2 times faster in the scaled one than in

the original one, thus probably resulting in a faster operation of the device. However,

we note that for the crystallization process, the nucleation and growth time can be

dominant factors to determine the total programming time [10]. In addition, since this

result shows that the thermal disturbance also scales with geometry, it also supports

the simulation and experiment results that reported that proximity disturbance is not

38

limiting the scaling of PCM. Scaling factors for other important features derived from

the above are summarized in Table 2-1: Constant-voltage isotropic scaling rule for

PCM and are analogous to those suggested in [4].

2.4 Constant-Voltage Non-Isotropic Scaling and Minimum

Programming Voltage

Now we analyze the maximum temperature rise of the phase change memory cell in

general structures in Figure 2-1 where we assumed that the boundary conditions

around the cell is given such that thermal and electrical conduction are parallel. If we

define the origin, x=0, at the point where dT/dx=0 so that the temperature peaks at the

origin, the energy conservation [11] states that

Figure 2-1: A general memory-cell structure between two boundaries, bd1 and bd2.

x-axis is parallel to electrical and thermal conduction and A(x) is the area that is

perpendicular to electrical and thermal conduction. The origin, x=0, is where the

temperature is maximized.

39

∫=−a

dxxA

xI

dx

adTaAa

0

2

)(

)(ρ)()()(κ (6)

where A(x) is the effective area that is perpendicular to electrical currents and heat

flows and I is the current between two boundaries. Integrating dT(x) from 0 to the one

of the boundaries with the assumption that the product of ρ and κ is constant,

regardless of respective ρ and κ with possible variations in time and space, we get

)ρκ2/()( 2,0

2

0 bd

bd

MAX RIxdTT =−=∆ ∫ (7)

where R0,bd is the electrical resistance between 0 and a boundary. The boundary can be

either the left one or the right one. Therefore, R0,bd should be one half of the overall

resistance, R, resulting in

ρκ8/ρκ)2/()2/( 222 VRITMAX ==∆ . (8)

Figure 2-2: Typical PCM structures: structure A and B. The only difference between A and B is

the material for the cylinder which connects top GST and bottom heater layer. L and r1 is the

length and radius of the cylinder respectively. The ratio of the two (=L/r1) is defined as aspect

ratio, s. Please note that the name ‘heater’ does not necessarily mean that its role in the structure

is providing Joule heating for the programming volume.

40

Equation (8) shows that the maximum temperature rise is only a function of the

applied voltage, electrical resistivity and thermal conductivity and does not depend on

the geometrical sizes. This implies that constant-voltage scaling is also valid for non-

isotropic scaling of the device. The assumption of constant product of ρ and κ (ρ·κ) is

based on the Wiedemann-Franz law, which is usually applicable to good electrical

conductors such as metal and phase change material in its low-resistivity state [12].

Therefore, (8) does not lose its applicability to cell structures with more than two

materials and different conductive states of phase change material such as the on-

Figure 2-3: Analytical calculation result with applied voltage of 1V and material properties

of ρGST=36.1 mΩcm, ρheater=0.893 mΩcm, κGST=0.005W/˚Kcm, and κheater=0.2 W/˚Kcm [4].

Temperature profile along the memory cell for different aspect ratios, s, defined as L/r1. for

(a) structure A and (b) structure B in Figure 2-2. For different aspect ratios, the maximum

temperature rise is the same as expected from (7). The inset explains how to interpret the x-

axis to the actual position in the memory cell.

41

states of the amorphous phase [9, 13] and dynamic on-states of the crystalline phase

[9].

42

Figure 2-4: ANSYS simulation result with applied voltage of 1V and material properties of

ρGST=36.1 mΩ·cm, ρheater=0.893 mΩ·cm, κGST=0.005W/˚K·cm, and κheater=0.2 W/˚K·cm [4]. On the

first y axis on the left side, maximum temperature as a function of aspect ratio (=L/r1) with zero

(κDL=0) or non-zero (κDL>0) dielectric thermal conductance for (a) structure A and (b) structure

B. For κDL=0, the maximum temperature is almost constant as expected from (7). On the other

hand, for κDL>0, the maximum temperature decreases as aspect ratio increases due to larger heat

loss to the surrounding dielectric layer. The insets show example image outputs for ANSYS

simulation. On the second y axis on the right side, the current for r=50nm is plotted. The current

decrease of structure B is more dramatic than that of structure A due to highly resistive GST

cylinder in structure B.

To support this analysis, analytical model and simulation results obtained by 2D

simulator ANSYS [14] are presented. The temperature profile from the analytical

model and the simulation result in Figure 2-3 and Figure 2-4 for typical structures [4]

43

in Figure 2-2 also agrees with (8). As can be seen from Figure 2-4, more realistic cases

including non-zero thermal conductivity of the insulating layer show that maximum

temperature in the cell is lower than what is expected from (8). This suggests that

appropriate design or material choice to prevent heat loss can minimize programming

voltage for the temperature requirement. There exists a minimum programming

voltage determined by the material properties, subject to further limitation due to the

threshold switching voltage, given by

MELTmin ρκ8 TV = (9)

where TMELT is the melting temperature of the phase change material. Considering the

case where highly resistive heater is used with non-ignorable phonon thermal

conduction, (9) still sets the lower bound for programming voltage with an optimized

structure and material choice for a given phase change material. Eq. (9) suggests that

the programming power for different phase change material is given by

MELT2

min κ/ TRVP ∝= (10)

2.5 Conclusion

The first order analysis shows that the maximum temperature rise of the programming

region is only a function of the voltage and material properties, not geometrical sizes.

Thus isotropic and non-isotropic scaling of geometrical sizes with constant voltage is a

valid scaling scenario for phase change memory in terms of the temperature rise. We

further show that there exists a minimum programming voltage for phase change

memory determined by material properties.

44

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acoustic and electromagnetic simulation capabilities. See http://www.ansys.com

for details.

46 Work described in this chapter is performed in collaboration with Yuan Zhang.

Chapter 3

Integrating Phase Change Memory Cell with Ge Nanowire

Diode for Cross-Point Memory – Experimental

Demonstration and Analysis

3.1 Introduction

Phase change memory (PCM) is an emerging non-volatile memory technology which

is expected to be highly scalable, endurable and fast writable and readable [1]. PCM

programs the resistance of a cell by changing the phase of phase-changing material

such as Ge2Te2Sb5 (GST) using Joule heating from the electrical current [1, 2]. The

unidirectional programming and reading of phase change memory enables phase

change memory cells to be two terminal devices using diode selection, which will

result in high density 4F2 cross-point memory. The diode selection devices for cross-

point memory cells have been implemented in previous works using selective

epitaxially grown silicon to achieve high current density [3] or semiconducting metal

oxide to decrease the processing temperature [4]. However, a technology which

combines low processing temperature with a single crystal semiconductor diode has

not been achieved. Having a diode selection device to achieve both high current

density and low process temperature can further increase the area density of phase

change memory cells by either minimizing single memory cell sizes or 3D-stacking of

cross-point memory cell layers.

47 Work described in this chapter is performed in collaboration with Yuan Zhang.

Considering these requirements for the diode selection devices, germanium nanowire

(GeNW) is a promising candidate. First, GeNW can be grown by the vapor-liquid-sold

(VLS) mechanism which keeps process temperature below 400oC for GeNWs [5,

6].The growth temperature is lower than the back-end-of-the-line temperature, and

thus it provides a path to 3-dimensionally stacking the cross-point memory arrays.

Secondly, its single crystalline structure with controlled orientation will not only

provide high current density but also tight distribution and less variation among

devices, which is important for memory applications.

GeNWs are potentially capable of reducing the programming current of PCM, which

is one of the greatest obstacles in successfully integrating high density PCM. As

suggested theoretically and experimentally [7], one of the methods to reduce

programming current is to minimize the contact area through which the programming

current flows into the phase changing material. A small contact area has been achieved

by carefully engineered processes such as an edge contact [8], lateral cell [9], trench

cell [10], and a ring type contact [3, 11]. The small GeNW diameters in the nanometer

regime can be utilized to form a small contact area using a bottom-up approach. Since

the diameter of the nanowire is determined by the catalyst size that they are grown

from, tight control of catalyst sizes by bottom-up synthesis methods such as self-

assembly patterning [12] will result in small diameter GeNWs.

In this chapter, we report successful integration of phase change memory cell with

GeNW diode as a selection device with detailed information on integration processes,

48 Work described in this chapter is performed in collaboration with Yuan Zhang.

GeNW diode IV characteristics, PCM cell characteristics [13], and repetitive pulse

programming results.

3.2 Device Fabrication

The n-doped GeNWs are grown by the vapor-liquid-solid (VLS) technique [14] on p-

type Si (111) substrate, which forms p-n hetero-junction. Figure 3-1 shows the process

steps. The resist is patterned by lithography on a RCA cleaned p-type Si (111)

substrate for squares ranging from 10×10µm2 to 0.5x0.5µm2. Thin Au catalyst layer

(5nm) is e-beam evaporated on the pattern and the resist is lifted-off leaving squares of

Au films on the substrate. 50:1 HF dip is applied both before and after Au deposition,

in order to remove the native oxide and ensure that the Au is in direct contact with a

H-terminated Si (111) substrate. The nanowires are grown in a cold-wall CVD system

Figure 3-1: Process flow of device fabrication. For GeNW diodes characterized in chapter 3.3, Ni

is deposited instead of TiN+GST layer.

49 Work described in this chapter is performed in collaboration with Yuan Zhang.

[5, 6]. By heating up the sample to 400oC inside CVD chamber, and flowing GeH4 gas,

Au and Ge reacts and forms a liquid Au-Ge droplet. After supersaturation of the Au

catalyst by Ge, Ge crystal starts to grow along <111> direction on Si (111) substrate

and the growth temperature is lowered to 300oC. The chamber pressure is 30Torr; the

partial pressure of GeH4 in H2 is 0.44Torr, 1µm long nanowires are grown in 12min.

The GeNW is in-situ doped with phosphorus by flowing PH3 gas during growth. A

1µm thick plasma enhanced chemical vapor deposition (PECVD) silicon dioxide is

deposited at 350oC to passivate GeNW surfaces and fill the gaps between GeNWs.

Then the SiO2 is thinned and planarized by chemical mechanical polishing (CMP)

with silica slurry to expose the top of the GeNWs and shorten the length of the

nanowires. The remaining oxide and length of GeNW is between 200 and 300nm,

which results in GeNWs having a high aspect ratio of 5 - 7.5. After patterning the

resist for subsequent lift-off, 25nm thick GST is deposited by sputtering, contacting

the exposed GeNW tip. Finally 100nm thick TiN is sputter-deposited as a top

electrode and the resist is lifted-off to pattern the GST and TiN. All fabrication

processes are performed on the full wafer.

50 Work described in this chapter is performed in collaboration with Yuan Zhang.

3.3 Germanium Nanowire Diode Selection Device

3.3.1 Germanium Nanowire Synthesis

Semiconductor nanowires grown via vapor-liquid-solid (VLS) mechanism [14] have

properties of single crystalline, defect-free, high aspect ratio and can be grown at a

temperature much lower than corresponding bulk materials. For device fabrication, the

Ge nanowire needs to be doped. Here, we examine the Ge nanowires both with in-situ

phosphorous doping and without doping. Using 40nm Au colloids as catalysts, the

undoped Ge nanowires grown from two-step temperature profile (400oC-300oC) have

a cylindrical shape with a high aspect ratio (Figure 3-2(a)). In the presence of

phosphine (PH3) gas, which serves as n-type dopant, the nanowires are tapered due to

side-wall deposition. Previous studies [15] revealed that the doping precursor helps the

decomposition of germane, which results in the conformal growth along with

incorporation of phosphorus while accompanying the acicular (needle-shaped)

(a)

Ge nanowire

Au droplet

(b)

Ge nanowire

Au droplet

Figure 3-2: A cross-section SEM of Ge nanowires grown from 40nm Au colloid catalyst (a)

without doping; (b) with phosphorus in-situ doping.

51 Work described in this chapter is performed in collaboration with Yuan Zhang.

nanowire growth. Figure 3-2(b) shows the tapered nanowire grown with PH3 precursor

using the same growth condition otherwise the same as the undoped case.

3.3.2 Germanium Nanowire Diode Characteristic

In process steps shown in Figure 3-1, by depositing Ni instead of TiN+GST as a top

electrode, we can characterize GeNW diodes separately from the memory element in

PCM cells (Figure 3-3(a)). The number of nanowires under one top electrode can be

estimated from the area of Au film, which ranges from 10×10µm2 to 0.5x0.5µm2.

When nanowires are grown from thin Au film, the number of nanowires per test cell is

determined by the total amount of Au divided by the size of each Au nuclei. In other

words, with the same thickness, the larger the area of Au film, the more nanowires a

device contains. Several different nanowire diodes are grown with varied Au pad size

from 10×10µm2 down to 0.5×0.5µm2. SEM analysis shows the density of wires is

roughly 4 wires/µm2 on average. DC sweep was applied to nanowire diode. In Figure

3-3(b), the IV characteristics of several devices with various Au pad sizes are

Figure 3-3: (a) Schematic test structure for GeNW hetero-junction. Ni was sputtered as a top

contact, and substrate contact was used to bias the device. (b) IV sweep characteristics of GeNW

diode with different sizes of Au catalyst. The inset figure magnifies the reverse bias region.

52 Work described in this chapter is performed in collaboration with Yuan Zhang.

displayed. An increase of on-current was observed with the increase of Au pad size,

which is consistent with the increasing number of nanowires in each device. Figure 3-

4 is the IV curve of a 2×2µm2 size device, and the threshold voltage of this device is

around 0.3V, similar to the threshold voltage of a Ge diode. The on/off resistance ratio

of the diode is about 100X.

3.4 Phase Change Memory Cell Characteristics

With GeNWs described in detail in section 3.3, we fabricate a PCM cell as shown in

the final structure in Figure 3-1. As can be seen from Figure 3-5, RESET state in these

PCM cells shows the threshold switching, which is commonly observed in phase

Figure 3-4: IV characteristics of 2µm by 2µm size Au catalyst. The on current increases

parabolically, indicating a surface charge limited conduction current. To flow 173µA current

through the diode, the voltage drop across the diode is roughly 7V. The inset figure shows IV

characteristics near turn-on voltage.

53 Work described in this chapter is performed in collaboration with Yuan Zhang.

change memory devices [16]. Figure 3-6 shows the IV characteristics of SET (low

resistance, crystalline) and RESET (high resistance, amorphous) state in a GeNW

PCM cell. In the forward biased region (positive voltage), the SET and RESET state

shows resistance difference of ~100 times. In the reverse biased region, the resistance

of SET states increases 50-100 times in comparison to SET resistance in forward bias.

On the other hand, the resistance of RESET states is almost the same in reverse and

forward. This is because the resistance of GeNW itself is lower than resistance of

amorphous programmed volume of GST and higher than that of crystalline

programmed volume. Therefore, most of voltages are dropped in the programmed

volume when the memory cell is in RESET state, which does not show rectifying

behavior. On the other hand, most of voltages are dropped in the GeNW diode when it

is in SET state. This suggests that lowering the resistance of GeNW will give us

higher overall resistance ratio between SET and RESET state.

54 Work described in this chapter is performed in collaboration with Yuan Zhang.

The circuit simulation for a cross-point array of memory cells modeled from IV

characteristics shown in Figure 3-6 suggests that an array as large as 64 by 64 (4Kb)

or larger can be built with these GeNW PCM cells (Figure 3-7). In the array

simulation, the bit-line resistance is assigned to be higher than the word-line resistance

because at present GeNWs have to be grown on a doped bit-lines in the substrate that

is more resistive than metal word-lines. The bit-line resistance per cell distance is

estimated from 2 squares of high dose implanted bit-lines (5 Ω /square) and the word-

line resistance per cell distance is estimated from 2 squares of thin TiN word-lines (0.5

Ω /square).

Figure 3-5: Current sweep IV characteristics of GeNW PCM cells. Cells in RESET state show

threshold switching behavior at voltages higher than 4V. The 5um by 5um cell has higher current

than the 1um by 1um cell possibly due to more number of nanowires.

55 Work described in this chapter is performed in collaboration with Yuan Zhang.

Our PCM cell can be programmed with repetitive programming pulses. Figure 3-8

shows the experimental setup for repetitive pulse programming. The oscilloscope

channel 1 serves as an impedance match to the pulse input and at the same time it

monitors pulse input into the memory cell. After the pulse goes through the memory

cell, it goes into a parallel load of series resistance and the oscilloscope channel 2

(1MΩ) to determine the actual programming current. The monitored pulse shape from

the oscilloscope provides more detailed information about the parasitic capacitance to

extract actual current that goes through the phase change memory cell [16]. After each

Figure 3-6: Current sweep IV characteristics of the SET and RESET programmed GeNW PCM

cell. (1) Current sweep to program SET state. (2) Current sweep after the first pulse RESET-

programming. (3) Current sweep after the first pulse SET-programming. (4) Current sweep after

the second pulse RESET-programming. IV characteristic of SET state is asymmetric because

GeNW diode is more resistive than the crystalline (SET) programming region in GST.

56 Work described in this chapter is performed in collaboration with Yuan Zhang.

programming cycle of the memory cell, the resistance of the programmed memory cell

is measured using voltage pulses with low voltage amplitude of 3V.

Stable and repetitive pulse programming is achieved at the pulse amplitude of 8.5V for

RESET and 5.5V for SET with various pulse widths. The resultant programming

currents are 173µA for RESET and 45.5µA for SET respectively. As can be seen from

Figure 3-9(a), the long programming widths of 1µs for RESET and 20µs for SET

shows stable repetitive SET and RESET transition with the average resistance ratio of

Figure 3-7: Circuit simulation results as a function of number of GeNW PCM memory cells in an

array. Each memory cell is modeled from IV curve in Fig. 6. Three different read schemes are

simulated – V, V/2, and V/3 scheme [20]. VREAD is 3V. ISETREADMIN /IRESET

READMAX are respectively

minimum/maximum read current of SET/RESET state including contributions from leakage

current in unselected cells in the estimated worst case. The maximum read current of RESET

state increases rapidly due to the leakage current through the unselected cells. Only V scheme

shows enough read margin at 64 by 64 array size.

57 Work described in this chapter is performed in collaboration with Yuan Zhang.

82 and SET resistances are quite uniform. If short programming pulse widths of 50ns

for RESET and 200ns for SET is used, the repetitive switching is still observable

(Figure 3-9(b)) while higher SET resistances than the average are occasionally

observed and the overall RESET resistance decreases compared to that of long pulse

width. Comparing results from short and long programming pulse widths, the

occasional high SET resistances from short pulse widths can be explained by partial

crystallization of the programmed volume, whereas the low overall RESET resistances

from short pulse widths can be explained by the smaller volume of programmed

amorphous region. As for the endurance of the device, a switching up to 500 times can

be observed. Afterwards, further programming brought the cell into an open circuit.

The endurance is expected to increase upon optimization of process steps and cell

architecture.

58 Work described in this chapter is performed in collaboration with Yuan Zhang.

3.5 Discussion

For the GeNW diode, a parabolic on-current IV curve is observed at voltage lower

than 2 volts, it is probably caused by surface charge limited conduction. At a larger

forward bias, the on-current increases linearly with voltage and it is degraded by the

series resistance of Ge nanowire. The extracted doping concentration for GeNW from

diode IV curve is ~1017cm-3; with a 200nm long wire, the series resistance can be as

large as tens of kΩ. The relatively small on/off ratio of 100 is due to unexpectedly

large leakage current. This leakage current is probably caused by nanowire surface and

bulk traps. Au is used as catalyst, which can diffuse into GeNW during growth. These

Figure 3-8: Pulse programming setup. Oscilloscope channel 1 serves as an

impedance matching to the input pulse at the top electrode of a memory cell

while monitoring the pulse shape. Oscilloscope channel 2 measures the

voltage that is converted from the programming current by the series

resistance.

59 Work described in this chapter is performed in collaboration with Yuan Zhang.

Au atoms can form generation and recombination centers in the depletion region of the

heterojunction, and cause leakage current at reverse bias. Furthermore, the cross-

section TEM image in the literature [6] shows imperfect interface of GeNW to Si

substrate, and several atomic layers of oxide were observed. These interface defects

will affect diode property. Therefore, there is still large enough room for further

improvement of programming voltage and array size of GeNW PCM cells by

optimizing GeNW diode characteristics such as doping concentration and leakage

current. The use of nanowire catalyst such as TiSi [17] instead of Au will also help

reduce leakage current and reduce contamination.

The programming voltage of 8.5V and 5.5V for GeNW PCM cells are relatively high

for PCM. This is because of the fact that the GeNWs are highly resistive, requiring

~7V to conduct the required amount of current for RESET (Figure 3-4). This large

voltage drop in GeNWs suggests that most of Joule heating is located in the GeNW

diodes, not in the programming region. Due to germanium’s relatively high thermal

Figure 3-9: (a) Resistance measured at 3V after each SET/RESET programming. The pulse

width/amplitude is 1µs/8.5V for RESET and 20µs/5.5V for SET. (b) The pulse is shorter than (a).

The pulse width/amplitude is 50ns/8.5V for RESET and 200ns/5.5V for SET. There are two data

points for SET state which show higher resistance than other SET states. This is speculated to be

due to partial crystallization. The average RESET resistances of (b) are smaller than those of (a).

This is speculated to be due to smaller amorphous volume.

60 Work described in this chapter is performed in collaboration with Yuan Zhang.

conductance of 60.2W/m·K in bulk [18] and its high electrical resistivity of 0.04 Ω·cm

that we have extracted from series resistance, the heat generated in GeNWs cannot

effectively raise the temperature of the programming region [19]. In addition to this,

the SiO2 surrounding GeNWs of high aspect ratios efficiently delivers the heat out

from the GeNWs. Figure 3-10 shows the results from the thermoelectric simulations

which show that either decreasing electrical resistivity or shortening height of a

GeNW can lower the programming voltage. If we make a GeNW 2 times less

electrically resistive which can be easily achieved by increasing the doping

concentration, the RESET programming voltage is expected to be reduced from 8.5V

Figure 3-10: Thermoelectric simulation results for temperature rise from 2D axis-symmetric

GeNW PCM cell. The diameter of GeNW is 40nm. (a) shows sample simulation result. The length

of GeNW is 250nm. The thickness of GST layer is 25nm. The applied voltage is 8.5V. κGe=60.2

W/m·K. κSiO2= 1.4 W/m·K. σGe=25 Ω-1cm-1. (b) shows simulation results for germanium

conductivity (σGe) from 25 to 500 Ω-1cm-1. As we increase the germanium conductivity, the

programming voltage decreases substantially without increasing programming current too much,

resulting lower power programming. (c) shows simulation results as a function of the GeNW

height. As we decrease the GeNW height, the programming voltage decreases but the

programming current increases rather rapidly. The programming power is minimized between

150nm and 250nm. Therefore, we can conclude that low doping concentration and large height of

GeNW are responsible for high programming voltage.

61 Work described in this chapter is performed in collaboration with Yuan Zhang.

to 6.0V. If we shorten the GeNW to 150nm, the RESET programming voltage as low

as 6.6V can be achieved.

3.6 Conclusion

For the first time, we have successfully integrated single phase-change-memory cells

with in-situ doped germanium nanowire diodes on a wafer level and demonstrated its

repetitive pulse programming capabilities. It shows a small SET and RESET

programming current of 173 and 45.5µA which is attributable to small contact sizes

between GeNWs and phase changing material. The forward/reverse current ratio of

100 of GeNW diodes characterized independently from phase changing material

shows that they are able to provide enough selectivity for cross-point array as large as

64 by 64 or larger. This work illustrates the combination of bottom-up synthesis

(GeNW) with conventional device fabrication techniques (CMP, sputtering) to achieve

3D stackable cross-point memory cells. Full-wafer processing of nanowire in an

integrated process is also demonstrated in this chapter. It is a necessary milestone

toward large scale integration of nanowire technology in a CMOS environment. While

the device characteristics achieved are promising, further improvements are required

for a competitive technology. Further improvements on GeNWs such as series

resistance and low leakage current can decrease required programming voltage and

power. Reducing the diameter of GeNWs down to as small as 5-7 nm by controlling

the catalyst size [12] and optimizing growth condition can potentially decrease RESET

programming current down to ~10µA.

62 Work described in this chapter is performed in collaboration with Yuan Zhang.

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65 Work described in this chapter is performed in collaboration with Yuan Zhang.

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[20] Yi-Chou Chen, C.F. Chen, C.T. Chen, J.Y. Yu, S. Wu, S.L. Lung, Rick Liu,

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66 Work described in this chapter is performed in collaboration with Byoung-Jae Bae.

Chapter 4

1D Thickness Scaling Study of Phase Change Material

(Ge2Sb2Te5) using a Pseudo 3-Terminal Device

4.1 Introduction

Phase change memory (PCM) is one of the most promising candidates for next

generation high-density and embedded memory [1 , 2 , 3 ]. The ultimate limit for

scalability of PCM is set by the minimum number of atoms or size of the programmed

region which can be switched between amorphous and crystalline phase reliably.

However, as we have seen from other memory and logic devices, many aspects of

device characteristics are affected by device scaling as well, which can become a

practical obstacle for scaling even before the ultimate scalability is reached. Therefore,

the scaling effect on important devices characteristics in PCM such as the threshold

switching voltage (Vth), RESET resistance (RRESET) drift, and crystallization

temperature (Tcrys) have been studied by other researchers through modeling and

experiments. Scalability study using novel structures such as nanowires [4, 5, 6, 7],

nanodots [8], and nanoparticles [9] and novel measurement techniques (e.g. time-

resolved x-ray diffraction [8, 9, 10 , 11 ]) have shown that material properties

themselves such as Vth, crystallization kinetics and melting temperature are affected by

scaling. However, we still lack direct observation of these property changes in the

typical PCM cell structures. There are scalability studies using typical PCM cell

structures which have carefully characterized the scaling effect on Vth [12] and the

67 Work described in this chapter is performed in collaboration with Byoung-Jae Bae.

RRESET drift [13]. However, scalability studies on those typical PCM cell structures

lack precise control of the programmed region size and the size of the programmed

region were only inferred from other electrically measured quantities [12, 13].

From this standpoint we study the scaling behavior of ultrathin Ge2Sb2Te5 (GST) film

using a pseudo 3-terminal device. The physical location of the pseudo terminal limits

the size of the accessible programmed region, which makes it possible to accurately

correlate the actual size of the programmed region to the observed properties. This

novel test structure is a fully functional PCM cell which closely resembles the scaled

version of typical PCM cell structure, i.e. a T-shape or mushroom cell [14]. This

allows us to characterize the scaling behavior of important PCM device characteristics

such as Vth, Vth drift, RRESET drift, and Tcrys from one structure as a function of precisely

determined amorphous GST thickness.

Bottom Electrode

BottomHeater

GST

Top Electrode(TE)

Additional TE(ATE)

Figure 4-1: Schematics of (a) a typical T-shape PCM cell and (b) a pseudo

3-terminal device with an additional top electrode (ATE) layer inserted into

Ge2Sb2Te5 (GST) layer.

68 Work described in this chapter is performed in collaboration with Byoung-Jae Bae.

4.2 Device Operation

The schematic structure of the pseudo 3-terminal device used for 1D thickness scaling

study is shown in Figure 4-1(b), in which an additional top electrode (ATE) metal is

placed inside the GST layer of the typical T-shape device (Figure 4-1(a)). The ATE

layer divides the GST layer into GST1 layer below the ATE and GST2 on top of the

ATE. The ATE cannot be directly probed and thus it is treated as a pseudo terminal.

Due to the ATE, the characteristics of RESET state such as Vth, drift speed, Tcrys are

determined primarily by the thickness of the GST1 layer regardless of the thickness of

the GST2 layer for the following reason. Once the amorphous regions (a-GST) are

formed after RESET programming as illustrated in Figure 4-2, the most electrically

conductive path is TiN top electrode – the crystalline region (x-GST) in the GST2

W

TiN

GST2

TiN

GST1ATE

a-GST1

a-GST2

x-GST

Low R path

Figure 4-2: Schematics of the RESET state of the pseudo 3-terminal

device. The diameter and length of the TiN bottom heater is 75 and

100 nm, respectively. Total thickness of GST1, ATE, and GST2 is

257 nm. The most conductive path is TiN top electrode – the

crystalline region (x-GST) in the GST2 layer – ATE – a-GST in the

GST1 layer – TiN heater – W bottom electrode.

69 Work described in this chapter is performed in collaboration with Byoung-Jae Bae.

layer – ATE – a-GST in the GST1 layer – TiN heater – W bottom electrode. In this

path, the most electrically resistive element is the a-GST in the GST1 layer and the

most of electric field is developed between the ATE and the TiN heater. As a result,

the device characteristics are measured as if the ATE terminal were directly probed.

Therefore, we can study the characteristics of RESET state as a function of GST

thickness by fabricating pseudo 3-terminal devices with different thicknesses for the

GST1 layer. Even though the GST2 layer seems insignificant electrically, the GST2

layer effectively confines the heat by thermally separating the GST1 layer from the top

electrode heat sink so that enough temperature-rise for programming can be achieved

in the GST1 layer. The overall effect is summarized in Figure 4-3. Thick GST and

short heater cause the hottest spot to be located above the heater inside the GST during

RESET programming [15]. By inserting the ATE, the hottest spot is confined in GST1

layer because the ATE metal is thermally more conductive than GST and spreads the

heat to the lateral direction effectively. This results in a full amorphization of the

GST1 layer and dome-shaped amorphous region in the GST2 layer.

70 Work described in this chapter is performed in collaboration with Byoung-Jae Bae.

To verify this device operation, we measure Vth while changing RESET voltage

(VRESET). Vth has been reported to scale linearly with the length (or the thickness) of the

amorphous region with constant threshold switching field using a lateral bridge type

PCM cell [16]. Vth of the pseudo 3-terminal device in this work is shown to be nearly

insensitive to VRESET (Figure 4-4(b)) because the switching is confined in the fully

amorphized GST1 layer even though larger VRESET forms larger a-GST region in the

GST2 layer. For the conventional T-shaped device, on the other hand, higher VRESET

results in a larger a-GST volume, hence a larger Vth (Figure 4-4(a)). The 6 nm thick

tungsten is chosen as adequate material for ATE due to its high thermal and electrical

conductivity and good chemical stability. The GST1 thickness is varied between 6 and

23 nm. The GST2 thickness is chosen such that the total GST thickness is constant at

251 nm. The TEM images of device with 6 nm-thick GST1 layer display that GST1

0 10 20 30 400

200

400

600

800

1000

1200

1400

1600

Tem

pera

ture

[K]

Position [nm]

TiN 6 nm W 6 nm

TiN

GST1

GST2

TiN

W

TiN W

GST1 ATE GST2

Figure 4-3: Finite element modeling (FEM) simulation results on the RESET operation for

devices with (a) 6 nm-thick TiN ATE, (b) 6 nm-thick W ATE and (c) their temperature profile

along the center line. The hottest spot is confined in the GST1 layer by ATE layers. Higher

thermal conductivity of W results in lower temperature rise in the GST1 layer.

71 Work described in this chapter is performed in collaboration with Byoung-Jae Bae.

film appears smooth without any pinhole, which enables the reliable fabrication

processes (Figure 4-5).

Characteristic Resistance-Power (R-P) curves for different thicknesses of GST1 layers

are shown in Figure 4-6. 75 ns long RESET pulses are applied to pseudo 3-terminal

devices while monitoring the resultant current to determine the power. Resistance

starts to increase at larger electrical power for thinner GST1 layers because the ATE

layer with high thermal conductivity is closer to the programmed region for thinner

GST1 layers causing larger thermal loss. RRESET decreases as GST1 thickness

decreases confirming that the overall resistance is dominated by a-GST region in the

GST1 layer. RSET is relatively constant regardless of GST1 thickness because

crystalline GST is highly conductive.

0.0 0.5 1.0 1.5 2.0 2.5 3.00

10

20

30

Cur

rent

(µA

)

Voltage (V)

VRESET

(V)

2.1 2.4 2.7

0.0 0.5 1.0 1.5 2.0 2.5 3.00

10

20

30

Cur

rent

(µA

)

Voltage (V)

VRESET

(V)

2.1 2.4 2.7

(a) (b)

Figure 4-4: RESET state current-sweep I-V curves of (a) T-shape and (b) pseudo 3-terminal

devices for various RESET voltages (VRESET). GST1 thickness is 25 nm. Threshold switching

voltage (Vth) of the pseudo 3-terminal device is nearly insensitive to VRESET. In the conventional T-

shaped device, on the other hand, higher VRESET results in a larger Vth

72 Work described in this chapter is performed in collaboration with Byoung-Jae Bae.

4.3 Threshold Switching Voltage

As PCM device scales down isotropically, a-GST volume decreases and so does Vth

[12]. Since the read voltage should be smaller than Vth in order to distinguish the SET

and RESET states and avoid disturbing programmed states, a Vth that is too small can

reduce the readout voltage window resulting in unreliable and slow readout. So far Vth

scaling of GST or any other phase-change material down to the nanometer regime is

still unclear due to the uncertainty of the melt-quenched amorphous region size [6],

[12, 16]. To provide insights into Vth scaling of GST, Vth of pseudo 3-terminal devices

with different GST1 thickness are measured. All devices are first programmed to the

RESET state by applying a voltage pulse 2.4V in amplitude and 75 ns in duration. Vth

is measured from the current sweep. Figure 4-7 shows that Vth decreases linearly with

100 nm

5 nmW BE

GST2

TiN TE

GST1W ATEGST2

6 nm

6 nm

SiO2

Figure 4-5: A cross-sectional TEM image of device with 6 nm-thick GST1 layer. Bottom

heater is not shown here. EDX analyses (not included here) show no composition difference

between GST1 and GST2.

73 Work described in this chapter is performed in collaboration with Byoung-Jae Bae.

slope of 41 mV/nm down to ~0.65 V value, where GST1 thickness reaches to 6 nm.

Therefore, Vth scaling can be phenomelogically described by the following equation.

01 thGSTthth VdEV +⋅= (1)

where Eth and Vth0 are the threshold switching field and threshold switching voltage

extrapolated to zero dGST1 respectively. Eth of 41 mV/nm is similar to 30-58 mV/nm

which have been reported for GST elsewhere [16, 17 ]. The non-zero minimum

threshold switching voltage (Vth0) has been previously reported as well [6, 16], which

is beneficial for scaling by preventing Vth from being too small. The physical origin of

non-zero Vth0 as well as the mechanism behind threshold switching is still debated.

Those include models based on impact ionization [18], field induced crystallization

0 1 2 3 4 5 6 7 81k

10k

100k

1M

10M

Res

ista

nce

(Ω)

Power (mW)

dGST1

No ATE 23 nm 15 nm 6 nm

Figure 4-6: Resistance-power (R-P) curve for various GST1 thicknesses (dGST1). 75 ns long

voltage pulse applied with various voltage amplitudes to a fresh SET state. Larger power is

required to initiate resistance increase for thinner dGST1. RRESET saturates at lower resistance

level for thinner dGST1 due to smaller amorphous volume. RSET is nearly constant for various

dGST1.

74 Work described in this chapter is performed in collaboration with Byoung-Jae Bae.

[19], and energy gain of electrons in a high electric field [20]. A minimum energy

required for impact ionization has been suggested as a possible explanation for non-

zero Vth0 [6].

It has been reported that Vth drifts after RESET programming [21 , 22 , 23 ]. To

determine which component of Vth is contributing to the drift, i.e. Eth or Vth0 or both,

we measure Vth as a function of time after RESET programming (sleep time) for

pseudo 3-terminal devices with different GST1 thicknesses. To measure Vth at a

specific sleep time, a single triangle voltage pulse is applied to the ATE device at the

specific sleep time after RESET programming. Once Vth is reached by rising voltage

amplitude of the triangle pulse, threshold switching takes place which can be detected

by measuring the sudden increase of the current through the pseudo 3-terminal device.

0.0 0.5 1.0 1.50.0

20.0

40.0

60.0

80.0

C

urre

nt (

µA)

Voltage (V)

dGST1

(nm)

23 19 15 12 9 6

0 5 10 15 20 25 300.0

0.5

1.0

1.5

Vth (

V)

dGST1

(GST1 layer thickness) (nm)

Slope = 41 mV/nm

Figure 4-7: (a) Current sweep I-V curves and (b) Vth for varying GST1 thickness (6 – 23nm). All

devices are first programmed to the RESET state by applying a voltage pulse 2.4V in height and

75 ns in duration before I-V measurement. Vth decreases linearly with slope of 41 mV/nm down to

~0.65 V value, where GST1 thickness reaches to 6 nm. Each GST1 thickness is confirmed by

TEM and SEM analyses. Threshold current showed variations from device to device, while Vth

values were nearly constant.

75 Work described in this chapter is performed in collaboration with Byoung-Jae Bae.

Vth can be determined from the ramp rate and time difference between the onset of the

triangle pulse and the switching.

Figure 4-8(a) shows Vth as a function of GST1 thickness for various sleep times. For

each sleep time, Vth linearly scales with GST1 thickness extrapolating to non-zero Vth0.

By linearly fitting the Vth measurement results, we can find Eth and Vth0 at each sleep

time and determine whether they drift. Eth and Vth0 as a function of sleep time is

plotted in Figure 4-8(b). Eth increases linearly as logarithm of sleep time increases in

the same manner for the Vth drift which also has shown the logarithmic dependence

[23, 24]. On the other hand, Vth0 does not show any clear dependence on the sleep time

and is almost constant at ~0.53 V. Therefore, the Vth drift can be attributed to the Eth

drift with constant Vth0. In the framework of the impact ionization model as a proposed

mechanism for threshold switching [18], this suggests that the minimum energy

required for impact ionization such as band gap of the phase change material

comparable to e·Vth0 does not drift. Eth drift can be attributed to the change of other

5 10 15 20 25

0.7

0.8

0.9

1.0

1.1

1.2

1.3

Vth (

V)

dGST1

(nm)

10 s 1 s 100 ms 10 ms 1 ms 100 µs

1m 100m 1010

15

20

25

30

35

40

Eth (

mV

/nm

)

Sleep time (s)

Eth

0.50

0.52

0.54

0.56

0.58

0.60

Vth0

Vth

0 (V

)

Figure 4-8: (a) Vth vs. GST1 thickness (dGST1) for various sleep times between 100 µs and 10 s. (b)

Threshold switching field (Eth) and extrapolated Vth (Vth0) at dGST1=0 as a function of sleep time.

Eth drifts linearly to the logarithm of the sleep time. Vth0 does not show any drift behavior.

76 Work described in this chapter is performed in collaboration with Byoung-Jae Bae.

factors that determine the carrier generation rate such as the carrier density. For

example, if the carrier density decreases, Eth should increase to maintain the same

generation rate. In fact, it has been suggested that the carrier density decreases after

RESET programming, which is attributed to be the cause of the resistance drift [21,

23].

It has been reported that Vth decreases as the temperature increases [24]. In order to

check that the read operation still has a large enough readout voltage window in the

high-temperature range, the dependence of Vth on temperature is investigated (Figure

4-9). The cells are annealed at 100 ˚C for 10 minutes to isolate the effect of the drift on

Vth [23]. We observed monotonic decrease of Vth from ~0.65 V to ~0.5 V in the

0.0 0.2 0.4 0.6 0.80

20

40

60

80

100

Cur

rent

(µA

)

Voltage (V)

25 oC 40 oC 55 oC 70 oC

Figure 4-9: Current-sweep I-V curves of device with 6 nm-thick GST1 layer for

varying temperature. Vth decreases from ~0.65 V to ~0.5 V in the temperature

range of 25 to 70 °C. Both RESET programming and subsequent I-V

measurement were performed at the same temperature.

77 Work described in this chapter is performed in collaboration with Byoung-Jae Bae.

temperature range of 25 to 70 °C, respectively, showing relatively weak temperature

dependency.

4.4 RESET Resistance Drift

The large on/off ratio of PCM of 2-3 orders is promising for the multilevel cell. The

drift of RESET resistance (RRESET) is one of main obstacles for realization of reliable

multilevel PCM [25]. It has been shown that the RRESET drift of partial-RESET state

with a small a-GST volume is insignificant compared to that of full-RESET state with

a large a-GST volume [13, 25]. However, it is not clear yet whether the full RESET

state with a small a-GST volume in a scaled PCM cell would have a small drift

coefficient. To analyze the dependence of the drift coefficient on the amorphous cap

thickness in the full RESET state, RRESET drift behavior as a function of GST1

thickness has been measured. In contrast to previous results which showed small drift

1m 10m 100m 1 10100k

1M

10M

Res

ista

nce

(Ω)

Sleep Time (s)

No ATE GST1 23 nm GST1 15 nm GST1 6 nm

1m 10m 100m 1 10

1

2

3

Nor

mal

ized

res

ista

nce

(R/R

0)

Sleep Time (s)

No ATE GST1 23 nm GST1 15 nm GST1 6 nm

Figure 4-10: Bi-logarithmic plot of (a) resistance and (b) normalized resistance ratio as a function

of time for varying GST1 thickness. All data follow an empirical equation of (R/Ro) = (t/to)ν. Here

the drift exponent ν ranges from about 0.10 to 0.12 with no clear dependence on thickness. All

devices are programmed to their full RESET states before read.

78 Work described in this chapter is performed in collaboration with Byoung-Jae Bae.

coefficients from small a-GST volume in the partial RESET state [13, 25], no

correlation between GST1 thickness and drift coefficient is observed down to 6 nm

when the a-GST volume is in the full RESET state (Figure 4-10). This indicates that

the same degree of RRESET drift can be still present even in a scaled device with small

GST thickness. The small drift exponent of the partial RESET state in other literatures

[13, 25] can be related to parallel conductive paths in the partial-RESET state which

does not drift [26]. These parallel conductive paths can be either crystalline filaments

remaining in the amorphous region or percolation paths [27] formed during partial

RESET programming. The reason why these paths are formed could be attributed to

insufficient temperature rise which is avoided in pseudo 3-thermal devices by full

RESET programming.

4.5 Crystallization Temperature

As a nonvolatile memory, PCM is required to retain data typically for 10 years at the

elevated temperature of 85 ˚C. The memory retention of PCM is determined by the

stability of amorphous phase-change material because amorphous phases crystallize

spontaneously [28]. One of the material properties that are related to the stability of

the amorphous phase is the Crystallization temperature (Tcrys) because higher Tcrys is

linked to the longer retention time. Previous study using time-resolved X-ray

diffraction has shown that when the chalcogenide film thickness falls below ~10nm,

Tcrys can change since the relative contribution from the interface increases [10, 11].

The direction and amount of change in Tcrys is determined by the adjacent materials

because the contribution from the interface is determined by the interfacial energy

79 Work described in this chapter is performed in collaboration with Byoung-Jae Bae.

between adjacent materials. For example, Tcrys of the GeSb layer sandwiched between

SiN layers increases as the GeSb layer thickness decreases while Tcrys decreases for the

GeSb layer sandwiched between W layers [11]. To examine whether such an effect

exists in the pseudo 3-terminal devices, the device resistance is measured as a function

of temperature (Figure 4-11). The resistance decreases continuously in the low-

temperature range with carrier activation and abruptly decreases due to crystallization.

The amorphous-to-crystalline transition at about 175 °C is observed for the device

with 6 nm-thick GST1 layer compared to thick a-GST at 145 °C. This result shows

that shifts in Tcrys of GST can be also observed in nano-sized PCM device.

80 Work described in this chapter is performed in collaboration with Byoung-Jae Bae.

60 80 100 120 140 160 180 2001k

10k

100k

1M

10M

Res

ista

nce

(Ω)

Temperature (oC)

No ATE GST1 15 nm GST1 6 nm

Figure 4-11: Dependence of resistance on temperature for varying GST1

thickness. Heating ramp rate is about 5 ˚C/min. Crystallization temperature

has been measured by observing the R shift while increasing temperature. The

amorphous-to-crystalline transition at about 175 °C is observed for the device

with 6 nm-thick GST1 layer compared to thick a-GST at 145 °C.

4.6 Conclusions

Scalability of PCM is assessed using a novel fully-functional PCM cell that has the

3rd pseudo terminal which enables the full amorphization of GST with known

thickness. Since GST thickness is controlled by deposition time, 1D thickness scaling

study on a-GST can be demonstrated without the need for ultra-fine lithography. Vth

linearly scales down to 0.65-0.5 V (25-75 °C) at 6 nm scale, showing that stable read

operation is possible in scaled PCM devices. The linear dependence of Vth on the

thickness suggests that threshold switching is initiated by the electric field not the

voltage. Threshold switching field has been shown to drift while the extrapolated Vth at

81 Work described in this chapter is performed in collaboration with Byoung-Jae Bae.

zero thickness stays almost constant. Both 3D isotropic scaling and 1D thickness

scaling result in the same electric-field scaling. Therefore, 1D thickness scaling results

on Vth is expected to be valid for the isotropically scaled PCM device. RRESET drift

shows no dependency on the a-GST thickness down to 6 nm regime in 1D scaling.

This suggests that the solution for drift is still needed even in the scaled PCM device.

Thin a-GST shows larger Tcrys compared to thick a-GST which suggests increased

thermal stability. The change in Tcrys is attributed to the increased contribution from

the interface. Therefore, 3D scaling can result in further change in Tcrys due to the

relative area change after scaling. From 1D scaling study on Vth, RRESET drift, and Tcrys,

no significant hurdles against scaling are found down to 6 nm scale and PCM remains

to be a promising future memory technology with high scalability.

82 Work described in this chapter is performed in collaboration with Byoung-Jae Bae.

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87

Chapter 5

Resistance and Threshold Switching Voltage Drift Behavior

in Phase-Change Memory and Their Temperature

Dependence at Microsecond Time Scales

5.1 Introduction

Phase-change memory (PCM) is one of the most mature candidates for a next

generation non-volatile memory [1]. PCM provides a new set of features in the

memory application field including non-volatility, good endurance, bit-alterability,

and fast read and write [2]. PCM stores data by changing the structural phase of a

chalcogenide material. The two memory states correspond to crystalline phase with

low resistivity (the SET state) and amorphous phase with high resistivity (the RESET

state). The phase change in the PCM cell is thermally induced by electrical Joule

heating. The electrical resistance of the written cell is read to determine the stored

phase.

The scalability and reliability of PCM are the key issues to be solved in order to

broaden its application among memory devices. It requires understanding of basic

physical properties of the phase change material related to the PCM operation such as

the threshold switching phenomenon [3, 4, 5], the drift behavior [6, 7, 8, 9, 10], the

recovery behavior [11], and the material property scaling [12]. Among them, the drift

behavior is the key factor that determines multi-bit capability and reliability. The drift

behavior is described as the continuous drift of the RESET state after the material has

88

been melted and quenched. As a result, electrical characteristics of the RESET state

including the RESET resistance and the threshold switching voltage drift after the cell

is programmed in the RESET state. The physics involved in the drift behavior is still

debated. In the past years, several theoretical models have been proposed based on

trap decay which reduces conductivity in the trap-assisted conduction model [7, 8, 9],

generation of the donor/accept defect pairs which reduces conductivity by

repositioning the Fermi level [6, 13], and mechanical stress release which widens the

energy gap between the Fermi level and the mobility edge [10]. There have been

experimental studies on the temperature dependence of the drift behavior using the

conventional hot stage or plate to compare with what various models [8, 9, 10, 14, 15]

predict. Due to the large thermal time constant of the conventional hot stage or plate,

temperature-dependent measurements were conducted at time scales of a few seconds

or more and the results were extrapolated over 5-6 orders of magnitude down to a few

microseconds. Therefore, the experimental demonstration of the validity of the

extrapolation is still important to understand the physics behind the drift phenomenon.

The temperature dependence of the drift behavior in the microsecond time scale is also

important to understand the effect of thermal disturbance on PCM operation [16].

Thermal disturbance refers to a situation in which the heat diffusion from the

programmed region during RESET programming causes temperature rise in the

adjacent cells. Temperature rise in the adjacent cells can crystallize the cell

unintentionally, resulting in retention failure when the thermal disturbance effect is

accumulated over time [17, 18]. In addition, the temperature rise can expedite the drift

behavior of the cell resulting in larger RESET resistance (RRESET) and threshold

89

switching voltage (Vth) variations [16]. The effect of the thermal disturbance in a

scaled device can become even larger as cell distances decrease due to aggressive

scaling which scales the cell distances more aggressively than the vertical dimension

[18]. To our best knowledge, an analytical prediction for the impact of the short

temperature rise (e.g. thermal disturbance) on the drift has not been provided yet.

In this chapter, we extend the temperature-dependent drift measurement down to

microsecond time scale which is the relevant time scale for PCM operation. We

measure both RRESET and Vth drift behavior which represent the drift of the RESET

state. With these new measurement results, we verify the existing phenomenological

drift model for constant annealing temperature down to 100 µs without extrapolation.

The key enabler for these new measurements is the micro-thermal stage (MTS). The

MTS consists of the lateral PCM cell and the Pt heater for changing the temperature of

the PCM cell in microseconds. Finally, we present the analytical expression for the

drift with time-varying annealing temperature, which can predict the impact of thermal

disturbance on the drift. The analytical prediction agrees well with measurement

results using the MTS.

5.2 The Drift Model and its Temperature Dependence

The drift behavior of PCM is described as the continuous drift of the RESET state

after the material has been melted and quenched [6, 7, 8, 9, 10]. As the RESET state

drifts, the measurable quantities such as RRESET and Vth that represent the RESET state

also drifts. Regardless of differences in the proposed mechanisms for the drift

behavior, experimental data on RRESET and Vth drifts for constant annealing temperature

90

were phenomenologically described by the following equations which were either

derived [10] or replicated by calculation [6, 7, 8] in each model.

ν)()(0

0 t

tRtRRESET = (1)

α)log()(0

0 t

tVtV thth += (2)

where t, ν, and α are time after RESET programming, RRESET drift coefficient, and Vth

drift coefficient respectively.

To theoretically model the temperature dependence of the drift behavior, we base our

analysis on the trap decay model [7, 8, 9], which has been expressed in analytical

forms with detailed description of most physics involved. The energy barrier for trap

decay in the proposed model results in strong temperature dependence [14]. To

theoretically estimate the temperature dependence of drift coefficients, ν and α, we

assume that RRESET and Vth are determined by the trap density, NT. According to the

trap decay model where traps are characterized by a distribution of trap energy and an

initial trap density, the total trap density (NT(t)) in the case of constant annealing

temperature is given by the following equation [7, 9, 14]

σAkT

TT t

tNtN

−= )()(

00 (for t >> t0) (3)

where NT0, k, TA, and σ are initial total trap density, Boltzmann constant, annealing

temperature and energy decay constant respectively. The drift coefficient for RRESET

can be related to NT by the following equation and it shows that it is proportional to

annealing temperature (TA).

91

AA

T

RESETT

T

RESETRESET TkT

tNd

tRd

td

tNd

tNd

tRd

td

tRd ∝−⋅=== )()(ln

)(ln

ln

)(ln

)(ln

)(ln

ln

)(ln

σν . (4)

The )(ln/)(ln tNdtRd TRESET term also has the temperature dependence but it

depends on the reading temperature (TR), not TA. The same derivation can be applied

to the drift coefficient for Vth and it can be shown that it is also proportional to TA.

When the Meyer-Neldel [19, 20] effect is considered, the temperature dependence of

the RRESET drift coefficient is expressed in a slightly different form which is

proportional to TA/(1-TA/TMN) [15] where TMN is the compensation temperature.

However, the overall tendency generally agrees well considering that TMN is relatively

high compared to the annealing temperature in consideration.

To experimentally measure the temperature dependence of drift coefficients, the

programming and reading temperature (TP and TR) should be constant while changing

the annealing temperature (TA) because non-constant TP and TR complicates

interpretation of measurement data by adding secondary effects. For example, TP

determines the initial RESET state such as the amorphous region size and the initial

trap density. In addition, the same number of traps may be represented by different

RRESET and Vth at different TR [6, 21, 22]. An experimental procedure which separates

the impact of TA on the drift from the impact of TR on the measurement results even

when TA and TR are identical has been proposed [23]. However, it is still not applicable

to measurements in microsecond time scale because it is still required to control TP

independently from TA or TR. Therefore, in the following experiment as well as

modeling, we maintained TP and TR at room temperature while changing only TA to

distinguish and study the effect of temperature on the drift. To extend these

92

temperature-dependent measurements to microseconds which are the relevant time

scale for PCM operation, a faster heater is required which has a thermal time constant

in the microsecond time scale because TA is not necessarily the same as TP and TR. We

implement such a fast heater with micro-thermal stage (MTS).

5.3 Micro-Thermal Stage (MTS)

The thermal time constant or speed of the temperature controller is determined by the

total thermal mass of the system. Therefore, by positioning the heat source near the

target region, the thermal mass and the thermal time constant can be reduced. The

micro-thermal stage (MTS) implements this design concept. Figure 5-1 shows the

lateral PCM cell integrated with the MTS. First, the lateral PCM cell is fabricated as

reported in ref. [24]. A 20 nm thick doped SbTe alloy is deposited by sputtering and

Figure 5-1: Microscope image of micro-thermal stage (MTS). Pt heater is

integrated on top of the lateral phase change memory (PCM) cell. The inset 3D

figure shows the Pt heater overlapped region over narrow phase change material

programmed region.

93

patterned by reactive ion etching (RIE) in a line cell. After pattering, the PCM cells

were passivated using a ~1 µm thick combination of silicon oxide and silicon nitride.

On top of the passivation layer, the 80 nm thick Pt bridge as a heater is patterned.

The inset figure in Figure 5-1 shows the 3D structure of the MTS. By generating Joule

heat in the Pt heater, the temperature of the programmed region of the PCM cell is

controlled. The Pt heater is only ~1 µm away from the programmed region resulting in

1.53 and 1.27 µs of thermal time constant for the programmed region and Pt heater

respectively. Additional thermal time constant of 0.26 µs can be attributed to the delay

time for generated heat to travel from the Pt heater to the programmed region. Width

1n 1µ 1m 1 1k

Tem

pera

ture

Termal time constant (s)

Figure 5-2: Micro-thermal stage (MTS) extends temperature control down to microsecond time

scale or below which is not accessible by conventional thermal stages with large thermal time

constants. Precise temperature control below crystallization temperature (Tcrys) is enabled by

MTS in contrast to phase change material self-Joule heating which suffers from sudden increase

of temperature caused by the threshold switching. Due to its extended temporal resolution,

programming (TP), annealing (TA), and reading temperatures (TR) can be independently

controlled.

94

of the Pt heater (5 µm) is much wider than the size of the programmed region (200 nm

by 400 nm) to ensure uniform temperature rise in the programmed region. The power

delivered to the Pt heater can be controlled precisely by controlling the voltage

amplitude to the Pt heater, resulting in accurate control of the amount of temperature

rise for a wide range of temperatures.

Note that if the temperature is controlled by the self-Joule heating of the phase change

material, the large conductivity difference before and after threshold switching makes

it difficult to control the amount of temperature rise especially for temperature range

below the crystallization temperature. Also, the self-Joule heating of the phase change

0.0 5.0m 10.0m 15.0m165

170

175

180

185

40 °C35 °C30 °C 25 °C20 °C

RP

t (Ω

)

Power (W)

THC

Linear fit

Figure 5-3: The resistance of the Pt heater increases linearly as temperature increases. The

temperature of the Pt heater is determined by electrical power provided to the Pt heater (P) and

hot-chuck temperature (THC). By fitting experimental results to (5), the amount of temperature

rise can be determined from electrical power. From resistance difference for various THC at

constant P, the temperature coefficient of Pt (TCRPt) is extracted first. Thermal resistance (RH)

can be extracted from the slope gradient from linear fitting which is the product of TCPPt and RH.

Temperature rise for given P is the product of RH and P.

95

material may accompany unintentional electronic effects on the drift such as re-

initiation of the drift after threshold switching even without melt-quenching [6], which

makes it difficult to distinguish temperature-dependent effects. The applicable range

of the thermal time constant and the temperature range of the MTS is compared with

conventional methods in Figure 5-2.

The temperature of the MTS is calibrated by the temperature dependence of the

resistance of the Pt heater. Most of the heat generated in the Pt heater propagates

downward toward the Si substrate because the thermal resistance between the Pt

heater and the Si substrate (i.e. heat sink) is low enough to remove most of heat

efficiently. Downward heat conduction can be treated as 1-dimensional conduction

because the width of the Pt heater is much larger than the thickness of underlying

layers. Therefore, the temperature is almost constant along the Pt heater during Joule

heating in the steady state. Since the resistivity of most metals linearly increases as

temperature increases [25], the temperature rise from Joule heating can be measured

from the resistivity change of the heater. In steady state, the resistivity of the Pt heater,

ρPt, on the temperature-controlled hot chuck is given by

)(0 HHCPtPt RPTTCR ⋅⋅⋅⋅++++⋅⋅⋅⋅++++==== ρρρρρρρρ (5)

where TCRPt, THC, P, RH are temperature coefficient of resistance of Pt, temperature of

hot chuck on which the sample is placed, power delivered to the Pt heater, and thermal

resistance between the Pt heater and the chuck respectively. After calibrating the

resistance of the Pt heater with the heater power and the chuck temperature (THC) as in

Figure 5-3, the temperature rise of the Pt heater can be determined once the power

provided to the Pt heater is known.

96

In steady state, the ratio of the temperature rise of the programmed region in the PCM

cell to the temperature rise of the Pt heater is constant and determined by the ratio of

their thermal resistances to ambient temperature. The temperature of the programmed

region of the PCM cell can be calibrated using the temperature dependence of the

RESET resistance of the PCM cell because the resistivity of the amorphous region is

highly dependent on the temperature [6, 21, 22]. By comparing the resistivity of the

amorphous region on the MTS with those at various temperatures of hot chuck, the

temperature rise of the programmed region can be determined directly from the

electrical power delivered to the Pt heater.

97

5.4 Experimental Results and Discussion

To study the dependence of the drift on the annealing temperature, we apply separate

electrical pulses to the PCM cell and the Pt heater. The electrical pulse to the PCM cell

programs the cell and measures cell characteristics such as RRESET and Vth. The

electrical pulse to the Pt heater controls the temperature of the programmed region of

the PCM cell. Timing of the electrical pulses are precisely controlled using triggering

signals and internal timers of pulse generators.

Figure 5-4: Electrical pulse and temperature profile for RRESET drift measurement.

The measurement results are shown in Fig. 5. Cells are programmed and read at

room temperature (= 25 ˚C). The cell resistances are read by small read voltage

pulses at multiple delay times for reading (dR). Cells are annealed at various

annealing temperature (TA) between 25 and 185 ˚C by the Pt heater.

98

5.4.1 RESET Resistance Drift for Constant Annealing

Temperature

We experimentally verify the existing phenomenological RRESET drift model for

constant annealing temperature in microsecond time scale. To measure the

temperature dependence of the RRESET drift coefficient, we vary the annealing

temperature (TA) between 25 ˚C (no annealing) and 185 ˚C. The PCM cell is

programmed and read at 25 ˚C without any heating from the Pt heater (i.e. TP=TR=25

˚C). The annealing pulse started at 10 µs after RESET programming. The 10 µs time-

margin guarantees that the programmed region quenches to 25 ˚C after RESET

programming to achieve identical initial RESET states. The reading pulse is 20 µs

long and the annealing pulse is turned off 40 µs before reading and restarts 40 µs after

the reading. The 40 µs time-margins guarantee that the programmed region stays

constantly at 25 ˚C throughout reading. The current-to-voltage amplifier makes short

reading time of 20 µs sufficient to read the RRESET with accuracy of less than 2 %. The

RRESET is read at 100 µs, 1 ms, 10 ms, 100 ms, and 1 s plus time-margins after RESET

programming. Time-margins contribute to measurement errors because the

programmed region is not annealed during time-margins. These errors from time-

margins can be compensated in the later calculation for the drift coefficient. The shape

and timing of the electrical pulse and resultant temperature are shown in Figure 5-4.

99

Figure 5-5(a) shows the RRESET drift over time for various TA. Each data point is from

~100 measurements such that random variations are averaged out. The RRESET drift

behavior in Figure 5-5(a) follows the power law as described in (1). Therefore, the

RRESET drift coefficient in (1) can be extracted for various TA. Figure 5-5(b) shows the

RRESET drift coefficient calculated from the data in Figure 5-5(a) for various TA. At low

temperature, the drift coefficient increases linearly as shown by (4). At high

temperature, the drift coefficient increases slowly and even decreases possibly due to

simultaneous crystallization at high temperatures [15] or drift saturation [10]. By

finding the intersection points between extrapolated lines at various TA from the data

in Figure 5-5(a), t0 and R0 are found to be between 10 ns and 1 ps and between 400

and 600 kΩ respectively.

∝

10µ 100µ 1m 10m 100m 1 101M

2M

3M

4M

5M

25 °C 45 °C 65 °C 85 °C 105 °C 125 °C 145 °C 165 °C 185 °C

RE

SE

T r

esis

tanc

e (Ω

)

Delay time for read (s)

50 100 150 2000.07

0.08

0.09

0.10

Drif

t coe

ffici

ent

Annealing temperature (TA) (°C)

Figure 5-5: (a) RESET resistance as a function of time after RESET programming for various

annealing temperatures (TA). (b) RRESET drift coefficient calculated from the data in (a). Cells are

programmed and read at room temperature (= 25 ˚C). RRESET drift coefficient increases linearly as

annealing temperatures increases below ~100 ˚C. Possibly due to drift saturation or simultaneous

crystallization process, drift coefficient decrease at high temperatures. Cells are programmed and

read at room temperature (= 25 ˚C). The measurement pulse details are shown in Figure 5-4.

100

5.4.2 RESET Resistance Drift for Time-Varying Annealing

Temperature

In a practical scenario for PCM cell in operation, the annealing temperature cannot be

constant because cells are thermally disturbed by the RESET programming of the

neighboring cells [16, 17, 18]. Then, how can we estimate the actual RRESET trace for

those thermally disturbed cells? The simple form in (1) cannot be directly applied to

this case because (1) assumes that annealing temperature stays constant after RESET

programming. If the annealing temperature is changing continuously as TA(t), the

RRESET drift speed is dependent on the present trap density and trap energy distribution

and annealing temperature (TA). The present trap density and trap energy distribution

can be represented by RRESET(TR, t), which is RRESET measured at reading temperature

(TR) and time after RESET programming (t). We assume that the same RRESET(TR, t)

corresponds to the same RESET state characterized by the same number of traps with

identical trap energy distribution. To derive an equation for RRESET(TR, t) for time-

varying annealing temperature, TA(t), we express RRESET(TR,t+∆t) in terms of

RRESET(TR,t), ∆t, and TA(t+∆t) as in the following equation.

),( ))((

00

ttTeffRRESET

A

t

ttRttTR ∆++∆

=∆+ ν

))(())((

1

000 ]

),([ ttTttTRRESET AA

R

tTR

t

tR ∆+∆++∆= νν , (6)

where teff is the time that it would have taken for RESET resistance to drift to

RRESET(TR,t) if the annealing temperature had been constant at TA(t+∆t) from the time

101

when it was RESET programmed (as in the drift model for constant annealing

temperature). Between t and ∆t, the RESET state drifts at the annealing temperature of

TA(t+∆t). The derivation of (6) is represented in Figure 5-6. Equation (6) leads to the

following partial differential equation,

))((

1

0

0

)),(

())(()),((ln tT

RRESET

ARRESET A

tTR

R

t

tT

dt

tTRd νν= . (7)

))((

00 )( ttT

t

mR ∆+ν

))((

1

00 ]

),([ ttTRRESET

eff

R

tTRt

t

∆+= ν

Figure 5-6: Schematic diagram for derivation of (6), which derives RRESET(TR,t+∆t) in terms of

RRESET(TR,t), ∆t, and TA(t+∆t). TA(t+∆t) is the annealing temperature between t and t+∆t. The curve

on the figure represents the RESET resistance drift trace that would have been followed if the

annealing temperature were constant at TA(t+∆t) since RESET programming. First, teff is

calculated from RRESET(TR,t). teff is the time that it would have taken for RESET resistance to drift

to RRESET(TR,t) if the annealing temperature had been constant at TA(t+∆t) since RESET

programming. RESET resistance drifts for a time period of ∆t, following the curve from teff to

teff+∆t. RRESET(TR,t+∆t) is determined as the RESET resistance that corresponds to teff+∆t on the

time-axis.

102

From (7), RRESET(TR, t) can be numerically determined for given TA(t) once we know

ν(TA), t0, and R0 at TR. To determine the validity of (7), we compare measurement

results with the prediction based on ν(TA), R0, and t0 obtained from Figure 5-5. The

prediction is calculated numerically from (7). TA(t) shown in Figure 5-7 is

implemented using the Pt heater on the MTS. We vary the delay time for annealing

(dA) and measure RRESET at various delay time for reading (dR). The temperature and

duration of the annealing pulse are 60 ˚C and 600 µs. The RRESET is read at 100 µs, 1

ms, 10 ms, 100 ms, 1 s, and 20 s after RESET programming. The programming and

reading is at 25 ˚C without any heating from the Pt heater. The delay time for

annealing (dA) is varied at 300 µs, 1.2 ms, 11 ms, and 110 ms.

Figure 5-7: Electrical pulse and temperature profile for RRESET drift measurement. The

measurement results are shown in Fig. 8. Cells are programmed and read at room

temperature (= 25 ˚C). The cell resistances are read by small read voltage pulses at

multiple delay times for reading (dR). The delay time for annealing (dA) is varied between

300 µs and 110 ms. The heat pulse is 600 µs long and 60 ˚C high.

103

Figure 5-8(a) shows the measured RRESET drift for various dA. Each data point is from

~100 measurements such that random variations are averaged out. RRESET at 100 µs are

the same for various dA verifying that the initial RESET states are the same. As can be

seen from Figure 5-8(b) where the percentage change from RRESET(t) without any

annealing is plotted, annealing at dA of 300 µs which is the shortest in this experiment

shows the largest percentage increase. This can be deduced from the resistance drift

model in (7) which shows larger percentage change (d(lnRRESET(TR,t))/dt) for smaller

RRESET(TR,t). Therefore, if the temperature and the duration of the annealing are the

same, the shortest dA results in the largest percentage increase.

104

Figure 5-8(c) shows the averaged RRESET drift coefficient (∆ln(RRESET(TR, t))/∆ln(t))

extracted from the same set of data in Figure 5-8(a). When dA is short, the extracted

averaged drift coefficient for time period which has annealing pulse in it is much

larger than the drift coefficient ν(TA=60 ˚C) in Figure 5-5(b). For example, averaged ν

between 100 µs and 1 ms for dA of 300 µs is close to 0.2 while ν(60 ˚C) is only ~0.085

in Figure 5-5(b). This rather non-intuitive result is due to the fact that ν(TA) is the

RRESET drift coefficient when the cell is continuously annealed at TA, which is not the

(a) (b)

(c) (d)

10µ 100µ 1m 10m 100m 1 10 100

1M

1.5M

2M

2.5M

RR

ES

ET (

Ω)

Delay time for read (s)

Delay time for annealing 300µs 1.2ms 11ms 110ms No annealing

10µ 100µ 1m 10m 100m 1 10500k

1M

1.5M

2M

2.5M[R

RESET]

Estimation Experiment

RR

ES

ET (

Ω)

Delay time for read (s)

0.0

0.1

0.2

0.3

0.4

0.5

Drif

t coe

ffici

ent

[Drift coefficient] Estimation Experiment

100µ 1m 10m 100m 1 100.00

0.05

0.10

0.15

0.20Delay time for annealing

300µs 1.2ms 11ms 110ms No annealing

Drif

t coe

ffici

ent

Delay time for read (s)

100µ 1m 10m 100m 1-5.0

0.0

5.0

10.0

15.0

20.0

25.0

30.0

∆RR

ES

ET/R

RE

SE

T (

%)

Delay time for read (s)

Delay time for annealing 300 µs 1.2 ms 11 ms 110 ms

Figure 5-8: (a) RRESET(t) for various delay time for annealing (dA). (b) The percentage difference of

RRESET(t) with respect to RRESET(t) without any annealing. Shorter dA results in larger percentage

difference during annealing. (c) RRESET drift coefficient calculated from 8(a). The RRESET drift

coefficient dramatically changes during and right after annealing for small dA. (d) The estimation

based on (7) agrees well with measurement results. The case when dA is 300 µs is shown here.

Cells are programmed and read at room temperature (= 25 ˚C). The measurement pulse details

are shown in Figure 5-7.

105

case in this measurement. In this measurement, the cell was not annealed at the

beginning, which leaves intact traps that would have otherwise decayed if the cell is

annealed continuously at TA. Therefore, when the annealing started at dA, these

remaining traps decay very rapidly resulting in a higher drift coefficient. The same

mechanism is responsible for the reduced drift coefficient after the annealing stops.

Some traps at low trap energy had already decayed at the elevated annealing

temperature (TA) and this leaves less traps to decay later on at the room temperature.

Figure 5-8(c) clearly shows this effect where the drift coefficient is reduced below

ν(25 ˚C) after the annealing. This effect of early expedited or impeded decay can be

better understood by simply inserting a time shift term (∆tshift) in the drift equation, (1).

∆tshift enables us to analyze the drift behavior with the time-varying annealing

temperature using a simpler form of the drift equation for constant annealing

temperature as shown by the following equation.

)(

00 )(),( ATshift

RRESET t

ttRtTR ν∆+

= . (8)

If the annealing temperature has been previously deviated from TA, its overall effect

can be accounted by ∆tshift. ∆tshift can be found so that RRESET(TR,t) calculated from (8)

is identical to that calculated from (7). Equation (8) leads to the effective drift

coefficient (νeff) to be

106

shift

ARRESETRRESET

eff tt

tT

td

dt

dt

tTRd

td

tTRd

∆+=== )(

ln

),(ln

ln

),(ln νν (9)

where ν(TA) is the RRESET drift coefficient for constant annealing temperature of TA. For

zero ∆tshift, i.e. the cell is continuously annealed at TA, νeff is the same as ν(TA). For

positive ∆tshift, i.e. the cell has less traps because traps at low trap energy have already

decayed due to pre-annealing temperature which is higher than TA, νeff is smaller than

ν(TA). For negative ∆tshift, i.e. the cell has more traps because trap decay has been

impeded by pre-annealing temperature which is lower than TA, νeff is larger than ν(TA).

Figure 5-9: Electrical pulse and temperature profile for Vth drift measurement. The measurement

results are shown in Fig. 10. Cells are programmed and read at room temperature (25 ˚C). Cells

are annealed by the Pt heater at annealing temperature (TA) between 25 and 185 ˚C. The reading

pulse for Vth is applied after delay time for read (dR) which varies between 0.1 µs and 1 s. The

reading pulse for Vth is a single triangular pulse which causes sudden increase of current when the

amplitude reaches Vth. By measuring the time it takes to threshold-switch (tth), Vth is determined

as the product of tth and the voltage ramp rate.

107

As can be seen from Figure 5-8(c), ∆tshift becomes negligible as t increases and νeff

converges to ν(TA). Figure 5-8(d) shows that the prediction from (7) agrees well with

measurement results for both RRESET and its drift coefficient.

5.4.3 Threshold Switching Voltage Drift and Temperature

Dependence

The temperature dependence of the RESET state drift can also be measured from

threshold switching voltage (Vth) drift measurement. The PCM cell on the MTS is

programmed into the full RESET state and Vth is read at 25 ˚C while cells are annealed

at various annealing temperatures (TA) before reading Vth. To read Vth, a single triangle

pulse which ramps up is applied to the RESET state. Once Vth is reached, the current

through the PCM cell suddenly increases (Figure 5-9). By monitoring the current

through the PCM cell, Vth can be determined from the ramp rate of the pulse and the

time it takes to threshold switch (tth).

0.0 50.0 100.0 150.0 200.0

0.06

0.08

0.10

Vth d

rift c

oeffi

cien

t

Annealing temperature (TA) (°C)

10µ 100µ 1m 10m 100m 1 10

1.0

1.1

1.2

1.3

1.4

1.5

25 °C 65 °C 105 °C 145 °C 185 °C

Vth (

V)

Delay time for read (s)

Figure 5-10: (a) Vth(t) for various annealing temperatures (TA). (b) Vth drift coefficient as a

function of TA calculated from (a). It shows the tendency to increase as TA increases and agrees

well with temperature dependence of RRESET drift coefficient. Cells are programmed and read at

room temperature (= 25 ˚C). The measurement pulse details are shown in Figure 5-9.

108

To measure the Vth drift behavior, Vth is read at 100 µs, 1ms, 10 ms, 100 ms, and 1 s.

Vth is read only once per RESET programming since the cells can be partial-SET

programmed by Vth measurement. The annealing of PCM cells starts 10 µs after

RESET programming. The annealing temperature (TA) is varied between 25 (no

annealing) and 185 ˚C.

Figure 5-10(a) shows the Vth drift over time with various TA. It confirms that the drift

is faster at higher annealing temperature resulting in higher Vth. By fitting the data

according to (2), the Vth drift coefficient can be found as a function of TA (Figure 5-

10(b)). As we have seen from the RRESET drift measurement, the drift coefficient of Vth

drift also shows the tendency to increase as temperature increases. The Vth drift data

has more variation than RRESET drift data perhaps because of the stochastic nature of

the formation of the conduction path due to percolation [16, 26].

5.5 The Drift Model Comparison

As it has been mentioned in the introduction, various models for the drift mechanism

have been proposed in the past years. Those include the models based on trap decay [7,

8, 9], generation of the donor/accept defect pairs defects [6, 71], and mechanical stress

release [10]. In previous sections, we derive analytical expressions and interpret our

measurement data based on the trap decay model.

Nonetheless, our analysis and results on temperature dependence do not conclude that

the trap decay model is the only valid model. With more or less rigorousness, different

drift models can lead to the same temperature dependence. The mechanical stress

release model [10] also implies the identical temperature dependence for the drift

109

coefficient with constant annealing temperature as the model derivation leads to the

following expression for the drift coefficient.

R

A

B T

T

W

Du

∆= 0ν , (10)

where, u0, D, and ∆WB are the maximum dilation, the deformation potential, and the

difference between maximum and minimum barrier heights. The donor/accept defect

pair model [71] also suggests that the similar temperature dependence can be observed

once the temperature dependence of the defect pair generation rate is included in the

model.

The analytical expression for the drift model with time-varying annealing temperature

in (7) is derived from the common phenomenological model in (1) which all drift

models suggested. The assumption that the same RRESET corresponds to the same

RESET state is applicable regardless of how each model defines the RESET state (e.g.

trap density, band gap, and donor/accept defect pair density). Therefore, the analytical

expression for the drift model with time-varying annealing temperature also does not

exclude any drift model to be invalid.

5.6 Conclusion

In this chapter, we measure the RESET resistance (RRESET) and threshold switching

voltage (Vth) drift coefficient and its temperature dependence in microseconds time

scale using a novel measurement structure, the micro-thermal stage (MTS). The MTS

places a metal heater in close proximity of the phase-change memory (PCM)

programmed region to reduce thermal time constant and accurately control the

110

temperature. Using PCM cells with MTS, we extend the temperature-dependent

measurement on the RRESET and Vth drift to 100 µs for PCM cells annealed constantly

at temperatures between 25 and 180 °C while maintaining the fixed programming and

reading temperature at 25 °C. We experimentally show that the existing

phenomenological model for the drift is applicable down to microseconds time scale

for wide range of annealing temperatures. We find that measured temperature

dependence of the drift coefficient for constant annealing temperature is proportional

to the annealing temperature as expected from the trap decay model with distributed

trap energy [7, 8, 9]. Based on the phenomenological drift model for constant

annealing temperature, we derive an analytical expression that can explain the drift

behavior for time-varying annealing temperature and show that it agrees well with

experimental results from MTS. This analytical expression will lead to better

assessment of the thermal disturbance effect on the RRESET and Vth drift and resultant

variations in them.

111

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[1] G. Servalli, “A 45nm generation phase change memory technology,” in IEDM

Tech. Dig., 2009, pp. 113-116.

[2] R. Bez, “Chalcogenide PCM: a memory technology for next decade,” in IEDM

Tech. Dig., 2009, pp. 89-92.

[3] A. Pirovano, A. L. Lacaita, A. Benvenuti, F. Pellizzer, and R. Bez, “Electronic

Switching in Phase-Change Memories,” IEEE Trans. Electron Devices, vol. 51,

no. 3, pp. 452-459, Mar 2004.

[4] V. G. Karpov, Y. A. Kryukov, S. D. Savransky, and I. V. Karpov, “Nucleation

switching in phase change memory,” Appl. Phys. Lett., vol. 90, p. 123504, 2007.

[5] D. Ielmini and Y. Zhang, “Analytical model for subthreshold conduction and

threshold switching in chalcogenide-based memory devices,” J. Appl. Phys., vol.

102, no. 5, p. 054517, Sep. 2007.

[6] A. Pirovano, A. L. Lacaita, F. Pellizzer, S. A. Kostylev, A. Benvenuti, and R. Bez,

“Low-field amorphous state resistance and threshold voltage drift in chalcogenide

materials,” IEEE Trans. Electron Devices., vol. 51, no. 5, pp. 714-719, May 2004.

[7] D. Ielmini, S. Lavizzari, D. Sharma, and A. L. Lacaita, “Physical interpretation,

modeling and impact on phase change memory (PCM) reliability of resistance

drift due to chalcogenide structural relaxation,” in IEDM Tech. Dig., 2007, pp.

939-942.

112

[8] D. Ielmini, D. Sharma, S. Lavizzari, and A. L. Lacaita, “Reliability impact of

chalcogenide-Structure relaxation in phase-change memory (PCM) cells-Part I:

Experimental study,” IEEE Trans. Electron Devices, vol. 56, no. 5, pp. 1070-1077,

May 2009.

[9] S. Lavizzari, D. Ielmini, D. Sharma, and A. L. Lacaita, “Reliability impact of

chalcogenide-Structure relaxation in phase-change memory (PCM) cells-Part II:

Physics-Based Modeling,” IEEE Trans. Electron Devices, vol. 56, no. 5, pp.

1078-1085, May 2009.

[10] I. V. Karpov, M. Mitra, D. Kau, G. Spadini, Y. A. Kryukov, and V. G. Karpov,

“Fundamental drift of parameters in chalcogenide phase change memory,” J. App.

Phys., vol. 102, no. 12, p. 124503, Dec. 2007.

[11] D. Ielmini, A. L. Lacaita, and D. Mantegazza, “Recovery and drift dynamics of

resistance and threshold voltages in phase-change memories,” IEEE Trans.

Electron Devices, vol. 54, no. 2, pp. 308-315, Feb 2007.

[12] S. Raoux, J. L. Jordan-Sweet, and A. J. Kellock, “Crystallization properties of

ultrathin phase change films,” J. Appl. Phys., vol. 103, p. 114310, 2008.

[ 13 ] A. Redaelli, A. Pirovano, A. Lacatelli, and F. Pellizzer, “Numerical

Implementation of low field resistance drift for phase change memory

simulations,” in proc. NVSMW/ICMTD 2008, pp. 39-42.

[14] D. Ielmini, S. Lavizzari, D. Sharma, and A. L. Lacaita, “Temperature acceleration

of structural relaxation in amorphous Ge2Sb2Te5,” Appl. Phys. Lett., vol. 92, no.

19, p. 193511, May 2008.

113

[15] D. Ielmini, M. Boniardi, A. L. Lacaita, A. Redaelli, A. Pirovano, “Unified

mechanisms for structural relaxation and crystallization in phase-change memory

devices,” Microelectronic Engineering, vol. 86, pp. 1942-1945, 2009.

[16] S. Kim, B. Lee, M. Asheghi, G.A.M. Hurkx, J. Reifenberg, K. Goodson, and H.-S.

P. Wong, “Thermal disturbance and its impact on reliability of phase-change

memory studied by micro-thermal stage,” in IEEE International Reliability

Physics Symposium (IRPS), Anaheim, CA, May 2-6, 2010, pp. 99-103.

[17] A. Pirovano, A. L. Lacaita, A. Benvenuti, F. Pellizzer, S. Hudgens, and R. Bez.,

“Scaling analysis of phase-change memory technology,” in IEDM Tech. Dig.

2003, pp. 29.6.1-29.6.4.

[18] U. Russo, D. Ielmini, A. Redaelli, and A. L. Lacaita., “Modeling of programming

and read performance in phase change memories - part II: Program disturb and

mixed scaling approach,” IEEE Trans. Electron Devices., vol. 55, no. 2, pp. 515-

522, Feb. 2008.

[19] W. Meyer and H. Neldel, “Uber die beziehungen zwischen der energiekonstanten

und der mengenkonstanten a in der leitwerts temperaturformel bei oxydischen

halbleitern,” Z. Tech. Phys., vol. 18, p. 588, 1937.

[20] K. Shimakawa and F. Abdel-Wahab, “The Meyer-Neldel rule in chalcogenide

glasses,” Appl. Phys. Lett., vol. 70, pp. 652-654, 1997.

[21] D. Ielmini and Y. Zhang, “Physics-based analytical model of chalcogenide-based

memories for array simulation,” in IEDM Tech. Dig., 2006, pp. 401-404.

114

[22] D. Ielmini and Y. Zhang, “Analytical model for subthreshold conduction and

threshold switching in chalcogenide-based memory devices,” J. Appl. Phys., vol.

102, no. 5, p. 054517, Sep. 2007.

[23] M. Boniardi, A. Redaelli, A. Pirovano, I. Tortorelli, D. Ielmini, and F. Pellizzer,

“A physics-based model of electrical conduction decrease with time in amorphous

Ge2Sb2Te5,” J. Appl. Phys., vol. 105, no. 8, p. 084506, May. 2009.

[24] D. Tio Castro, L. Goux, G. A. M. Hurkx, K. Attenborough, R. Delhougne, J.

Lisoni, F. J. Jedema, M. A. A. in ‘t Zandt, R. A. M. Wolters, D. J. Gravesteijn, M.

A. Verheijen, M. Kaiser, R. G. R. Weemaes, and D. J. Wouters, “Evidence of the

thermo-electric Thomson effect and influence on the program conditions and cell

optimization in phase-change memory cells,” in IEDM Tech. Dig., 2007, pp. 315-

318.

[25] R. B. Belser and W. H. Hicklin, “Temperature coefficients of resistance of

metallic films in the temperature range 25° to 600°C,” J. Appl. Phys., vol. 30, no.

3, pp. 313-322, Mar. 1959.

[26] D. Fugazza, D. Ielmini, S. Lavizzari, and A. L. Lacaita, “Distributed-Poole-

Frenkel modeling of anomalous resistance scaling and fluctuations in phase-

change memory (PCM) devices,” in IEDM Tech. Dig., 2009, pp. 723-726.

115

Chapter 6

Thermal Disturbance and its Impact on Reliability of Phase-

Change Memory Studied by the Micro-Thermal Stage

6.1 Introduction

Phase-change memory (PCM) is one of the most mature candidates for a next

generation non-volatile memory [1, 2]. As a candidate for future memory devices,

scalability is the key issue. Aggressive scaling scenarios on PCM and migration to a

4F2 cross-point array structure result in faster scaling for cell-to-cell distances which

leads to a larger temperature rise in adjacent cells [3, 4]. Therefore, understanding the

impact of thermal disturbance (TD) on PCM reliability is important.

The main concern for TD has been its impact on retention for high resistance (RESET)

state [3, 4]. However, this can be a too simplistic picture because many characteristics

of the RESET state are also dependent on temperature such as RESET resistance

(RRESET) [5], threshold switching voltage (Vth) [6], and their drift behaviors [7-11].

Therefore, TD results in larger variation for RRESET and Vth, which is one of main

concerns for memory reliability and makes multi-bit realization more difficult. TD

effect is not static because the RESET state continuously changes after RESET

programming due to the drift behavior. Therefore, TD can have different impact on

RRESET and Vth variation depending on the time when it affects the memory cell (delay

time).

116

In this chapter, we experimentally evaluate the impact of TD on retention, RRESET, and

Vth variation using a PCM cell integrated with an external heater and their impact on

reliability of PCM is discussed.

6.2 Micro-Thermal Stage

When a selected cell in the PCM array is programmed, the adjacent cells are thermally

disturbed due to the heat diffusion. The programming time is typically less than a few

hundred nanoseconds and thus TD can be treated as a short heat pulse. To

experimentally emulate short time-scale thermal fluctuations as TDs, we implement

the micro-thermal stage (MTS). The MTS is designed to enable precise long-range

temperature control in a microsecond time-scale. Figure 6-1 shows the MTS. The

MTS heater is integrated directly on top of the lateral PCM cell to control the local

Figure 6-1: Microscope image of the micro-thermal stage (MTS). A Pt MTS heater

is integrated on top of the lateral phase-change memory (PCM) cell which was

reported elsewhere [12]. The inset figure shows the MTS heater overlapped region

over PCM programming region.

117

temperature in-situ during the measurement. The total thermal mass of the MTS is

much less compared to the conventional thermal stages where the whole sample and

chuck are heated. Therefore, the MTS lowers thermal time constant to a few

microseconds and we extend the time-scale of temperature dependence measurement

from ~100 µs to ~10 s with current MTS design. Pt is chosen as a MTS heater material

because the temperature of the heater can be calibrated using the temperature

coefficient of resistance and its resistivity is appropriate for effective heating for the

geometry of the heater. The electrical pulse to the MTS heater generates Joule heat

and controls the temperature of the programmed region of the memory cell.

118

6.3 Experimental Results

6.3.1 Crystallization Time

We first investigate the impact of TD on retention. Retention failure occurs when the

phase-change material in the RESET state is crystallized into the low resistance (SET)

state and the crystallization process can be accelerated by TD. Therefore, retention

characteristic can be characterized by the temperature dependence of crystallization

time (tcrys). tcrys at various temperatures has been determined by monitoring current

through the PCM cell with a small bias while being heated by the MTS heater in time-

scale as short as hundreds of microseconds and detecting the first sudden increase in

current. In measurement of current through the PCM cell, multiple steps are observed

0.0 20.0m 40.0m

0.0

20.0µ

40.0µ

60.0µ

Cur

rent

(A

)

Time after heating starts (s)

# of steps 1 2 3

Temperature rises to200 °C

tcrys

Figure 6-2: Number of crystallization steps varies between 1 to several.

Crystallization behaviors are represented by the current through PCM

cells. Reading voltage is 0.1V. Cells are annealed at 200 °C for

crystallization.

119

(Figure 6-2). This observation suggests that multiple crystalline paths are formed

during crystallization as schematically depicted in Figure 6-3.

Figure 6-4 shows that tcrys follows an Arrhenius behavior with activation energy of

1.84 eV over a large temperature range between 240 and 130 ˚C with tcrys between 100

µs and 10 s across 5 orders in time-scale. We compare tcrys with and without TDs

(Figure 6-4). A 75 µs long heating pulse at 240 °C is applied 100 µs after RESET

programming as a TD by the MTS and tcrys is measured afterwards. The measured tcrys

with TD shows a constant shift in log-scale time, which means that the ratio between

tcrys with and without TD is constant throughout large temperature range between 130

˚C and 240 ˚C. The 75 µs long heating pulse at 240 °C corresponds to ~40 % of tcrys at

240 °C, which corresponds to the ratio of difference in tcrys with and without TD (the

inset figure in Figure 6-4). When the heating pulse width is reduced to 25 µs, the ratio

is reduced accordingly. In most of retention measurements [3, 4], it has been assumed

that TDs at different temperatures and for different durations can be simply added.

Cur

rent

Time after heating starts

Figure 6-3: Schematic crystallization process for growth dominated material. Non-uniformity in

growth speed can result in multiple conduction paths.

120

Result in Figure 6-4 experimentally verifies this assumption for the first time.

Equation (1) summarizes this relationship between retention and TD.

∫= dttTvr crys ))(( (1)

where T(t) is the temperature as a function of time, vcrys(T) is the crystallization speed

as a function of temperature, and r is the degree of the crystallization between ‘0’ (no

crystallization) and ‘1’ (the formation of the crystalline conductive path). Once tcrys(T)

is experimentally found, vcrys(T) is given by the following equation.

)(/1)( TtTv cryscrys ==== . (2)

EA=1.84 eV

10µ

100µ

1m

10m

100m

1

10

100250 200 150

Cry

stal

lizat

ion

time

(s)

With thermal disturbance (TD) Without TD

T (°C)

22 24 26 281/k

BT (eV-1)

0.0

0.5

1.0150 200 250

Temperature (°C)

75 µs TD 25 µs TD1-

r(T

D)

Figure 6-4: Crystallization time (tcrys) with and without thermal disturbance (TD). For tcrys

with TD, cells are disturbed at 240 °C for 75 µs before annealing for crystallization.

Constant difference in log-scale crystallization time suggests that their ratio is constant. The

inset figure shows that given TD results in a fixed amount of crystallization between 130 and

240 °C, i.e. for at least 5 orders in time. ‘r’ is the degree of crystallization between ‘0’ (no

crystallization) and ‘1’ (the formation of the first crystalline conductive path).

121

In a cross-point array with diode selection devices, unselected cells can be reverse-

biased while being thermally disturbed by the adjacent selected cell. If the electric

field has an effect on the crystallization process, this can result in different tcrys and

retention behavior. Therefore we have measured tcrys dependence on electric field by

applying different amount of read bias on the PCM cell. Figure 6-5 shows that larger

read bias results in shorter tcrys. In other words, larger read bias shifts the curve in

Figure 6-5 to the right by temperature difference less than 30 °C. This small difference

in temperature can be attributed to the Joule heating in the phase-change material by

the read bias. The Joule heating caused by the read bias is usually insignificant

because RESET state is highly resistive. However, the Joule heating in the phase-

change material becomes significant at higher temperatures because amorphous phase-

10µ

100µ

1m

10m

100m

1275 250 225 200

Read bias (V) 0.1 0.2 0.3 0.4

Cry

sta

lliza

tion

tim

e (s

)

T (°C)

1/kBT (eV-1)

21 22 23 24 25

Figure 6-5: Crystallization time dependence on read bias between 0.1 and 0.4 V. Curves

are shifted to right as read bias increases. Temperature difference caused by Joule heating

in phase-change material is responsible for differences.

122

change material becomes much more conductive as temperature increases [5].

Therefore, the actual temperature of the programmed region is higher than the

temperature set by the MTS heater due to Joule heat generated in phase-change

material, which explains the temperature shift in Figure 6-5. The direct dependence of

tcrys on the electric field itself has not been observed for read biases between 0.1 and

0.4 V.

6.3.2 RESET Resistance and Threshold Switching Voltage Drift

TD can cause changes in RRESET and Vth in two different ways. First, if TD changes the

temperature of the cell when RRESET and Vth are read, the measurement results will

change even when amorphous region has the same trap density. Second, TD can cause

difference in trap densities because the drift behavior is expedited at high temperatures

RESET Prog.

The PCM cell

The MTS heater

Read pulse (RRESET, Vth,

tcrys)

tAtB

tA : Delay time for readtB : Delay time for annealing (or thermal disturbance)

Figure 6-6: Pulse input profiles for the phase-change memory cell (top) and micro-thermal

stage heater (bottom). tA: The delay time between the RESET programming event and the

read event. tB: The delay time between the RESET programming event and the TD (or

annealing) event. Read pulse shapes are determined by properties to be measured and reading

temperature (TR).

123

causing faster trap decay. Difference in trap densities will result in different RRESET and

Vth even though they are read at the same temperature.

First, we investigate how much effect TD has on RRESET drift and how it depends on

the delay time between the RESET programming event and the TD event. Electrical

pulses applied to the PCM cell and the MTS heater are shown in Figure 6-6. Though

not intuitive, the well-known structural relaxation (SR) model [10, 13] suggests that 1)

the same amount of annealing (temperature and duration) has the largest impact on

instantaneous RRESET if the delay time for annealing (‘tB’ in Figure 6-6) is the shortest,

2) the accelerated drift caused by annealing results in slowing down of the drift right

afterwards, and 3) final value of RRESET would not depend on the delay time for

annealing (‘tB’ in Figure 6-6) if the amount of annealing is the same. All these implicit

inferences of the SR model are verified experimentally for the first time in the

)/log()/log(

12

12

tt

RR====γγγγ

100µ 1m 10m 100m 1 100.00

0.05

0.10

0.15

0.20

Drif

t coe

ffici

ent

Delay time for read (s)

Delay time for annealing 300 µs 1.2 ms 11 ms 110 ms no annealing

10µ 100µ 1m 10m 100m 1 10 100

1M

2M

3M

RR

ES

ET (

Ω)

Delay time for read (s)

Delay time for annealing 300 µs 1.2 ms 11 ms 110 ms

Figure 6-7: (a) RESET resistance (RRESET) and (b) drift coefficient (γ) for the same amount of

annealing (60 °C for 600 µs) with different delay times for annealing. Resistances are measured at

room temperature. Each data point is averaged over 150 measurements. Annealing at the shortest

delay time (300 µs) increases RRESET by 25 % instantaneously (‘A’), while annealing at larger

delays shows much less increase for RRESET. ‘B’: Instantaneous drift coefficient increases more if

the delay time for annealing is shorter. ‘C’: Drift coefficient is reduced right after annealing.

124

following experiments. PCM cells in the RESET state are annealed with the MTS

heater at 60 ˚C for 600 µs and the delay time for annealing (‘tB’ in Figure 6-6) is

varied between 300 µs and 110 ms. Cell resistances are measured at room temperature.

Figure 6-7(a) shows that TD at the shortest delay time for annealing (300 µs, black

squares) has the largest effect resulting in ~25% increase for instantaneous RRESET right

after annealing. On the other hand, TD at 1.2 ms causes smaller increase and TD at 11

ms and 110 ms do not cause any meaningful RRESET increase. Therefore, TD at earlier

delays after RESET programming should be prevented to reduce variation in RRESET.

In addition, when the drift coefficient is significantly increased by annealing, the drift

10µ 1m 100m 10 1k0.8

1.0

1.2

1.4

Vth (

V)

Delay time for read (s)

TA :

25 °C 35 °C 45 °C 55 °C 65 °C

mV 6856

)log(0

−=

=∆

α

αt

tVth

Figure 6-8: Threshold switching voltage (Vth) drift dependence on annealing temperature (TA).

Annealing at the elevated temperature makes Vth drift faster resulting in higher Vth at the given

time after RESET programming. Cells are programmed and Vth is measured at room

temperature. Annealing started at 1 µs after RESET programming and the PCM cell is brought

back to room temperature before Vth measurement. The inset equation describes the Vth drift

behavior where α is the Vth drift coefficient which increases as TA increases.

125

coefficient right afterwards gets lower than normal as can be seen from data ‘C’ in

Figure 6-7(b). This is because traps with certain activation energy already decayed

earlier during annealing and there is less number of traps remaining that would have

decayed right after annealing. However, the drift coefficient is recovered long time

after annealing because traps that decay at that time-scale have large activation

energy and the impact of short TD on those traps can be ignored due to their large

activation energy. Finally, RRESET measured at the same delay time for read (‘tA’ in

Figure 6-6) is the same if the amount of annealing (temperature and duration) is the

same regardless of their differences in delay time for annealing (‘tB’ in Figure 6-6), as

can be seen from Figure 6-7(a), e.g. two samples with 300 µs and 1.2 ms of delay time

for annealing merge into the same RRESET at 10 ms. This is because each trap has its

own decay time constant which depends only on temperature regardless of the delay

time.

126

We experimentally show that measured Vth and its drift are affected by TD as well.

Figure 6-8 shows the effect of annealing on Vth drift. Vth is measured at room

temperature by a triangular pulse that ramps up. When the voltage amplitude ramps

and reaches at Vth of the PCM cell, the current through the PCM cell suddenly

increases. The measurement results clearly show that Vth drifts in time and it drifts

faster at higher annealing temperatures. Vth dependence on measurement temperature

is shown in Figure 6-9. PCM cells are not annealed but the temperature is raised by the

MTS heater right before the measurement. Results clearly show that measured Vth

decreases as measurement temperature increases even though they have the same trap

density. Reduced Vth by TD can be problematic for reliable writing operation of the

PCM array. When the selected cell is being programmed, adjacent cells are thermally

25 50 75 1000.6

0.7

0.8

0.9

1.0

1.1

1.2

Vth (

V)

Reading temperature (TR) (ºC)

Delay time (read) 100 µs 1 ms 10 ms 0.1 s 1 s 10 s 100 s

Figure 6-9: Threshold switching voltage (Vth) dependence on reading temperature

(TR) for various delay time for read. Vth decreases as TR increases due to increased

conductivity at higher TR.

127

disturbed while they are in reverse bias. If the amount of reverse bias is larger than the

reduced Vth, adjacent cells in the RESET state can be switched to the partial SET state.

Combining these effects of TD on Vth, current measurement data show that TD at

65 °C alone could lead to ~100 % variation (from 1.4 V to 0.7 V) in Vth.

6.3.3 Multi-Bit Operation

Random TD can be harmful to robust operation of multi-bit memory cells by causing

larger RRESET and Vth variations [14]. However, if we deliberately use the large effect

of annealing in early delays on drift, we can make multi-bit operation more reliable by

suppressing the amount of drift. Figure 6-10 shows that 600 µs long annealing at 300

µs delay and 60 ˚C provides 25 % larger room in resistance for middle resistance

levels at 1 ms delay. The temperature and duration of annealing can be optimized for

the largest resistance margin with minimum energy consumption and the smallest

reduction in retention time.

128

6.4 Conclusion

Using a novel measurement structure called the micro-thermal stage (MTS), we study

thermal disturbance (TD) effect on not only retention but also RESET resistance

(RRESET) and threshold switching voltage (Vth) variations. We experimentally verify

how to add up the impacts of TD on retention. We show that TD can cause at least

25% variation in RRESET and 100% in Vth. Experimental results support details of the

structural relaxation model with distributed activation energy. We propose a scheme to

deliberately use this TD effect to make larger resistance margin for multi-level

operation.

0 1M 2M 3M0.1

1

5102550759095

99

99.9

Dis

trib

utio

n (%

)

Resistance (Ω)

Annealed Not annealed

∆RRESET

=~200 kΩ

SET Resistance (~3 kΩ)

Figure 6-10: Larger resistance margin is achieved by annealing the cell. The RESET

resistance is measured at 1ms after programming. The additional margin is ~25% larger

by annealing the cell at 60 °C between 300 and 900 µs delay (for 600 µs). The widened

margin can be utilized for robust multi-level operation.

129

Bibliography

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mixed-scaling approach,” IEEE Trans. Electron Devices, vol. 55, no. 2, pp. 515-

522, 2008.

[5] D. Ielmini, and Y. Zhang, “Analytical model for subthreshold conduction and

threshold switching in chalcogenide-based memory devices,” J. Appl. Phys., vol.

102, p. 054517, 2007.

[6] D. Ielmini, “Threshold switching mechanism by high-field energy gain in the

hopping transport of chalcogenide glasses,” Phys. Rev. B, vol. 78, p. 035308, 2008.

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“Low-field amorphous state resistance and threshold voltage drift in chalcogenide

materials,” IEEE Trans. Electron Devices, vol. 51, no. 5, pp. 714-719, 2004.

130

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[9] D. Ielmini, D. Sharma, S. Lavizzari, and A. L. Lacaita, “Reliability impact of

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Experimental study,” IEEE Trans. Electron Devices, vol. 56, no. 5, pp. 1070-1077,

2009.

[10] S. Lavizzari, D. Ielmini, D. Sharma, and A. L. Lacaita, “Reliability impact of

chalcogenide-Structure relaxation in phase-change memory (PCM) cells-Part II:

Physics-based modelling,” IEEE Trans. Electron Devices, vol. 56, no. 5, pp. 1078-

1085, 2009.

[11] D. Ielmini and M. Boniardi, “Common signature of many-body thermal

excitation in structural relaxation and crystallization of chalcogenide glasses,”

Appl. Phys. Lett., vol. 94, p. 091906, 2009.

[12] D. Tio Castro et al., “Evidence of the thermo-electric thomson effect and

influence on the program conditions and cell optimization in phase-change

memory cells,” in IEDM Tech Dig., pp. 35-38, 2007.

[13] D. Ielmini, S. Lavizzari, D. Sharma, and A. L. Lacaita, “Temperature

acceleration of structural relaxation in amorphous Ge2Sb2Te5,” Appl. Phys. Lett.,

vol. 92, p. 193511, 2008.

[14] D.-H. Kang et al., “Two-bit cell operation in diode-switch phase change

memory cells with 90nm technology,” in VLSI Symp. Tech. Dig., pp. 98-99, 2008.

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Chapter 7

Conclusion

7.1 Summary of Contributions

This thesis addresses issues related to scalability and reliability of phase change

memory (PCM) using various methods spanning theoretical analysis and modeling,

design and fabrication of novel structures, and measurement and characterization of

devices.

The focus of this thesis is on scalability from chapter 2 to chapter 4. In chapter 2,

theoretical analysis based on energy conservation theory shows that PCM follows

constant voltage scaling rule whether scaling is isotropic or non-isotropic. Minimum

programming voltage is set by electrical resistivity and thermal conductivity of phase

change material. In case of isotropic scaling, the thermal diffusion length between

adjacent cells is scaled by the same scaling factor, relieving concerns for thermal

disturbance between scaled cells.

Chapter 3 (in collaboration with Yuan Zhang) presents experimental work on

fabrication and characterization of PCM single cells integrated with Ge nanowire

diodes. In-situ doped Ge nanowire diodes grown by vapor liquid solid (VLS)

mechanism using Au as catalyst show on/off ratio of ~100 which can be used to build

a PCM array as large as 64 by 64. Ge2Sb2Te5 is directly contacted by Ge nanowire, the

diameter of which is only 40 nm. Small contact size results in small programming

current below 200 and 50 µA for RESET and SET respectively. This work illustrates

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the combination of bottom-up synthesis (Ge nanowire) with top-down conventional

device fabrication techniques on a full wafer scale. The growth temperature of Ge

nanowire is below 400 °C, which makes Ge nanowire diodes promising candidate for

selection device of 3D memory architecture.

Chapter 4 (in collaboration with Byoung-Jae Bae) studies scaling of both device

characteristics and material properties of PCM. For this purpose, a novel PCM cell

with a pseudo terminal is designed and fabricated. The PCM cell with the pseudo

terminal successfully relates the observed properties to the thickness of amorphous

region, enabling accurate scaling study of Ge2Sb2Te5. Measurement results on

threshold switching voltage (Vth) show that Vth linearly scales with thickness and is

extrapolated to non-zero Vth at the zero thickness. Drift measurement of Vth reveals

that threshold switching field drifts proportional to logarithm of time while

extrapolated Vth at zero thickness does not drift. The drift coefficient for RESET

resistance does not depend on the thickness. This suggests that the drift behavior

which is potentially harmful for multibit operation will still exist in scaled PCM cells.

Resistance vs. temperature measurement shows that the crystallization temperature

increases for thinner amorphous GST, which suggests that retention might be

improved for scaled PCM cells.

This thesis focuses on reliability from chapter 5 to chapter 6. In chapter 5, we measure

the RESET resistance (RRESET) and threshold switching voltage (Vth) drift behavior and

its temperature dependence in microseconds time scale using a novel measurement

structure, the micro-thermal stage (MTS). We find that the drift coefficient is

proportional to annealing temperature when the annealing temperature does not

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change during measurement. We derive and experimentally verify the analytical

expression that can explain the drift behavior when the annealing temperature changes

during measurement. This analytical expression will lead to better assessment of the

thermal disturbance effect on the RRESET and Vth drift and resultant variations in them.

In chapter 6, the impact of thermal disturbance (TD) on PCM characteristics is

presented using the micro-thermal stage (MTS). Experimental results show that the

short temperature rise caused by TD can cause not only retention deterioration but also

RESET resistance (RRESET) and threshold switching voltage (Vth) variations. Methods

on how to add up the impacts of TD on retention is verified experimentally. TD can

cause at least 25% variation in RRESET and 100% in Vth. A scheme to deliberately use

this TD effect to make larger resistance margin for multi-level operation is proposed.

7.2 Recommendations for future work

7.2.1 Toward 3D Integration of PCM cells with Ge Nanowire

Diodes as Selection Devices

To build a memory array with Ge nanowire diodes as selection devices, more work

needs to be done on engineering the substrate which we grow nanowires from. The

yield of defect-free vertical nanowire growth highly depends on characteristics of

substrate. In current work shown in chapter 3, nanowires are grown from silicon (111)

substrate to maximize the yield. To integrate nanowires in 3D structure, these

substrates need to be repeated to form layers of nanowires. Processing temperature of

building substrate layers should be minimized such that it does not degrade existing

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structures and devices. The characteristics of substrates which impact the yield of

nanowires need to be indentified and optimized for 3D integration.

7.2.2 Modeling the Drift Behavior of RESET Resistance and

Threshold Switching Voltage Based on New Findings of its

Thickness Dependence

The 1D thickness scaling study in chapter 4 includes new findings on the drift

behavior of RESET resistance and threshold switching voltage. It shows that thinner

amorphous region has the same drift coefficient for RESET resistance, while a few

literatures reported that the drift coefficient decreases for smaller amorphous region.

This motivates further study on the drift mechanism to explain the observed

differences. The difference can be attributed to many different factors including

material, device structure, mechanical stress, interface effects and programming

scheme. Thickness dependence of threshold switching voltage drift also identifies

threshold switching field drift as a main cause for threshold voltage drift. This

observation can lead to development or refinement of not only drift model but also

threshold switching model.

7.2.3 Statistical Analysis on Drift Behavior

The statistical variation on the drift behavior can pose more serious reliability problem

than the drift behavior itself. In addition to the detailed study on the drift behavior and

its temperature dependence in chapter 5, more understanding on its statistical nature

and cause for variation is needed to fully estimate the reliability impact of the drift.

One may need a series of measurements on a large array with PCM cells or repetitive

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measurements on a single PCM cell to perform statistical analysis. Final goal would

be assessment and development of techniques to manage statistical variations on the

drift.

7.2.4 Thermal Disturbance Effect on the Array and Chip level

Chapter 6 presents possible impacts of thermal disturbance on a single cell level.

Based on the actual memory application of the memory chip, extent and frequency of

thermal disturbance can be largely different. Phase change memory is still open for a

wide range of future applications including NAND Flash like applications and DRAM

like applications. For given application, the actual impact of thermal disturbance on

chip level operation needs to be evaluated. For applications that do not need frequent

write, thermal disturbance impact might be ignored. On the other hand, applications

that need frequent write might allow large thermal disturbance impact which should be

mitigated by increasing thermal resistances between cells. Special writing schemes

similar to wear-leveling writing schemes in Flash memory can be used as well to

prevent frequent writing near one cell.

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Appendix A

Pulse Measurement Design

Phase change memory programming requires a pulse programming as opposed to a dc

programming because electrical power that melts the phase change material should be

turned off fast enough to form the amorphous region typically within few tens of

nanoseconds. In addition, short-time characterization of the drift behavior of phase

change memory which is enabled by the measurement using pulses is very useful for

in-depth study of the drift behavior because the drift behavior is initiated right after

programming within less than few µs. Throughout this dissertation, various pulse

measurement techniques are applied to study various aspects of phase change memory.

In this appendix, we present theoretical backgrounds and practical details of pulse

measurement techniques.

A.1. Theoretical Background

In electrical testing setups, pulses are delivered by coaxial cables which are treated as

transmission lines in the circuit analysis. One of the main characteristic parameters of

coaxial cables is the characteristic impedance which is typical 50 Ω. Having the same

unit as resistors in the circuit theory, one may be misled to treat transmission lines as

resistors and reach an inaccurate conclusion.

The voltage signal is “applied” across the resistor. However, in the transmission lines,

the voltage signal (pulse) is “delivered” by the transmission line. The voltage pulse on

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the transmission line is transmitted with accompanying current pulse, the amplitude of

which is determined by the characteristics impedance by the following equation.

0/ ZVI pulsepulse = (1)

where Ipulse, Vpulse, and Z0 are the amplitude of the current pulse and voltage pulse and

the characteristic impedance of the transmission line, respectively. Since the

transmission line literally transmits the electrical pulse, one may calculate the time it

takes to transmit the electrical signal from the one end of the cable to the other end of

the cable – or propagation speed in the transmission lines. The propagation speed is in

the same order as the speed of light which travels ~30 cm in 1 ns. For example, when

the pulse generator sends out the electrical pulse through a 30-cm-long coaxial cable,

the electrical pulse arrives at the other end of the transmission line after ~1 ns.

Then what happens to the electrical signal when it reaches at the end of the

transmission line and encounters other circuit elements such as resistors, capacitors,

other transmission lines, and etc? The voltage pulse at the node will induce electrical

current to flow in the encountered circuit elements and the amount of the current will

be determined by the amplitude of the transmitted voltage pulse and the characteristics

of each circuit element such as the resistance of a resistor. If the sum of generated

electrical current is the same as amplitude of the transmitted current pulse, all of the

transmitted electrical current is successfully transmitted through the node. This occurs

when the combined impedance of encountered circuit elements are the same as the

characteristic impedance of the transmission line that delivered the pulse. Therefore,

this behavior is typically called ‘impedance match’.

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However, if the sum of generated electrical current is different from the amplitude of

the transmitted current, the excess (or shortfall) current should be delivered out from

the node (or into the node) to satisfy the continuity of electrical currents. This requires

that the additional voltage is generated at the node, which can initiate pulses to be

transmitted through the transmission lines out of the node. The same transmission line

that just delivered the electrical pulse is also influenced by the generated voltage at the

node and forced to transmit another pulse to the opposite direction. This behavior is

typically called ‘reflection’. The amount of the generated voltage or the amplitude of

the reflected pulse can be derived by the following.

0Z

V

Z

V

Z

VI reflected

L

reflected

L

pulsepulse +=− (2)

where ZL is the combined impedance of other circuit elements at the node and Vreflected

is the amplitude of the reflected voltage pulse which is the same as the amplitude of

the generated additional voltage at the node. Combining (1) and (2), Vreflected is given

by

pulseL

Lreflected V

ZZ

ZZV

0

0

+−= . (3)

The voltage at the node, Vnode is given by

pulseL

Lpulsereflectednode V

ZZ

ZVVV

0

2

+=+= . (4)

We will continue to investigate how these theories can be applied to the typical pulse

test setup for phase change memory devices.

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A.2. Pulse Test Setup Design

The SET resistance of typical phase change memory (PCM) cell is few kilo-ohms

resulting from the resistivity of the crystalline phase of the phase change material.

Therefore, in a simple configuration shown in Figure A-1(a), where a pulse generator

sends a pulse to a PCM cell through a coaxial cable (transmission line with Z0=50 Ω),

the pulse is reflected at the node with almost the same voltage amplitude as the

originally transmitted pulse. (Equation (3) shows that pulsereflected VV ≅ when ZL>>Z0.)

As a result, the actual voltage that is applied to the PCM cell is twice as large as the

amplitude that is applied by the pulse generator. (Equation (4) shows that

pulsenode VV 2≅ when ZL>>Z0.) This reflection is not a serious issue by itself as long as

one realizes that the pulse is being reflected. One might speculate whether the

reflected pulse is reflected again when it is transmitted back to the other end of the

coaxial cable and encounters the pulse generator. The internal resistance of the pulse

generator output channel is typically 50 Ω which prevents the reflected pulse from

Figure A-1: (a) Typical PCM memory testing setup with one pulse generator. (b) PCM memory

testing setup with two pulse generators. (c) PCM memory testing setup with one pulse generator

and one oscilloscope.

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being reflected again. If the pulse generator provides an option for choosing the

internal resistance, it is recommended to carefully set it at 50 Ω to prevent pulses from

being reflected back and forth and increasing the settling time.

Even though the simple setup in Figure A-1(a) works well for most types of

measurements on phase change memory, some of carefully designed pulse

measurement requires multiple pulse generators (or output channels). For example, the

voltage pulse shown in Figure 5-4 requires two pulse generators (or output channels)

to be connected to the PCM cell. Figure A-1(b) shows such setup. How will pulses be

transmitted in this setup? When the pulse that was transmitted from the pulse

generator ‘A’ reaches the node, it encounters two circuit elements. One is the phase

change memory cell (i.e. a resistor) and the other is also the transmission line that is

connected to the pulse generator ‘B’. The combined impedance of these two elements

is almost 50 Ω because the resistance of the PCM cell is much larger than 50 Ω and

large resistances can be ignored in the parallel resistance network. Therefore, the pulse

is not reflected because it is almost perfectly impedance matched. In this setup, the

voltage amplitude that is applied to the PCM cell is almost identical to the voltage

amplitude of the pulse that is generated by the pulse generator. Therefore, two pulse

generators (or output channels) can work together to apply various types of pulses to

the PCM cell without any reflection.

The configuration shown in Figure A-1(b) is also useful for monitoring voltage pulses

with the oscilloscope. A measurement setup in which one of the pulse generators are

replaced by the oscilloscope is shown in Figure A-1(c). The voltage at the node is

delivered to the oscilloscope as it is and no reflection occurs at the oscilloscope by

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setting the input resistance of the oscilloscope to be 50 Ω. Therefore, in this setup, the

oscilloscope not only monitors the actual voltage applied to the PCM cell but also

serves as an impedance match which makes the measurement setup easier to

understand.

A.3. Resistance Measurement of the RESET State Using Short

Time Pulse

To measure the resistance of the RESET state in a short time, we need to use the

electrical pulse to measure the resistance. By measuring the current while applying the

voltage pulse with the known amplitude, the resistance can be determined.

Unfortunately, there is no single equipment that we can simply connect and measure

the current within a short time around a few microseconds. Reading the RESET

Figure A-2: (a) A PCM memory cell with added resistor connected in series with PCM. (b) A

PCM memory cell connected to the virtual ground node of the current-to-voltage amplifier. The

effect of the parasitic capacitor on the quenching time is minimized.

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resistance of the PCM cell is even more challenging since the current can be less than

few microamperes for the given read voltage.

The most common setup to read such a large RESET resistance is to add an external

series resistor to the PCM cell as shown in Figure A-2(a). By measuring the voltage

drop across the external resistor using oscilloscope, the current pulse that is passing

through the PCM cell can be measured. However, this setup has some undesirable

issues for PCM testing. Due to the large parasitic capacitance, Cpara, at the node

between the PCM cell and the external resistor, the pulse transition can be slowed

down by the RC delay. This makes it difficult to RESET program the cell since the

voltage at the node cannot be removed immediately which results in slow quenching

speed. To mitigate the RC delay, large resistance cannot be added as the external

resistor, which results in voltage that is not large enough to be read by the oscilloscope.

Therefore, we use the current-to-voltage amplifier to measure the RESET resistance as

shown in Figure A-2(b).

The PCM cell is connected to the virtual ground node of the current-to-voltage

amplifier. Therefore, even if Cpara exists at the node, it does not slow down the

quenching speed. Without worrying about the RC delay, we can add the large

resistance to the amplifier which results in large voltage signal that can be read by the

oscilloscope easily. The RESET resistance can be read within 10 µs with the current-

to-voltage amplifier which has the bandwidth of ~200 kHz.

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List of Publications

Journal Articles

SangBum Kim, Byoung-Jae Bae, Yuan Zhang, Rakesh Gnana David Jeyasingh,

Youngkuk Kim, In-Gyu Baek, Soonoh Park, Seok-Woo Nam, and H.-S. Philip

Wong, “1D Thickness Scaling Study of Phase Change Material (Ge2Sb2Te5)

using a Pseudo 3-Terminal Device,” (in preparation - IEEE Transaction on

Electron Devices).

SangBum Kim, Byoungil Lee, Mehdi Asheghi, G.A.M. Hurkx, John

Reifenberg, Kenneth Goodson, and H.-S. Philip Wong, “Resistance and

Threshold Switching Voltage Drift Behavior in Phase-Change Memory and

Their Temperature Dependence at Microsecond Time Scales Studied Using a

Micro-Thermal Stage,” (in preparation - IEEE Transaction on Electron

Devices).

H.-S. Philip Wong, Simone Raoux, SangBum Kim, Jiale Liang, John P.

Reifenberg, Bipin Rajendran, Mehdi Asheghi, Kenneth E. Goodson, "Phase

Change Memory", Proceedings of the IEEE, (in press).

SangBum Kim, Stephen L. Brown, Stephen M. Rossnagel, John Bruley,

Matthew Copel, Marco Hopstaken, Vijay Narayanan, and Martin M. Frank,

“Oxygen migration in TiO2-based higher-k gate stacks,” Journal of Applied

Physics, vol. 107, no. 5, p. 054102, 2010.

John P. Reifenberg, Kuo-Wei Chang, Matthew A. Panzer, SangBum Kim,

Jeremy A. Rowlette, Mehdi Asheghi, H.-S. Philip Wong, and Kenneth E.

144

Goodson, “Thermal boundary resistance measurements for phase-change

memory devices,” IEEE Electron Device Letters, vol. 31, no. 1, pp.56-58, Jan.

2010.

M. M. Frank, S. Kim, S. L. Brown, J. Bruley, M. Copel, M. Hopstaken, M.

Chudzik, and V. Narayanan, “Scaling the MOSFET gate dielectric: From high-

k to higher-k? (Invited Paper),” Microelectronic Engineering, v.86, pp.1603-

1608, 2009.

S. Kim, Y. Zhang, J. P. McVittie, H. Jagannathan, Y. Nishi, and H.-S. P. Wong,

“Integrating phase-change memory cell with Ge nanowire diode for crosspoint

memory – Experimental demonstration and analysis,” IEEE Transaction on

Electron Devices, vol.55, no.9, pp.2307-2313, Sep. 2008.

J. P. Reifenberg, M. A. Panzer, S. Kim, A. M. Gibby, Y. Zhang, S. Wong, H.-

S. P. Wong, E. Pop, and K. E. Goodson, "Thickness and stoichiometry

dependence of the thermal conductivity of GeSbTe films," Applied Physics

Letters, vol.91, 111904, 2007.

SangBum Kim, and H.-S. Philip Wong, “Analysis of Temperature in Phase

Change Memory Scaling,” IEEE Electron Device Letters, vol.28, no.8, pp.697-

699, Aug. 2007.

Conference Presentations

SangBum Kim, Byoungil Lee, Mehdi Asheghi, G.A.M. Hurkx, John

Reifenberg, Kenneth Goodson, and H.-S. Philip Wong, “Thermal disturbance

and its impact on reliability of phase-change memory studied by micro-thermal

145

stage,” IEEE International Reliability Physics Symposium (IRPS), Anaheim,

CA, May 2-6, 2010.

SangBum Kim, Rakesh Jeyasingh, John Reifenberg, Jaeho Lee, Mehdi

Asheghi, Kenneth Goodson, and H.-S. Philip Wong, "Electrical and Thermal

Contact Resistance of the Phase-Change Material Cycled by Micro-thermal

Stage," Materials Research Society (MRS) Spring Meeting, Symposium H,

session H-5.6, April 5-8, 2010.

Byoung-Jae Bae, SangBum Kim, Yuan Zhang, Youngkuk Kim, In-Gyu Baek,

Soonoh Park, In-Seok Yeo, Siyoung Choi, Joo-Tae Moon, H.-S. Philip Wong,

and Kinam Kim, “1D thickness scaling study of phase-changing material

(Ge2Sb2Te5) using a pseudo 3-terminal device,” IEEE International Electron

Devices Meeting (IEDM), session 5.2, Dec 7 - 9, 2009.

J. P. Reifenberg, K. Chang, M. A. Panzer, S. Kim, J. A. Rowlette, M. Asheghi,

H.-S. P. Wong, and K. E. Goodson, “Thermal Boundary Resistance between

Phase-Change Memory Materials Ge2Sb2Te5 and TiN,” Materials Research

Society (MRS) Fall Meeting, Symposium CC, session CC-5.8, November 30 –

December 4, 2009.

SangBum Kim, Yuan Zhang, Byoungil Lee, Marissa Caldwell, and H.-S.

Philip Wong, “Fabrication and characterization of emerging nanoscale

memory,” invited paper, IEEE International Symposium on Circuits and

Systems (ISCAS), May 24 - 27, 2009.

Y. Zhang, S. Kim, B. Lee, M. Caldwell, H.-S. P. Wong, “Fabrication and

Characterization of Emerging Nanoscale Memory,” invited paper,

146

International Disk Drive Equipment and Materials Association (IDEMA)

Technical Symposium, “What's in Store for Storage, The Future of Non-

Volatile Technologies,” San Jose, CA, paper 5.3, December 11, 2008.

S. Kim, M. M. Frank, S. L. Brown, S. M. Rossnagel, M. Copel, and V.

Narayanan, “Buffered TiO2 Higher-k Gate Dielectrics with TiN Metal Gate:

Physical Characteristics and Device Performance for PVD-, ALD- and MBE-

grown Layers,” Materials Research Society (MRS) Spring Meeting,

Symposium H, session H-3.6, March 24 - 27, 2008.

J. Reifenberg, S. Kim, Y. Zhang, E. Pop, H.-S. P. Wong, and K. Goodson,

“Phase Transitions and Thermal Properties in GeSbTe (2:2:5),” invited talk,

Materials Research Society (MRS) Spring Meeting, Symposium II, session II-

2.4, April 10 - 13, 2007.

SangBum Kim, and H.-S. Philip Wong, “Generalized Phase Change Memory

Scaling Rule Analysis,” IEEE Non-Volatile Semiconductor Memory Workshop,

Monterey, CA, Feb. 2006.

Y. Zhang, S. Kim, J. P. McVittie, H. Jagannathan, J. B. Ratchford, C. E.D.

Chidsey, Y. Nishi, and H.-S. P. Wong, “An Integrated Phase Change Memory

Cell with Ge Nanowire Diode for Cross-Point Memory,” Symposium on VLSI

Technology 6B-2, Kyoto, Japan, 2007.

147

Author’s Biography

SangBum Kim was born in Seoul, Korea. He received the B.S. degree from Seoul

National University, Seoul, Korea, in 2001, and the M.S. degree from Stanford

University, Stanford, CA, in 2005, all in electrical engineering. He received Samsung

scholarship and KFAS scholarship (The Korean Foundation for Advanced Studies)

from 2005 to 2009 and from 2003 to 2005 respectively. He is expected to get his Ph.D.

degree in electrical engineering at Stanford University, Stanford, CA, USA. He has

hold intern positions at SAIT (Samsung Advanced Institute of Technology) and IBM

T. J. Watson Research Center in 2007.

His Ph.D. project at Stanford was carried in the Nanoelectronics group directed by

Prof. H.-S. Philip Wong. SangBum Kim’s research focuses on fabrication and

characterization of novel phase-change memory (PCM) structures with reduced

programming power and cell size, and measurement of phase-change material

properties to understand how they can affect PCM operation.