SC200x Peripherals Broadband Entertainment Division DTV Source Applications July 2001

SC200x PeripheralsSC200x Peripherals

Broadband Entertainment Division

DTV Source Applications

July 2001

SC200x Peripherals - July 20018-2LSI Logic Confidential

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Agenda for PeripheralsAgenda for Peripherals

Peripheral system overview DMA module UART interface SmartCard interface I2C interface IEEE 1284 interface Infrared interface Teletext interface GPIO pins Modem interface


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Peripheral System OverviewPeripheral System Overview

I-BUS

Chip external signals

Interrupts

SUB-modules

and

Interfaces

Control

Interrupts

DMA-Requests

S-BUS

Soft reset

Arbiter


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Peripheral System DetailPeripheral System Detail

AuxPort

Two DMA

UART 1 InfraredI/O

IEEE1284

SmartCard 1

SmartCard 0 UART 0 Modem Teletext Serial GPIO

Controllers

I-Bus I-Bus

S-Bus

To TransportSubsystem

I-Bus

To CPUSubsystem

To SDRAMController

To Mixer/EncoderSubsystem

Peripheral InterfacesSubsystem

ControlModule and

Host


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Peripheral InterruptsPeripheral Interrupts

Peripheral Interrupt Status Two status/enable/acknowledge registers All peripheral interrupts are route to 15 I-Bus interrupts

Submodule peripheral reset control is provided


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DMA ModuleDMA Module

Two DMA channels Each one has an RX and TX engine

All engines operate concurrently Handles DMA transfers between SDRAM-B and UART 0/1,

SmartCard 0/1 or 1284 port Automatically checks RX and TX ready status in the

required peripheral Peripheral interrupts can be disabled DMA interrupts should be enabled


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UART InterfacesUART Interfaces

Two identical UART Interfaces U0 and U1 Subset of the industry standard 8251 UART Asynchronous, Full Duplex operation Built in Baud Rate Generator (BRG) providing TX and RX clock 16-byte TX and RX FIFOs Operation

Each UART has the following pins: TXD - Transmit Data, RXD - Receive Data, RTS - Request to Send,

CTS - Clear to Send, DTR - Data Terminal Ready, DSR - Data Set Ready

IRDA modulator/demodulator mode support requires external transmit/receive device


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UART

Baud RateGenerator

External SC2005

Registers

I-Bus

TXD0

RXD0Interface

Data/Control

ModemCTSn0

RTSn0

DSRn0

DTRn0

TXC = RXC

CPUInterrupt

IRQ

Control

Control IRDAFilter

Serial DeviceOr Modem

UART Block DiagramUART Block Diagram


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Modem InterfaceModem Interface

Interfaces to proprietary Codecs (available from SGS-Thomson and Analog Devices)

Used by the on-chip soft modem (2400 baud, V.22bis), which is controlled by the internal CPU

SCLK and Frame Sync are derived from the external Codec

Contains a 32 bit Shift Register controlled by the CPU Six wire interface shared with UART ports 16 bit samples are transferred synchronously after each

Frame Sync The CPU can DMA blocks of data from this interface


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SmartCard InterfacesSmartCard Interfaces

Two SmartCard Interfaces are available S0 and S1 For SmartCards that adhere to ISO7816

Each SmartCard Interface has the following:- Programmable Clock generation Programmable Baud Rate Generator (BRG) Supports T=0 and T=1 Asynchronous protocol types 16-byte deep TX and RX FIFOs Detection of Unresponsive cards Detection of the insertion and removal of cards External SmartCard Coupler required


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4 reset methods available:- Global Reset SmartCard Interface Software Reset SmartCard Card Reset SmartCard RX FIFO/TX FIFO Reset

Clock Generator provides several clock frequencies: 54MHz /2 ../3 ../4 ../6 ../8 ../12 ../16

SmartCard typically uses a Baud rate of Clock/372 SmartCard Interface generates an even parity bit when

transmitting (bug in parity detection being fixed in SC2005-A)


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New for SC2005 NDS SmartCard module (shares pins with SmartCard 0)

Pin AF15 (formerly a NC pin) is now defined as the SC0_VPP_EN pin

Frequency lock for NDS mode (four possible values) SmartCard 0 defaults to the SC2000 compatible mode

Irdeto CA protocol is added, along with a 6 MHz option SmartCard Watchdog timer enhancements

Counter increased to 24 bits Second watchdog register added Allows efficient switching between multiple wait times used for

unresponsive card detection


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The watchdog timer consists of a 24-bit up-counter and 2 watchdog registers.

Counter starts counting ½ character after the parity bit

Timer can generate interrupt whenever count exceeds register timeout value


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Serial Host InterfaceSerial Host Interface

(Formerly called I2C) Operates in Master or Slave mode 2 wire (clock and data) bidirectional interface Two modes of operation, Philips 80C652 compatible or 4-

byte FIFO Multi-Master 8 bit Data-Shift Transfer Register Programmable bit rate Internal ‘spike’ filtering


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IEEE 1284 InterfaceIEEE 1284 Interface

Features Parallel I/O Port Operates as a peripheral slave device Support for internal DMA Controller

Operation Parallel I/O Port (PA) interrupts the CPU CPU reads the PA Registers CPU can set the PA to DMA mode CPU commands DMA Controller to start transactions The Parallel I/O Port asserts DMA requests The Parallel I/O Port sends/receives data through the DMA

Controller concurrent with IEEE1284 Interface activity


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IEEE 1284 InterfaceIEEE 1284 Interface

IEEE 1284 Parallel Port compliance The Port supports the following modes:

Compatible Mode Reverse (from SC2000 to host) data transaction in Nibble

Mode Reverse data transaction in Byte Mode Reverse and forward (from host to SC2000) data

transaction in ECP (Extended Capability Port) Mode.

RLE (Run Length Encoding) data compression/decompression supported

EPP Mode is NOT supported.


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Infrared InterfacesInfrared Interfaces

Two I/R Receivers IR0 and IR1 with the following features Configurable Receive Filter sample rate Configurable Level Change notification Time Stamping of each level change to the CPU Different Coding schemes are supported

Single I/R Transmitter IRT with the following features:- Configurable basic transmit bearer clock frequency Simple interface to the CPU for pulse and silence periods Double Buffering from the CPU Notification to the CPU if FIFO is not full

Both share signals with GPIO


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Infrared InterfacesInfrared Interfaces

Received signals are typically encoded to RC-5 where a binary 0 is represented by a high to low transition

A binary 1 is represented by a low to high transition The CPU sets up the software timer upon receipt of a command

start Hardware control over detection of level transitions A configurable clock divider is set to the default value of 675 The default line sampling clock is 80 kHz (54 MHz / 675) The CPU outputs line data via a Double Buffer FIFO so that it

can directly form the shape of the Amplitude Modulated signal The transmit clock of 36 kHz is derived from the 54 MHz clock

(/1500) The output line is driven low when the FIFO is empty


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Teletext InterfaceTeletext Interface

Two line interface - Teletext Data out and Teletext Request in (shared with GPIO pins)

64-byte Data FIFO (16 words each of 4 bytes) Direct Interface to the SDRAM Controller Programmable SDRAM fetch Start Address Transfers PES Format Teletext Data from SDRAM-B Block Length of 46 bytes (1 DVB Teletext Data Unit) FIFO Read Control handles requests from external device New Teletext Line fetches will start when there are 48

bytes free in the buffer


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Teletext Interface Block DiagramTeletext Interface Block Diagram

TeletextSerial Converter

TTXDATA

TTXREQ

SAA7183/82SC2005

Register FileI-Bus

S-Bus

InternalEncoder

DMAController

TeletextFIFO

OptionalExternalVideo Encoder


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GPIO PinsGPIO Pins

There are 50 General Purpose I/O pins (most are shared with other functions)

GPIO[16:0] UART, SmartCard, IR, I2C GPIO[23:17] Channel data GPIO[31:24] Dedicated GPIOs GPIO[49:32] 1284/Aux port

GPIO[31:28] can be used as interrupt inputs The GPIOs are configured as GPIO inputs at power up

Documents

SC200x Peripherals Broadband Entertainment Division DTV Source Applications July 2001