VDDNB

VCC_CORE_S0_10~1.55V 18A

667/800 MHzDDR2

0~1.55V 18A

667/800MHz

667/800MHzDDR2

ODD SATA

SATA

HDD SATA

USB3 Port

Camera

Mini USBBlue Tooth

USB

WinbondWPC775

KBC

TouchPad

INT.KB

BIOSWinbondW25X80

CONN.DEBUG

a/b/g/n

LPC BUS

LPC

Kedron

PCIex1Mini Card

TXFMGiga LANLAN

BCM5764

RJ45

PWR SWTPS2231

New card

LCD

CRT

ICS9LPRS480BKLFT 71.09480.A03RTM880N-796-VB-GRT 71.00880.A03

CLK GEN.

ALC268

Codec

G792

MIC In

INT MIC

MODEM

AZALIA

MDC Card

Line Out(No-SPDIF)

667/800 MHz

RJ11

14

8,9

8,9

3

24

24

23

23

22

15

272726

24

30

2928

2828

32

3131

31

30

30

Dolomites Block Diagram

32

INT.SPKR

OP AMPAPA205730

30

Title

Size Document Number Rev

Date: Sheet of

Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.

Dolomites SA

BLOCK DIAGRAMA3

1 43Monday, May 19, 2008

<Core Design>

REVISION : 08220-SAPCB P/N : 48.4Z701.001Project code: 91.4Z701.001

TOP

PCB STACKUP

BOTTOM

GND

S

S

VCC

SYSTEM DC/DC

INPUTS

5V_S5

SYSTEM DC/DC

DCBATOUT

OUTPUTS37

5V_S5(6A)

TPS51125

39DDR_VREF_S3

RT9026PFP

3D3V_S5(6A)

1D1V_S0(7.5A)DCBATOUT

38

1D2V_S0(4A)

RT9161

0D9V_S3

RT8202 X 2OUTPUTSINPUTS

2D5V_S0(200mA)

3D3V_S0

36

41

CPU DC/DC

OUTPUTS

0~1.55V 18A

VCC_CORE_S0_0

CHARGER

DCBATOUT

INPUTS

CHG_PWR

INPUTS OUTPUTS

18V 6.0A

5V 100mAUP+5V

DCBATOUT

ISL6265HR

MAX8731

CardReaderRealtekRTS5158E 5 in 1

MS/MS Pro/xD/MMC/SD

25 25

A-Link

AMD Giffin CPU S1G2 (35W)

INTEGRATED GRAHPICS

CPU I/F

AMD RS780M

638-Pin uFCPGA638

ETHERNET (10/100/1000Mb)

USB 2.0/1.1 ports

AMD SB700

LVDS, CRT I/F

LPC I/F

ACPI 1.1

High Definition Audio

ATA 66/100

PCI/PCI BRIDGE

South Bridge

North Bridge

16X16IN

OUT

RT8202SYSTEM DC/DC

4,5,6,7

11,12,13

17,18,19,20,21

4X4

DCBATOUT

40

39OUTPUTSINPUTS

1D8V_S3(11A)

G9161 40

40G957

1D2V_S5(400mA)

1D5V_S0(1A)

3D3V_S5

3D3V_S0

16

Daughter BoardLAUNCH Board

08575SATA2 頻寬為 3Gb/s=300MB/s USB2.0 最大頻寬

為 480MB/s

PCI-E 每一對的頻寬為 2.5Gb/s=250MB/s

A-Link2.5Gb/s*4=10Gb/s=1GB/s( 除以 10 的原因是原本的 8 位元再加上 2 個偵錯位元 )

200MHz( 基頻 )*2( 兩組 CLK)*2( 上下觸發 )=800MHz800MHz*64bit(64 根 Data,1 根 1bit)/8=6400MB/s=6.4GB/s

Hyper Transport (HT3.0)2.6GHz(CPU 頻率 )*2( 上下觸發 )*2( 雙向 )*32bit(16bit up +16bit down)/8=41.6GB/s

Dolomites Power ON/RESET Sequence

DCBATOUT

3D3V_S5 5V_S5

3D3V_S0 3D3V_S5

5V_S05V_S5

5V_S0

VCC_CORE_S0_0/1

RTC_AUX_S5

5V_S5

3D3V_AUX_S5

SB700

RT8202

G792

GriffinISL6265HR

RS780M

KBCWPC775

-3

240ms afterVCC_G792>4.38V

KBC WPC775

LAN BCM5764

RTC

EN2

SLP_S5#

EN/DEM

SLP_S3#

PWRGOOD LDT_PG

ENABLE

SYSRESET#

VBAT

VCORE_EN

EN1

POWERGOODPWROK

RSMRST#

RSMRST#_KBC

PWR_BTN#

PLT

_RS

T1

#

3D3V_AUX_S5

ECRST#

KBC_PWRBTN#PM_PWRBTN#

PM_PWRBTN#

RT9026

RESET#

CPU

_PW

RG

D

A_RST#

Adapter In

AD+ DCBATOUT5V_AUX_S53D3V_AUX_S5

TPS51125

-4

-5-6-7

1

2

23 3.1

1D8V_S3

DDR_VREF_S3

9

17

18

18

TPS51125S5_ENABLE

-4

-14

5

6

6

LPC Debug BD

PM_SLP_S5#

PM_SLP_S5#

PM_SLP_S3#PM_SLP_S5#

0D9V_S3

-5

5V_S5

VLDOIN/VDDQSNS

3V/5V_EN

3V/5V_EN

Mini Card

3V/5V_EN

7

1D8V_S3

TPS2231 New CardAND

RUNPWROK

13

15

PM_SLP_S3#

1D8V_S0

1D1V_PWRGD

RUNPWROK_D

ANDSB_PWRGD

G9161

RT9161

G957

3D3V_S5

3D3V_S0

3D3V_S0

1D2V_S5

2D5V_S0

1D5V_S0

RT8202

RT8202

1D2V_PWRGDEN/DEM

EN/DEMPGOOD

PGOOD5V_S5

5V_S51D2V_S0

1D1V_S0

1D1V_PWRGD

AND

PM_SLP_S3#

2D5V_S0

VDDNB

CPU

_LD

T_S

TO

P#

CPU

_LD

T_R

ST#

LDT_STP# LDT_RST#

-2

8

7

12

1011

14

1916

NB_PWRGD

VCORE_EN

9

RESET_ LLDTSTOP_ L

3D3V_S5

N-MOS

1D8V_S3

3D3V_S5

Buffer

N-MOS

0D9V_S3

CLK GENICS9LPRS480

750mA

CODEC3.3V(35mA)5V(55mA)

LPCROM6mA

DDRII1D8V_S3(5000mA) 0D9V_S3(1200mA)

1D2V_S0

Mini card802.11/BT1500mA

4381 mA

3D3V_S0

5V_S0

CRT500mA

HDD1500mA

CD ROM1300mA

AMP 2057500mA

TOUCHPAD25mA

3D3V_S5

LCD500mA

4610 mA

FAN500mA

KBC Winbond WPC775L3D3V_AUX_S5(170mA)

KBC EV BD

1D1V_S0

BCM57643D3V_LAN_S5(190mA)

VCC_CORE_S0

MDC40mA

2D5V_S0

ExpressCARD

1000mA

BIOS ROM30mA

1D8V_S3

Dolomites Power Budget

5V_S5

MS Card200 mASD Card200 mA

USB*32000mA

DCBATOUT

1D8V_S0

0D9V_S3

1D2V_S0

3D3V_S5

2D5V_S0

1D8V_S3

5V_S5

DCBATOUT

1D8V_S0

VCC_CORE_S036000mA 1950mA8900mA

3875mA 310mA

720mA 8000mA 250mA 1472mA 2000mA

SB700

1D2V_S0(PCIE_I/O,PCIE_PVDD,ATA_I/O,ATA_PLL,SB_CORE)(1875mA)1D2V_S5 (USB CORE,1.2_S5_PW)(310mA)3D3V_S5(USB I/O,3.3V_S5_PW)(712mA)3D3V_S0(PCI/GPIO)(250mA)5V_S0(VREF)(1mA)

RS780M

1D1V_S0(VDDHTRX,VDDHT,VDDPCIE,VDDC,PLLs)(8900mA)1D2V_S0(VDDHTTX)(500mA)1D8V_S0(VDDA18,VDD18_MEM,VDD_MEM,VDDLT18,PLLs)(720mA)3D3V_S0(VDDG33,AVDD,VDDLT33)(165mA)

S1G2

VCC_CORE_S0(CORE0 & CORE1)(36A)VDDNB(Memory&Controller)(3000mA)0D9V_S3(VTT)(750mA)1D2V_S0(VLDT)(1500mA)1D8V_S3(VDDIO)(3000mA)2D5V_S0(VDDA)(250mA)

VDDNB

1D2V_S5

VDDNB 3000mA

1D1V_S0

1D2V_S5

Dolomites POWER BLOCK DIAGRAM

MAX8731AETI

TPS51125

AD+

BT+

DCBATOUT

5V_S5(2000mA)

3D3V_S5(1472mA)

3D3V_S0(3787mA)

S0S3S5

5V_S0(5206mA)

5V_AUX_S5(175mA)

AO4468

AO4468

RT82021D8V_S3(8000m

A)

0D9V_S3(1950mA)

3D3V_AUX_S5(175mA)

AD+

BT+

ISL6265HR

VCC_CORE_S0_0/1(36A)

DC Jack: 19V / 3.42A

Battery Conn.:11.1V / 4000mAh

1D2V_S5(310mA)G9161

RT9026

APM23001D8V_S0(720mA)

1D2V_S0(3875mA)

RT8202

RT8202

1D1V_S0(8900mA)

1D5V_S0(1000mA)G957

RT91612D5V_S0(250mA)

VDDNB(3000mA)

Dolomites Clock Block Diagram Crystal

14.31818MHz

CPUKG0C_LPRS

CPUKG0T_LPRS

CLKGEN

X1/X2

Crystal32.768KHz

KBC WPC775

48MHz_0

HTT0T_LPRS

SRC0T_LPRS

SRC3C_LPRS

SRC3T_LPRS

SRC1C_LPRS

SRC1T_LPRS

SRC4C_LPRS

SRC4T_LPRS

PCLK_KBC

ICS9LPRS480

SB700

X1/X2

HDA_BIT-CLK

CLK_PCIE_SB#

RS780M

HT_REFCLKP

HT_REFCLKN

REFCLK_P

GPPSB_REFCLKPGPPSB_REFCLKN

NEW CARDCLK_PCIE_NEW

CLK_PCIE_NEW#

CLK_NBHT_CLK

MINI CARD

CLK_PCIE_MINI1

CLK_PCIE_MINI1#

Crystal 25MHz

LANBCM5764

CLK_PCIE_LAN

CLK_PCIE_LAN#

CPU Griffin

CLKIN_L

CLKIN_HCPU_CLK

CPU_CLK#

RTC 32.768kHz

DDR2NORMAL

TYPEDIMM2

DDR2NORMAL

TYPEDIMM1

MEM_MA_CLK0_P

CODECALC268

MDC

ACZ_BTCLK_MDC

CPU_CLK(200MHz)

100MHz differential spreading SRC clock

SEL_HTT66REF0

SEL_SATAREF1

66MHz 3.3V single ended HTT clock

*

1

0 *

1

0

0

SEL_27REF2

100MHz non-spreading differential SATA clock

100MHz differential HTT clock

1

*

27MHz non-spreading singled clock on pin 5and 27MHz spread clock on pin 6

100MHz differential spreading SRC clock

CLK_PCIE_SB

CLK48_USB

SMBC0_SB

SMBD0_SB

SRC0C_LPRS

SMBDAT

SMBCLK

LPCCLK1

CLK_NBHT_CLK#

CLK_NB_14M

CLK_NB_GPPSB

CLK_NB_GPPSB#

HTT0C_LPRS

SRC2T_LPRS

SRC2C_LPRS

REF0

Crystal 25MHz

SATA_X1/X2

SDL0

SCA0

PCIE_RCLKN

PCIE_RCLKP

USBCLK

ACZ_BITCLK

HT_CPU_NB_CLK HT_NB_CPU_CLK

L0_CLKOUT L0_CLKIN

HT_RXCLK HT_TXCLK

MEM_MA_CLK0_NMEM_MA_CLK1_PMEM_MA_CLK1_N

MEM_MB_CLK0_P

MEM_MB_CLK1_P

MEM_MB_CLK0_N

MEM_MB_CLK1_N

ACZ_SPKR

CODECALC268

SB700

PCBEEP

Dolomites Audio Block Diagram

MDC CON.

H.P. Jack

Line Out

1 Watt

1 Watt

ACZ

KBCWPC775

KBC_BEEP

AUDIO_BEEP

Audio AMP.APA2057ARI

ACZ_SDATAINMic-In

FRONTL

FRONTR

MIC1_R

HP_OUT_R

MIC1_L

HP_OUT_L

SPKR_L+1

SPKR_R+1

AUD_MICIN_R

AUD_MICIN_L

SOUNDRLINE_OUT_R

LINE_OUT_LSOUNDL

SPKR_R+

SPKR_R-

SPKR_L+

SPKR_L-

KBC WPC775

3D3V_S5

New Card

3D3V_S0

DDR2DIMM2

DDR2DIMM1

CLK GENICS9LPRS480

SMB_CLK

SMB_DATA

Thermal

BAT_SCL

BatteryCONNECTOR

SMBC0_SB

SMBD0_SB

4k7 R4k7 R

BAT_SDA

SMBC_G792

10KR

33R

SB700

3D3V_S0

SMBD_G792 G792

4K7R

3D3V_AUX_S5

Dolomites SMB Interface

CHARGERMAX8731

Mini CardLAN

0R 33R 33RDY DY

RS780M

GMCH_DDCCLK

GMCH_DDCDATA

CLK_DDC_EDID

DAT_DDC_EDID

3D3V_S0

2K2R 10KR

5V_S03D3V_S0

CRTDAT_DDC1_5

CLK_DDC1_5

LCD

4K7R

3D3V_S0

Dolomites SMB Interface

當 SCL 為 High 而 SDA 由 High 變 Low 時表示開始一個 SMbus 的命令 . 當 SCL 為 High 而 SDA 由 Low 變 High 時表示結束一個 SMbus 的命令 . 這二個狀況在 Smbus 裡是唯一的 . 在一般傳送資料時均不可能發生 . 而在一般傳送資料時則是在每一次 SCL 的上升緣時的 SDA 狀態來決定 . 這些資料包含了仲裁 ,確認 , 送出資料給那一個裝置及送出的資料 . 或要取得那一個裝置的資料及由裝置送出的資料 .

在 SMbus 上只有一個 Master. 所有的命令均有此 Master 發出 . 其他的裝置 (Slave) 只能接收 Master 發出的命令或回覆資料給 Master.

SMbus 是由兩條訊號所組成的一種匯流排 . 是為了在系統上較慢速的裝置及電源管理裝置之間的溝通使用 . 使系統可取得這些裝置的製造廠商 , 型號 , 一些控制資訊 , 錯誤訊息及狀態 . 這兩條訊號為 SMBCLK 和 SMBDATA. 這和 I2C 上的 Clock(SCL) 和 Data(SDA) 是一樣的 .

LPC BUS

KBCWPC775

ECSCI#

PWUREQ#

LPC_PME#/GEVENT3#

USB_OC6#/IR_TX1

Dolomites SMI/SCI/SWI Interface

HDA_SDIN0

PWRBTN#

SB700

Power Switch Block

GPIO06

GPIO42

From S3 state wakeup event: (1) Power Button; (2) WOL ( AC Only ); (3) Embedded Modem ( AC Only ) ;(4) RTC; (5) Lid; (6) Battery Critical

GPIO07

GPIO41

RSMRST#

HDA_SDIN1CODECALC268

MDC

FWH

GPIO20

GPIO43

GPIO03

GPIO01

HDA_SDOUT

ECSMI#_KBC

ECSCI#_1

ECSWI#

RSMRST#_KBC

PM_PWRBTN#

ACZ_SDATAOUTAC_Link

ACZ_SDATAIN1

ACZ_SDATAIN0

SPI

PM_SLP_S3#

AC_IN#

AD_OFF

BAT_IN#

KBC_PWRBTN#

LID_CLOSE#

SMI 在 DOS 底下動作

SCI 在 windows 底下動作

SWI 是指 wake up event

PCIE_WAKE# LANBCM5764WAKE#/GEVENT8#

NEW CARD

0RDY10K

3D3V_S0

CPU

PHASE0

ISP0

PWRGD

VDDNB_FB_H

VCC_CORE_S0_0/1

VSEN_NBVCC_CORE_S0_0

Dolomites VCC_CORE Block Diagram

UGATE0

BOOT0

PHASE0

DCBATOUT

DPRSTP#

Griffin

UGATE0

BOOT0

ENABLE

VCORE_ENRT8202

1D1V_S0

RT8202

1D2V_S0

DCBATOUT

PHASE1

BOOT1

LGATE1

ISP1

ISN1

VCC_CORE_S0_1

ISN0

開

開

關

關

Sense 電阻

濾波電容

補償用

相差 180度

Positive Input of the Output Current SenseNegative Input of the Output Current Sense

LGATE0

CPU_VDDNB_RUN_FB_H

CPU_VDDNB_RUN_FB_L

CPU_VDD0_RUN_FB_H

CPU_VDD0_RUN_FB_L

CPU_VDD1_RUN_FB_H

CPU_VDD1_RUN_FB_L

ISL6265HR

RTN_NB

VSEN0

RTN0

VSEN1

RTN1

VDDNB_FB_L

VDD0_FB_H

VDD0_FB_L

VDD1_FB_H

VDD1_FB_L

DCBATOUT

VDDNB

UGATE1

PHASE1

BOOT1

LGATE1

UGATE_NB

BOOT_NB

LGATENB

ISP0

ISN0

ISN1

ISP1

LGATE0

UGATE1

UGATE_NB

LGATE_NB

BOOT_NB

CPU_PWRGD_SVID_REG

CPU_SVD

CPU_SVCSVC

SVD

PWROK

SVC

SVD

PWROK