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SEIKO EPSON CORPORATION Rev 1.1

S2D13515 Display Controller

S5U13515P00C100 Evaluation Board User

Manual

NOTICE

No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any lia-bility of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or cir-cuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency.

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©SEIKO EPSON CORPORATION 2008 - 2009, All rights reserved.

S5U13515P00C100 Evaluation Board User Manual (Rev 1.1) EPSON 3

Table of Contents

Chapter 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Chapter 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Chapter 3 Installation and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.1 CNF[7:0] Configuration Inputs . . . . . . . . . . . . . . . . . . . . . . . . . 73.1.1 CNF[2:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73.1.2 CNF[7:3] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83.1.3 Host Interface Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.2 Configuration Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Chapter 4 Technical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154.1 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.1.1 Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154.1.2 Voltage Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154.1.3 S2D13515 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154.1.4 LCD Backlight Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.2 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164.3 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164.4 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.4.1 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174.4.2 Serial Flash Memory with SPI interface . . . . . . . . . . . . . . . . . . . . . . . 17

4.5 Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174.5.1 Direct Host Bus Interface Support . . . . . . . . . . . . . . . . . . . . . . . . . . 174.5.2 Connecting to the Epson S5U13U00P00C100 USB Adapter Board . . . . . . . . . 18

4.6 LCD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194.6.1 FP1IO Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194.6.2 FP2IO Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.7 Camera / I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 204.8 Keypad Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214.9 I2S Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224.10 PWM Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234.11 C33 Debugger Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244.12 JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Chapter 5 Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Chapter 6 Schematic Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29Chapter 7 Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4 EPSON S5U13515P00C100 Evaluation Board User Manual (Rev 1.1)

Chapter 8 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .368.1 Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .368.2 Document Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Chapter 1 Introduction


Chapter 1 IntroductionThis manual describes the setup and operation of the S5U13515P00C100 Evaluation Board. The evaluation board is designed as an evaluation platform for the S2D13515 Display Controller.

The S5U13515P00C100 evaluation board can be used with many native platforms via the host connector which provides the appropriate signals to support a variety of CPUs. The S5U13515P00C100 evaluation board can also connect to the S5U13U00P00C100 USB Adapter board so that it can be used with a laptop or desktop computer, via USB 2.0.

This user manual is updated as appropriate. Please check the Epson Research and Development Website at www.erd.epson.com for the latest revision of this document before beginning any development.

We appreciate your comments on our documentation. Please contact us via email at [email protected].

Chapter 2 Features


Chapter 2 FeaturesThe S5U13515P00C100 Evaluation Board includes the following features:

• 256-pin PBGA S2D13515 Display Controller

• On-board SDRAM, configurable as 32MB (32-bit wide) or 16MB (16-bit wide)

• On-board Serial Flash Memory, 32Mbit

• Headers for connection to various Host Bus Interfaces (includes all S2D13515 Host Bus Interface signals)

• Headers for connection to the S5U13U00P00C100 USB Adapter board

• Headers for connection to various LCD panels (includes all S2D13515 FP1IO and FP2IO interface signals)

• Header for connection to cameras

• Header for I2S outputs

• On-board 3x3 keypad

• On-board 20MHz crystal

• 14-pin DIP socket (if an oscillator for CLKI input is required)

• 3.3V input power

• On-board voltage regulator with 1.8V output

• On-board voltage regulator with adjustable 12~25V output, 60~100mA max., to provide power for LED back-light of LCD panels.

Chapter 3 Installation and Configuration


Chapter 3 Installation and ConfigurationThe S5U13515P00C100 evaluation board incorporates a DIP switch, jumpers, and 0 ohm resistors which allow it to be used with a variety of different configurations.

3.1 CNF[7:0] Configuration Inputs

The S2D13515 has 8 configuration inputs (CNF[7:0]), which can be configured through a combination of a DIP switch and 0 ohm resistors. CNF[2:0] are dedicated inputs and are configured using DIP switch SW1. CNF[7:3] are multiplexed with some host interface signals and are configured by 0 ohm resistors.

3.1.1 CNF[2:0]

CNF[2:0] are configured using DIP switch SW1 as described below.

The following figure shows the location of DIP switch SW1 on the S5U13515P00C100 evaluation board.

Figure 3-1: Configuration DIP Switch (SW1) Location

Table 3-1: CNF[2:0] Configuration SettingsCNF[2:0] 1 (connected to HIOVDD) 0 (connected to VSS)

CNF2 CNF[2:1] are used in combination with CNF[7:3] to select the host bus interface. For a summary of the possible host bus interfaces, see Section Table 3-3 :, “Host Interface Configuration Settings” on page 9.CNF1

CNF0 OSCI is the source for Input Clock 1 CLKI is the source for Input Clock 1

= suggested settings



3.1.2 CNF[7:3]

CNF[7:3] are configured using 0 Ohm resistors as described below.

NoteCNF3 and CNF6 are mapped to different pins depending on the combination of the other CNF inputs.

The following figure shows the location of the 0 Ohm resistors used to configure CNF[7:3].

Figure 3-2: CNF[7:3] 0 Ohm Resistor Locations

Table 3-2: CNF[7:3] Configuration Settings

CNF Pin 1 (connected to HIOVDD) 0 (connected to VSS)

CNF3(see Note)

TEA# R100 populatedR107 not populated

R100 not populatedR107 populated

AB0 R99 populatedR106 not populated


CNF4 BDIP# R95 populatedR102 not populated


CNF5 BURST# R96 populatedR103 not populated


CNF6(see Note)



BE1# R97 populatedR104 not populated




CNF7 AB4 R101 populatedR108 not populated


= default settings, required settings when using S5U13U00P00C100 USB Adapter Board



3.1.3 Host Interface Configuration

The host bus interface used by the S5U13515P00C100 evaluation board is selected using a combination of the CNF[2:1] pins and unused host interface pins. Many host bus interfaces have unused pins that can be used as config-uration pins (CNF[7:3]) to select the host bus interface. The following table summarizes the available settings.

Table 3-3 : Host Interface Configuration SettingsCNF1 CNF2 CNF3 CNF4 CNF5 CNF6 CNF7 Host Interface

0 0 0 (TEA#) 0 (BDIP#) 0 (BURST#) 0 (AB3) X Indirect, 8-bit, Intel80 Type10 0 0 (TEA#) 0 (BDIP#) 0 (BURST#) 1 (AB3) X Indirect, 8-bit, Intel80 Type20 0 0 (TEA#) 0 (BDIP#) 1 (BURST#) 1 (AB3) 0 (AB4) SPI0 0 0 (TEA#) 0 (BDIP#) 1 (BURST#) 1 (AB3) 1 (AB4) I2C0 0 0 (TEA#) 1 (BDIP#) 0 (BURST#) 0 (AB3) X Indirect, 8-bit, NEC V850 Type10 0 0 (TEA#) 1 (BDIP#) 0 (BURST#) 1 (AB3) X Indirect, 8-bit, NEC V850 Type20 0 0 (TEA#) 1 (BDIP#) 1 (BURST#) 0 (AB3) X Indirect, 8-bit, Renesas SH40 1 0 (TEA#) 0 (BDIP#) 0 (BURST#) 0 (AB3) X Indirect, 16-bit, Intel80 Type10 1 0 (TEA#) 0 (BDIP#) 0 (BURST#) 1 (AB3) X Indirect, 16-bit, Intel80 Type20 1 0 (TEA#) 0 (BDIP#) 1 (BURST#) 1 (AB3) 0 (AB4) SPI (2-stream)0 1 0 (TEA#) 0 (BDIP#) 1 (BURST#) 1 (AB3) 1 (AB4) I2C0 1 0 (TEA#) 1 (BDIP#) 0 (BURST#) 0 (AB3) X Indirect, 16-bit, NEC V850 Type10 1 0 (TEA#) 1 (BDIP#) 0 (BURST#) 1 (AB3) X Indirect, 16-bit, NEC V850 Type20 1 0 (TEA#) 1 (BDIP#) 1 (BURST#) 0 (AB3) X Indirect, 16-bit, Renesas SH40 0 1 (TEA#) 0 (BDIP#) 0 (BURST#) 0 (BE1#) X Direct, 8-bit, Intel80 Type10 0 1 (TEA#) 0 (BDIP#) 0 (BURST#) 1 (BE1#) X Direct, 8-bit, Intel80 Type20 0 1 (TEA#) 0 (BDIP#) 1 (BURST#) 1 (BE1#) 0 (AB4) SPI0 0 1 (TEA#) 0 (BDIP#) 1 (BURST#) 1 (BE1#) 1 (AB4) I2C0 0 1 (TEA#) 1 (BDIP#) 0 (BURST#) 0 (BE1#) X Direct, 8-bit, NEC V850 Type10 0 1 (TEA#) 1 (BDIP#) 0 (BURST#) 1 (BE1#) X Direct, 8-bit, NEC V850 Type20 0 1 (TEA#) 1 (BDIP#) 1 (BURST#) 0 (BE1#) X Direct, 8-bit, Renesas SH40 1 1 (TEA#) 0 (BDIP#) 0 (BURST#) 0 (AB0) X Direct, 16-bit, Intel80 Type10 1 1 (TEA#) 0 (BDIP#) 0 (BURST#) 1 (AB0) X Direct, 16-bit, Intel80 Type20 1 1 (TEA#) 0 (BDIP#) 1 (BURST#) 0 (AB0) X Direct, 16-bit, Intel PXA3xxs0 1 1 (TEA#) 0 (BDIP#) 1 (BURST#) 1 (AB0) 0 (AB4) SPI0 1 1 (TEA#) 0 (BDIP#) 1 (BURST#) 1 (AB0) 1 (AB4) I2C0 1 1 (TEA#) 1 (BDIP#) 0 (BURST#) 0 (AB0) X Direct, 16-bit, NEC V850 Type10 1 1 (TEA#) 1 (BDIP#) 0 (BURST#) 1 (AB0) X Direct, 16-bit, NEC V850 Type20 1 1 (TEA#) 1 (BDIP#) 1 (BURST#) 0 (AB0) X Direct, 16-bit, Renesas SH41 0 0 (AB0) X X X X Indirect, 16-bit, TI EBI1 0 1 (AB0) X X X X Direct, 16-bit, TI EBI1 1 0 (BE1#) X X X X Indirect, 16-bit, MPC5551 1 1 (BE1#) X X X X Direct, 16-bit, MPC555

= default settings, required settings when using S5U13U00P00C100 USB Adapter BoardX = don’t care



3.2 Configuration Jumpers

The S5U13515P00C100 has 16 jumpers which configure various evaluation board settings. The jumper positions for each function are shown below.

Table 3-4: Configuration Jumper SettingsJumper Function Position 1-2 Position 2-3 No Jumper

JP1 COREVDD Normal — COREVDD current measurement

JP2 PLL1VDD Normal — PLL1VDD current measurement

JP3 PLL2VDD Normal — PLL2VDD current measurement

JP4 OSCVDD Normal — OSCVDD current measurement

JP5 PIO1VDD Normal — PIO1VDD current measurement

JP6 HIOVDD Normal — HIOVDD current measurement

JP7 HIOVDD Source H4 connector, pin 31 3.3VDD —

JP8 PIO1VDD Source H9 connector, pin 9 3.3VDD —

JP9 PIO2VDD Source H9 connector, pin 10 3.3VDD —

JP10 CM1VDD Normal — CM1VDD current measurement

JP11 PIO2VDD Normal — PIO2VDD current measurement

JP12 CM1DD Source H9 connector, pin 8 3.3VDD —

JP13 IOVDD Source H9 connector, pin 7 3.3VDD —

JP14 IOVDD Normal — IOVDD current measurement

JP15 SDVDD Normal — SDVDD current measurement

JP16 SDRAM Width Select (see Note) 32-bit wide SDRAM 16-bit wide SDRAM —

= Required settings when using S5U13U00P00C100 USB Adapter board



JP1, JP2, JP3, JP4, JP5, JP6, JP10, JP11, JP14, JP15 - Power Supplies for the S2D13515

JP1, JP2, JP3, JP4, JP5, JP6, JP10, JP11, JP14, and JP15 can be used to measure the current consumption of each S2D13515 power supply. When the jumper is at position 1-2, normal operation is selected. When no jumper is installed, the current consumption for each power supply can be measured by connecting an ammeter to pin 1 and 2 of the jumper.

The jumper associated with each power supply is as follows:

JP1 for COREVDD JP2 for PLL1VDD JP3 for PLL2VDD JP4 for OSCVDD JP5 for PIO1VDD JP6 for HIOVDD JP10 for CM1VDD JP11 for PIO2VDD JP14 for IOVDD JP15 for SDVDD

Figure 3-3: Configuration Jumper Locations (JP1, JP2, JP3, JP4, JP5, JP6, JP10, JP11, JP14, JP15)



JP7 - HIOVDD Source

JP7 is used to select the source for the HIOVDD supply voltage. When the jumper is at position 1-2, the HIOVDD voltage must be provided to pin 31 on the H4 connector. When the jumper is at position 2-3, the HIOVDD voltage is provided by the 3.3V power supply of the board.

Figure 3-4: Configuration Jumper Location (JP7)

JP8 - PIO1VDD Source

JP8 is used to select the source for the PIO1VDD supply voltage. When the jumper is at position 1-2, the PIO1VDD voltage must be provided to pin 9 on the H9 connector. When the jumper is at position 2-3, the PIO1VDD voltage is provided by the 3.3V power supply of the board.




JP9 - PIO2VDD Source

JP9 is used to select the source for the PIO2VDD supply voltage. When the jumper is at position 1-2, the PIO2VDD voltage must be provided to pin 10 on the H9 connector. When the jumper is at position 2-3, the PIO2VDD voltage is provided by the 3.3V power supply of the board.


JP12 - CM1VDD Source

JP12 is used to select the source for the CM1VDD supply voltage. When the jumper is at position 1-2, the CM1VDD voltage must be provided to pin 8 on the H9 connector. When the jumper is at position 2-3, the CM1VDD voltage is provided by the 3.3V power supply of the board.




JP13 - IOVDD Source

JP13 is used to select the source for the IOVDD supply voltage. When the jumper is at position 1-2, the IOVDD voltage must be provided to pin 7 on the H9 connector. When the jumper is at position 2-3, the IOVDD voltage is provided by the 3.3V power supply of the board.


JP16 - SDRAM Width Select

JP16 is used to select the bus width of the external SDRAM. When the jumper is at position 1-2, the external SDRAM is 32 bits wide and the memory size is 32M bytes. In this configuration, the memory consists of 2 chips in parallel, each16M bytes and 16 bits wide. When the jumper is at position 2-3, the external SDRAM is 16 bits wide and the memory size is 16M bytes. In this configuration, one memory chip is disabled and only one chip is active (16M bytes and 16 bits wide).


Chapter 4 Technical Description



4.1 Power

4.1.1 Power Requirements

The S5U13515P00C100 evaluation board requires an external regulated power supply (3.3V / 1A). The power is supplied to the evaluation board through pin 33 of the H4 header, or pin 5 of the P2 header.

The green LED “3.3V Power” is turned on when 3.3V power is applied to the board.

4.1.2 Voltage Regulators

The S5U13515P00C100 evaluation board has an on-board linear regulator to provide the 1.8V power required by the S2D13515 Display Controller. It also has a step-up switching voltage regulator to generate adjustable 12~25V, which can be used to power the LED backlight on some LCD panels.

4.1.3 S2D13515 Power

The S2D13515 Display Controller requires 1.8V power and 2.3~2.7V or 3.0~3.6V power.

COREVDD, PLL1VDD, PLL2VDD, and OSCVDD require 1.8V power which is provided by an on-board linear voltage regulator.

HIOVDD, PIO1VDD, PIO2VDD, CM1VDD, and IOVDD input power may be in the range 2.3V~2.7V or 3.0V~3.6V. When JP7, JP8, JP9, JP12, or JP13 are set to the 2-3 position, the corresponding power input is connected to 3.3V. If a different voltage is required, set the corresponding jumper to the 1-2 position and connect the external power supply to the evaluation board as indicated in Table 3-4: “Configuration Jumper Settings,” on page 10.

SDVDD input power may be in the range 2.3V~2.7V or 3.0V~3.6V. On the evaluation board, SDVDD is connected to 3.3V.

4.1.4 LCD Backlight Power

On the evaluation board there is an adjustable 12~25V power supply. At 12V, the maximum current available is 100mA. At 25V, the maximum current available is 60mA. This power supply is intended for use to power the LED backlight on some LCD panels. The voltage is adjusted by the R175 pot.

NoteFor LCD panels that use a CCFL backlight, an external power supply must be used to provide power to the inverter for the CCFL backlight. Usually, the inverter current consumption is higher than the maximum 100mA current available from the on-board voltage regulator.



4.2 Clocks

The clock for the S2D13515 Display Controller is provided by a 20MHz crystal connected to the OSCI and OSCO pins.

Additionally, the S5U13515P00C100 evaluation board can also use an oscillator if the DIP14 footprint is populated. If populated, the oscillator is connected to the CLKI input clock of the S2D13515 Display controller.

NoteFor details on the S2D13515 clock structure, refer to the S2D13515 Hardware Functional Specification, document number X83A-A-001-xx.

4.3 Reset

The S2D13515 Display Controller on the S5U13515P00C100 evaluation board can be reset using a push-button switch (SW2), or via an active low reset signal from the host development platform (pin 30 on the H4 connector).

Figure 4-1: Reset Switch (SW2) Location



4.4 Memory

4.4.1 SDRAM

The S5U13515P00C100 evaluation board has 2 SDRAM ICs, each 128Mbit x16-bit, CL=2 in a TSOP54 package. When the S2D13515 Display Controller is configured for 32-bit wide DRAM bus, both SDRAM ICs are used. When the S2D13515 Display Controller is configured for 16-bit wide DRAM bus, only one of the SDRAM ICs is used and the other SDRAM ICs is disabled by having its chip select input pulled high to inactive state, by putting jumper JP16 in 2-3 position.

4.4.2 Serial Flash Memory with SPI interface

The S2D13515 Display Controller has a SPI Flash Memory interface which is connected to a 32Mbit Flash EPROM.

4.5 Host Interface

4.5.1 Direct Host Bus Interface Support

All S2D13515 host interface pins are available on connectors H3 and H4. This allows the S5U13515P00C100 evalu-ation board to be connected to a variety of development platforms. For S2D13515 host interface pin mapping, refer to the S2D13515 Hardware Functional Specification, document number X83A-A-001-xx.

The following figure shows the location of host bus connectors H3 and H4. H3 is a 0.1” x 0.1” 40-pin header (20x2) and H4 is a 0.1” x 0.1” 34-pin header (17 x 2).

Figure 4-2: Host Bus Connector Location (H3 and H4)

For the pinout of connectors H3 and H4, see Section Chapter 6, “Schematic Diagrams” on page 29.



4.5.2 Connecting to the Epson S5U13U00P00C100 USB Adapter Board

The S5U13515P00C100 evaluation board is designed to connect to a S5U13U00P00C100 USB Adapter Board. The USB adapter board provides a simple connection to any computer via a USB 2.0 connection. The S5U13515P00C100 directly connects to the USB adapter board through connectors P1 and P2.

The USB adapter board also supplies the 3.3V power required by the S5U13515P00C100 evaluation board. HIOVDD should be configured for 3.3V and JP7 should be set to the 2-3 position.

When the S5U13515P00C100 is connected to the S5U13U00P00C100 USB Adapter board, there are 2 LEDs on the S5U13515P00C100 which provide a quick visual status of the USB adapter. LED1 blinks to indicate that the USB adapter board is active. LED2 turns on to indicate that the USB has been enumerated by the PC.

The following diagram shows the location of connectors P1 and P2. P1 and P2 are 2mm x 2mm, 40-pin headers (20 x 2) located on the underside of the board.

Figure 4-3: USB Adapter Connector Locations (P1 and P2)

For the pinout of connectors P1 and P2, see Section Chapter 6, “Schematic Diagrams” on page 29.

NoteA windows driver must be installed on the PC when the S5U13515P00C100 is used with the S5U13U00P00C100 USB Adapter Board. The S1D13xxxUSB driver is available at www.erd.epson.com.



4.6 LCD Interface

The LCD interface uses the FP1IO[23:0] and FP2IO[27:0] pins. All signals on these pins are available on connectors H5, H6, and H7.

Connectors H5, H6, and H7 are 0.1” x 0.1”, 40-pin headers (20 x 2). The following diagram shows the location of these connectors.

Figure 4-4: FP1IO and FP2IO Connectors Location (H5, H6, H7)

For the pinout of connectors H5, H6, and H7, see Section Chapter 6, “Schematic Diagrams” on page 29.

4.6.1 FP1IO Interface

The FP1IO interface signals have multiplexed functions. All FP1IO interface signals, except FP1IO18 and FP1IO19, are available on connector H6. FP1IO18 and FP1IO19 signals go through 0 ohm resistors and are available on connector H7.

The FP1IO interface can be configured as a LCD interface, 18-bit RGB input stream interface, or 8-bit YUV camera interface and keyboard interface. For S2D13515 FP1IO interface pin mapping, refer to the S2D13515 Hardware Functional Specification, document number X83A-A-001-xx.

4.6.2 FP2IO Interface

All FP2IO interface signals are available on connectors H5 and H7. For S2D13515 FP2IO interface pin mapping, refer to the S2D13515 Hardware Functional Specification, document number X83A-A-001-xx.



4.7 Camera / I2C Interface

The S2D13515 Display Controller has a Camera interface. All the camera interface signals are available on connector H10. To control the camera, the S2D13515 Display Controller has an I2C master interface. The SDA and SCL signals are pulled high to CM1VDD by 2.2 kΩ resistors and are available on connector H10. The reset signal provided on H10 is active low and is pulled to HIOVDD when inactive.

Connector H10 is a 0.1” x 0.1”, 20-pin header (10 x 2). The following figure shows the location of the connector H10.

Figure 4-5: Camera Connector Location (H10)

For the pinout of connector H10, see Section Chapter 6, “Schematic Diagrams” on page 29.



4.8 Keypad Interface

NoteThe keyboard is non-operational with the buttons SW3-SW11, mounted as they are on the board. In order to make the keyboard operational, the user must remove the buttons SW3-SW11 from the board and mount them back on the board, but rotated by 90 degrees or 270 degrees. The buttons will not match the footprint on the PCB, but this is how they must be mounted on the board.

The S2D13515 Display Controller can support up to a 5x5 matrix keypad, but the S5U13515P00C100 evaluation board includes only a 3x3 keypad. The keypad interface can be configured to use either the FPIO1 interface or Host interface pins. For S2D13515 pin mapping, refer to the S2D13515 Hardware Functional Specification, document number X83A-A-001-xx. The keypad interface is configured for either the FPIO1 interface or Host Interface pins using 0 ohm resistors.

Figure 4-6: Keypad Interface Zero Ohm Resistor Overview Diagram

The keypad can be configured to connect to 1 of 2 source pins on the S2D13515. Depending of the configuration, the input lines must be pulled high to corresponding power supply. The source connection for the keypad is deter-mined by populating the correct set of zero ohm resistors as described below.

S5U13515P00C100 evaluation board comes configured with the keyboard interface from the Host Interface pins, so resistors R185 ~ R190 and R180 are populated and R191 ~ R196 and R181 are not populated.

Table 4-1: Keypad Zero Ohm Resistor Summary

Keypad Pin FunctionPopulate only 1 set of the zero ohm resistors below

Zero Ohm For FP1IO Zero Ohm For Host InterfaceKBR0 R191 R185KBR1 R192 R186KBR2 R193 R187KBC0 R194 R188KBC1 R195 R190KBC2 R196 R189Power

(HIOVDD or PIO1VDD) R181 R180

S2D13515

ZeroOhms

ZeroOhms

3x3M/R#, AB[20:19], AB[16:14]

FP1IO[23:20], FP1IO[16:15] Keypad



4.9 I2S Interface

The S2D13515 Display Controller has an I2S Audio output interface. All of the I2S interface signals are available on connector H8. The I2C signals, available on the same connector, can be used to program an external I2S Audio DAC IC.

Connector H8 is a 0.1” x 0.1”, 24-pin header (12x2). The following figure shows the location of the connector H8.

Figure 4-7: I2S Connector Location (H8)




4.10 PWM Connector

The S2D13515 Display Controller has two PWM outputs which are available on connector H9. The other pins on connector H9 are used to connect the external power supplies to CM1VDD, IOVDD, PIO1VDD, and PIO2VDD, if a voltage level different than 3.3V is required. Note that connector H9 is not populated on the S5U13515P00C100 evaluation board.


Figure 4-8: PWM Connector Location (H9)




4.11 C33 Debugger Port

The S2D13515 contains an embedded C33 microprocessor core. The debug monitor interface is available on connector H2 for firmware debugging using C33 Debugger. In order to use connector H2, zero ohm resistors must be configured depending on the desired S2D13515 configuration.

The C33 debugger function can be sourced from 2 sets of the host interface pins or from a set of FP2IO pins.

Figure 4-9: C33 Debugger Zero Ohm Resistor Overview Diagram

The connection to the C33 Debugger port is determined by populating the correct set of zero ohm resistors as described below.

S5U13515P00C100 board comes configured for the C33 Debugger port from the Host Interface AB[11:6] pins, so resistors R63, R65 ~ R69 are populated and R197 ~ R202 are not populated, R203 ~ R215 are populated and R64, R70 ~ R81 are not populated.

Table 4-2: C33 Debugger Port H7 Zero Ohm Selection

C33 Pin FunctionPopulate only 1 set of the zero ohm resistors below

C33 Debugger port from FP2IO pins

C33 Debugger port from AB[11:7], AB6 or BS# pins

C33 Debugger port from DB[13:8] pins

PEDST0 R74 populatedR210 not populated

R65 populatedR202 not populated








PEDCLK R70 populatedR213 not populated



PEDSIO R71 populatedR215 not populated



PEDCPCO R75 populatedR214 not populated

R63 populated (from AB6)R64, R197 not populated R81 populated

R203 not populatedR64 populated (from BS#)R63, R209 not populated

S2D13515 ZeroOhms

ZeroOhms

ZeroOhms

H2C33

DebuggerPort

AB[11:7], AB6 or BS#

FP2IO[17, 16, 14, 13, 11, 10]

DB[13:8]




Figure 4-10: C33 Debugger Connector Location (H2)


4.12 JTAG Interface

The S2D13515 Display Controller has a JTAG interface. All the JTAG signals are available on connector H1. Note that connector H1 is not populated on the S5U13515P00C100 evaluation board.


Figure 4-11: JTAG Connector Location (H1)


Chapter 5 Parts List



Table 5-1 : S5U13515P00C100 Parts ListItem Quantity Reference Part Description

1 50

C1,C2,C3,C4,C5,C6,C7,C8,C17,C20,C24,C25,C26,C27,C28,C29,C30,C31,C39,C40,C41,C42,C43,C49,C50,C51,C52,C53,C54,C55,C63,C67,C69,C71,C72,C74,C75,C76,C77,C78,C79,C80,C81,C82,C83,C84,

C85,C86,C87,C106

0.1uF Yageo America 04022F104Z7B20D, C0402

2 43

C9,C10,C11,C12,C13,C14,C15,C16,C23,C32,C33,C34,C35,C36,C37,C38,C44,C45,C46,C47,C48,C56,C57,C58,C59,C60,C61,C62,C68,C88,C89,C90,C91,C92,C93,C94,C95,C96,C97,

C98,C99,C100,C101

0.01uF Yageo America 0402ZRY5V7BB103, C0402

3 2 C18,C21 1nF Yageo America 04022R102K9B20D, C0402

4 5 C19,C22,C64,C70,C73 10uF Panasonic - ECG ECJ-CV50J106M, C0805

5 2 C65,C66 18pF Panasonic - ECG ECJ-0EC1H180J, C0402

6 1 C102 2.2uF 10V Taiyo Yuden LMK212BJ225KG-T, C0805,CAP CER 2.2UF 10V X7R 0805

7 1 C103 10uF 35V Taiyo Yuden GMK325BJ106KN-T, C1210,CAP CER 10UF 35V X5R 1210

8 1 C104 150pF Panasonic - ECG ECJ-0EC1H151J, C0402

9 1 C105 1uF Panasonic - ECG ECJ-0EB0J105M, C0402

10 3 D1,D2,D3 Panasonic - SSG LNJ308G8LRA, LED0603,LED GREEN SS TYPE LOW CUR SMD

11 10 D4,D5,D6,D7,D8,D9,D10,D11,D12,D13 MBR0540 Micro Commercial Co. MBR0540-TP, SOD-123,

DIODE SCHOTTKY 40V 500MA SOD123

12 1 F1 ACH32C-333-T TDK ACH32C-333-T,FILTR 3TERM 10MHZ TO 300MHZ SMD

13 1 F2 ACF451832-222 TDK ACF451832-222,FILTER 3-TERM 60MHZ 300MA SMD

14 0 H1 JTAG Samtec TSW-106-07-G-DDo not populate

15 1 H2,H9 Samtec TSW-105-07-G-D, Do not populate H9

16 1 H3 HEADER_20X2 Samtec TSW-120-07-G-D

17 1 H4 HEADER_17X2 Samtec TSW-117-07-G-D

18 3 H5,H6,H7 Samtec TST-120-01-G-D

19 1 H8 I2S PORT Samtec TSW-112-07-G-D

20 1 H10 CAMERA1 Samtec TSW-110-07-G-D



21 10 JP1,JP2,JP3,JP4,JP5,JP6JP10,JP11,JP14,JP15

SIP2 CONN HEADER VERT 2POS .100 TIN or GENERIC

22 6 JP7,JP8,JP9,JP12,JP13,JP16

SIP3 CONN HEADER VERT 3POS .100 TIN or GENERIC

23 6 L1,L2,L3,L4,L5,L6 Ferrite Steward HZ0603B751R-10, R0603,FERRITE 200MA 938 OHMS 0603 SMD

24 1 L7 10uH Panasonic - ECG ELL-6SH100M, IND_ELL6,COIL 10UH 1300MA CHOKE SMD

25 2 P1,P2 HEADER_20X2 3M 151240-8422-RB, HDR2X20/2MM

26 61

R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,R13,R14,R15,R16,R17,R18,R19,R20,R21,R22,R23,R24,R25,R26,R27,R28,R29,R30,R31,R32,R33,R34,R35,R36,R37,R38,R39,R40,R41,R42,R43,R44,R45,R46,R47,R48,R49,R50,R51,R53,R54,R55,R57,R58,R59,R6

0,R61,R62,R88

33 1% R0402

27 0

R52,R64,R70,R71,R72,R73,R74,R75,R76,R77,R78,R79,R80,R81,R95,R96,R97,R98,R99,R100,R101,R104,R106,R108,R134,R135,R136,R137,R138,R139,R140,R141,R142,R143,R144,R145,R146,R147,R148,R149,R150,R151,R161,R163,R165,R167,R169,R170,R181,R191,R192,R193,R194,R195,R196,R197,R198,R199,R200,R201,R202,R216,

R217,R218,R219

0_np R0402Do not populate

28 68

R56,R63,R65,R66,R67,R68,R69,R83,R85,R86,R87,

R102,R103,R105,R107,R109,R110,R111,R113,R114,R115,R116,R117,R118,R119,R120,R121,R122,R123,R124,R125,R126,R127,R128,R129,R130,R131,R132,R152,R153,R154,R155,R160,R162,R164,R166,R168,R171,R180,R185,R186,R187,R188,R189,R190,R203,R204,R205,R206,R207,R208,R209,R210,R211,R212,

R213,R214,R215

0 R0402

29 1 R82 1M R0402

30 1 R84 1k R0402




31 10 R89,R91,R92,R93,R94,R156,R174,R182,R183,R184 10k R0402

32 1 R90 150k 1% R0402

33 3 R112,R133,R172 0 R0603

34 3 R157,R158,R159 270 1% R0402

35 1 R173 120k R0402

36 1 R175 200k Panasonic - ECG EVN-5ESX50B25,POT 200K OHM 3MM CARBON TRIM SMD

37 1 R176 56k R0402

38 1 R177 13.3k 1% R0402

39 2 R178,R179 2.2k R0402

40 16

SH1,SH2,SH3,SH4,SH5,SH6,SH7,SH8,SH9,SH10,SH11,SH12,SH13,SH14,SH

15,SH16

.100 in. Jumper Shunt

Sullins Electronics Corp. STC02SYANJUMPER SHORTING TIN

41 1 SW1 SW4_DIPSW4 CTS Corp 218-4LPST, DIPSW4,SWITCH DIP HALF PITCH 4POS

42 10SW2,SW3,SW4,SW5,SW6,SW7,SW8,SW9,SW10,S

W11SW TACT-SPST ITT Industries KSC201JLFS,

SWITCH TACT SILVR 120GF J-LEAD

43 2 TPGND1,TP3.3VDD1 TP_SMT Keystone 5015, TP_1206,PC TEST POINT MINIATURE SMT

44 1 U1 S2D13515PBGA256

45 1 U2 M25P32-VMF ST Microelectronics M25P32-VMF6P,IC SRL FLASH 32MBIT 3V 16-SOIC

46 2 U3,U4 128M16 DRAM Qimonda HYB39S128160FE-7,IC SDRAM 128MBit 54-TSOP

47 1 U5 MIC37100-1.8WS Micrel MIC37100-1.8WS, SOT-223,Alternate MIC39100-1.8WS

48 1 U6 LM2733YNational Semiconductor LM2733YMF/NOPB,

SOT23-5,IC CONV BOOST 40V FET SW SOT23-5

49 1 X1 MA-506 20.0000M Epson MA-506 20.0000M,CRYSTAL 20.0000MHZ 18PF SMD

50 0 Y1 14-Pin DIP AMP 2-641609-1Do not populate


Chapter 6 Schematic Diagrams



Figure 6-1: S5U13515P00C100 Schematics (1 of 5)

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

TDO

TMS

TDI

TCK

FP2I

O17

FP2I

O27

FP2I

O5

FP2I

O16

FP2I

O4

FP2I

O15

FP2I

O3

FP2I

O26

FP2I

O14

FP2I

O25

FP2I

O13

FP2I

O24

FP2I

O12

FP2I

O23

FP2I

O11

FP2I

O22

FP2I

O10

FP2I

O21

FP2I

O9

FP2I

O20

FP2I

O8

FP2I

O19

FP2I

O7

FP2I

O18

FP2I

O6

FP2I

O2

FP2I

O1

FP2I

O0

FP1I

O9

FP1I

O18

FP1I

O8

FP1I

O17

FP1I

O14

FP1I

O7

FP1I

O11

FP1I

O6

FP1I

O22

FP1I

O5

FP1I

O21

FP1I

O4

FP1I

O20

FP1I

O3

FP1I

O16

FP1I

O2

FP1I

O15

FP1I

O1

FP1I

O13

FP1I

O0

FP1I

O23

FP1I

O12

FP1I

O10

FP1I

O19

TCK

TMS

TDI

TDO

ME

MA

2M

EM

A1

ME

MA

12

ME

MA

0

ME

MA

11

ME

MA

8

ME

MA

10

ME

MA

6

ME

MA

9

ME

MA

5M

EM

A4

ME

MA

7

ME

MA

3

ME

MD

Q6

ME

MD

Q17

ME

MD

Q27

ME

MD

Q5

ME

MD

Q16

ME

MD

Q26

ME

MD

Q4

ME

MD

Q25

ME

MD

Q3

ME

MD

Q24

ME

MD

Q2

ME

MD

Q23

ME

MD

Q15

ME

MD

Q1

ME

MD

Q12

ME

MD

Q22

ME

MD

Q14

ME

MD

Q10

ME

MD

Q0

ME

MD

Q21

ME

MD

Q13

ME

MD

Q9

ME

MD

Q20

ME

MD

Q8

ME

MD

Q19

ME

MD

Q11

ME

MD

Q7

ME

MD

Q18

ME

MD

Q31

ME

MD

Q30

ME

MD

Q29

ME

MD

Q28

AB

20A

B19

AB

18A

B17

AB

16A

B15

AB

14A

B13

AB

12A

B11

AB

10A

B9

AB

8A

B7

AB

6A

B5

AB

4A

B3

AB

2A

B1

AB

0

DB

15D

B14

DB

13D

B12

DB

11D

B10

DB

9D

B8

DB

7D

B6

DB

5D

B4

DB

3D

B2

DB

1D

B0

AB

[20:

0]pB

S#

pFP

2IO

17

FP2I

O[2

7:0]

pFP

2IO

16pF

P2I

O10

pFP

2IO

14

pFP

2IO

11pF

P2I

O13

pAB

7pA

B8

pAB

9

pAB

6pA

B11

pAB

10

pDB

8

pDB

12

pDB

9

pDB

13

pDB

11

pDB

10

C33

_PE

DC

LK

C33

_PE

DS

T1C

33_P

ED

ST2

C33

_PE

DS

IO

C33

_PE

DS

T0C

33_P

ED

CP

CO

pAB

6pA

B7

pAB

8pA

B9

pAB

10pA

B11

pBS

#

pDB

8pD

B9

pDB

10pD

B11

pDB

12pD

B13

pFP

2IO

10pF

P2I

O11

pFP

2IO

13pF

P2I

O14

pFP

2IO

16pF

P2I

O17

1.8V

DD

CO

RE

HIO

VD

DH

IOP

IO1V

DD

PIO

1

IOV

DD

OS

C1.

8VD

D

PLL

21.

8VD

D

3.3V

DD S

DV

DD

PIO

2VD

DP

IO2

CM

1VD

DC

M1

1.8V

DD

PLL

1

GN

D3

GN

D2

GN

D1

IOV

DD

IO

HIO

VD

D_I

N

3.3V

DD

HIO

VD

D

PIO

1VD

D_I

N

3.3V

DD

PIO

1VD

D

PIO

2VD

D_I

N

3.3V

DD

PIO

2VD

D

CM

1VD

D_I

N

3.3V

DD

CM

1VD

D

IOV

DD

_IN

3.3V

DD

IOV

DD

GN

D1

GN

D2

GN

D3

SD

VD

DC

OR

EP

LL1

PLL

2O

SC

HIO

PIO

1P

IO2

IOC

M1

FP2I

O[2

7:0]

4

FP1I

O[2

3:0]

4,5

PW

M2

4P

WM

14

SC

L4,

5S

DA

4,5

CM

1DA

T45

CM

1CLK

OU

T5

CM

1FIE

LD5

CM

1DA

T55

CM

1VR

EF

5

CM

1DA

T65

CM

1DA

T25

CM

1DA

T15

CM

1DA

T05

CM

1CLK

IN5

CM

1DA

T35

CM

1HR

EF

5

CM

1DA

T75

ME

MA

[12:

0]2

ME

MC

LK2

ME

MC

KE

2

ME

MW

E#

2M

EM

CA

S#

2

ME

MC

S#

2M

EM

RA

S#

2

ME

MB

A1

2M

EM

BA

02

ME

MD

QM

12

ME

MD

QM

22

ME

MD

QM

32

ME

MD

QM

02

ME

MD

Q[3

1:0]

2

AB

[20:

0]2,

3,5

DB

[15:

0]3

CS

#3

TEA

#2,

3W

AIT

#3

IRQ

3

M/R

#3,

5R

D#

3R

D/W

R#

3B

E0#

3B

E1#

2,3

BS

#3

BU

RS

T#2,

3B

DIP

#2,

3

RE

SE

T#

2,3,

5

CN

F02

CN

F12

CN

F22

BU

SC

LK3

CLK

I2

OS

CI

2O

SC

O2

SP

IDIO

2

SP

ICS

#2

SP

ICLK

2

WS

IO4

SC

KIO

4S

DO

4M

CLK

O4

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and

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cap

on

each

CO

RE

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pin

of t

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2D13

515

Pla

ce a

0.0

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and

a 0.

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cap

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ach

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pin

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ce a

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and

a 0.

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cap

on

each

PIO

1VD

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pin

of t

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515

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ce a

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and

a 0.

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cap

on e

ach

OS

CV

DD

pow

er p

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S2D

1351

5

Pla

ce a

0.0

1uF

and

a 0.

1uF

cap

on e

ach

SD

VD

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pin

of t

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2D13

515

Pla

ce a

0.0

1uF

and

a 0.

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cap

on e

ach

PIO

2VD

D p

ower

pin

of t

he S

2D13

515

Pla

ce a

0.0

1uF

and

a 0.

1uF

cap

on e

ach

CM

1VD

D p

ower

pin

of t

he S

2D13

515

Pla

ce a

0.0

1uF

and

a 0.

1uF

cap

on

eac

hIO

VD

D p

ower

pin

of t

he S

2D13

515

Boa

rd d

efau

lt co

nfig

urat

ion:

-indi

rect

inte

rface

Inte

l 80,

16-

bit

-C33

Deb

ug p

ort f

rom

AB

[11:

6]-E

ID s

igna

ls fr

om F

P1I

O in

terfa

ce

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inte

rface

on

AB

[20:

12]

Sig

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race

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ssth

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cm.

Pla

ce th

ese

resi

stor

s as

cl

ose

to U

1 as

pos

sibl

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For I

ndire

ctH

ost

Inte

rface

For R

EG[0

01C

h] b

it 0

=1b

, C33

deb

ug p

ins

onFP

2IO

For D

irect

8-b

itIn

terfa

ce

R23

33 1

%R

2333

1%

R21

20

R21

20

R27

33 1

%R

2733

1%

R11

33 1

%R

1133

1%

C7

0.1u

F

C7

0.1u

F

R57

33 1

%R

5733

1%

123

JP7

HIO

VD

D S

OU

RC

E

JP7

HIO

VD

D S

OU

RC

E

R37

33 1

%R

3733

1%

C11

0.01

uF

C11

0.01

uF

R67

0R

670

C54

0.1u

F

C54

0.1u

F

R16

33 1

%R

1633

1%

R72

0_np

R72

0_np

C56

0.01

uF

C56

0.01

uF

R47

33 1

%R

4733

1%

R8

33 1

%R

833

1%

R13

33 1

%R

1333

1%

C16

0.01

uF

C16

0.01

uF

SH

7.1

00 in

. Jum

per

Shu

ntS

H7

.100

in. J

umpe

r S

hunt

C46

0.01

uF

C46

0.01

uF

C38

0.01

uF

C38

0.01

uF

L1 Ferr

iteL1 Fe

rrite

R22

33 1

%R

2233

1%

C62

0.01

uF

C62

0.01

uF

R24

33 1

%R

2433

1%

R21

30

R21

30

R58

33 1

%R

5833

1%

R43

33 1

%R

4333

1%

R7

33 1

%R

733

1%

123

JP12

CM

1VD

D S

OU

RC

E

JP12

CM

1VD

D S

OU

RC

E

R66

0R

660

C20

0.1u

F

C20

0.1u

F

R18

33 1

%R

1833

1%

L6 Ferr

iteL6 Fe

rrite

R48

33 1

%R

4833

1%

R71

0_np

R71

0_np

C6

0.1u

F

C6

0.1u

F

R81

0_np

R81

0_np

C10

0.01

uF

C10

0.01

uF

R38

33 1

%R

3833

1%

SH

12.1

00 in

. Jum

per

Shu

ntS

H12

.100

in. J

umpe

r S

hunt

12

JP4

OS

CV

DD

1

JP4

OS

CV

DD

1

C53

0.1u

F

C53

0.1u

F

R60

33 1

%R

6033

1%

C15

0.01

uF

C15

0.01

uF

R9

33 1

%R

933

1%

R14

33 1

%R

1433

1%

R17

33 1

%R

1733

1%

R29

33 1

%R

2933

1%

R15

33 1

%R

1533

1%

R52

0_np

R52

0_np

R32

33 1

%R

3233

1%

C22

10uF

C22

10uF

C31

0.1u

F

C31

0.1u

F

C37

0.01

uF

C37

0.01

uF

SH

4.1

00 in

. Jum

per S

hunt

SH

4.1

00 in

. Jum

per S

hunt

C52

0.1u

F

C52

0.1u

F

R65

0R

650

R59

33 1

%R

5933

1%

R80

0_np

R80

0_np

R21

00

R21

00

C5

0.1u

F

C5

0.1u

F

L5 Ferr

iteL5 Fe

rrite

R21

33 1

%R

2133

1%

C9

0.01

uF

C9

0.01

uF

R28

33 1

%R

2833

1%

R63

0R

630

C51

0.1u

F

C51

0.1u

F

R19

80_

npR

198

0_np

12

JP3

PLL

VD

D2

JP3

PLL

VD

D2

R1

33 1

%R

133

1%

C24

0.1u

F

C24

0.1u

F

C14

0.01

uF

C14

0.01

uF

R21

40

R21

40

C36

0.01

uF

C36

0.01

uF

R33

33 1

%R

3333

1%

R10

33 1

%R

1033

1%

C30

0.1u

F

C30

0.1u

F

SH

3.1

00 in

. Jum

per S

hunt

SH

3.1

00 in

. Jum

per S

hunt

R79

0_np

R79

0_np

123

JP13

IOV

DD

SO

UR

CE

JP13

IOV

DD

SO

UR

CE

L2 Ferr

iteL2 Fe

rrite

R12

33 1

%R

1233

1%

12

JP10

CM

1VD

D

JP10

CM

1VD

D

C42

0.1u

F

C42

0.1u

F

C50

0.1u

F

C50

0.1u

F

2 4 6 8 10 12

1 3 5 7 9 11

H1 JT

AG

H1 JT

AG

12

JP5

PIO

1VD

D

JP5

PIO

1VD

D

12

JP2

PLL

VD

D1

JP2

PLL

VD

D1

R25

33 1

%R

2533

1%

R20

20_

npR

202

0_np

C28

0.1u

F

C28

0.1u

FC4

0.1u

F

C4

0.1u

F

R3

33 1

%R

333

1%

SH

13.1

00 in

. Jum

per

Shu

ntS

H13

.100

in. J

umpe

r S

hunt

SH

11.1

00 in

. Jum

per S

hunt

SH

11.1

00 in

. Jum

per S

hunt

SH

5.1

00 in

. Jum

per S

hunt

SH

5.1

00 in

. Jum

per S

hunt

SH

2.1

00 in

. Jum

per S

hunt

SH

2.1

00 in

. Jum

per S

hunt

R45

33 1

%R

4533

1%

C57

0.01

uF

C57

0.01

uF

R49

33 1

%R

4933

1%

C13

0.01

uF

C13

0.01

uF

R39

33 1

%R

3933

1%

R21

50

R21

50

R78

0_np

R78

0_np

C29

0.1u

F

C29

0.1u

F

C34

0.01

uF

C34

0.01

uF

R70

0_np

R70

0_np

R76

0_np

R76

0_np

C49

0.1u

F

C49

0.1u

F

R20

30

R20

30

C41

0.1u

F

C41

0.1u

F

C18

1nF

C18

1nF

R44

33 1

%R

4433

1%

R2

33 1

%R

233

1%

R20

10_

npR

201

0_np

L3 Ferr

iteL3 Fe

rrite

123

JP8

PIO

1VD

D S

OU

RC

E

JP8

PIO

1VD

D S

OU

RC

E

R34

33 1

%R

3433

1%

C58

0.01

uF

C58

0.01

uF

R20

40

R20

40

C3

0.1u

F

C3

0.1u

F

R40

33 1

%R

4033

1%

R20

50

R20

50

C23

0.01

uF

C23

0.01

uF

R20

60

R20

60

12

JP14

IOV

DD

JP14

IOV

DD

R20

70

R20

70

R61

33 1

%R

6133

1%

R77

0_np

R77

0_np

2 4 6 8 10

1 3 5 7 9

H2

C33

DE

BU

G P

OR

T

H2

C33

DE

BU

G P

OR

T

R51

33 1

%R

5133

1%

C59

0.01

uF

C59

0.01

uF

R75

0_np

R75

0_np

C21

1nF

C21

1nF

R50

33 1

%R

5033

1%

R20

80

R20

80

C33

0.01

uF

C33

0.01

uF

R41

33 1

%R

4133

1%

12

JP6

HIO

VD

D

JP6

HIO

VD

D

C27

0.1u

F

C27

0.1u

F

C39

0.1u

F

C39

0.1u

F

R19

33 1

%R

1933

1%

123

JP9

PIO

2VD

D S

OU

RC

E

JP9

PIO

2VD

D S

OU

RC

E

SH

8.1

00 in

. Jum

per

Shu

ntS

H8

.100

in. J

umpe

r S

hunt

R20

00_

npR

200

0_np

C43

0.1u

F

C43

0.1u

F

SH

14.1

00 in

. Jum

per S

hunt

SH

14.1

00 in

. Jum

per S

hunt

SH

6.1

00 in

. Jum

per S

hunt

SH

6.1

00 in

. Jum

per S

hunt

R53

33 1

%R

5333

1%

C2

0.1u

F

C2

0.1u

F

R64

0_np

R64

0_np

C17

0.1u

F

C17

0.1u

F

R30

33 1

%R

3033

1%

R4

33 1

%R

433

1%

R35

33 1

%R

3533

1%

C60

0.01

uF

C60

0.01

uF

12

JP1

CO

RE

VD

D

JP1

CO

RE

VD

D

C40

0.1u

F

C40

0.1u

F

R20

33 1

%R

2033

1%

12

JP11

PIO

2VD

D

JP11

PIO

2VD

D

R74

0_np

R74

0_np

12

JP15

SD

VD

D

JP15

SD

VD

D

SH

9.1

00 in

. Jum

per

Shu

ntS

H9

.100

in. J

umpe

r S

hunt

C44

0.01

uF

C44

0.01

uF

FP2I

O16

T11

FP2I

O24

P9

FP2I

O22

M9

PIO2VDDR16

FP2I

O25

R9

FP2I

O26

K8

FP1I

O4

P7

FP1I

O5

R7

COREVDDM16

FP1I

O10

K7

FP1I

O23

T5

FP2I

O15

P11

PIO2VDDN9

COREVDDE1

CLK

IB

1

AB

0H

6

DB

13H

3

VSS A1

AB

17E

5

FP2I

O23

T10

DB

10J6

AB

8G

6

AB

1H

7

AB

18D

3

AB

7F2

AB

11F5

DB

14H

4

FP1I

O19

P3

FP1I

O21

N5

FP1I

O2

P8

FP2I

O21

L9

DB

9J3

FP1I

O1

M8

AB

19D

4

AB

20C

1

VSS A16

FP1I

O9

L7

FP1I

O3

R8

SD

ON

14

SP

ICS

#M

15

FP1I

O8

M7

FP1I

O16

L6FP

1IO

15M

6

FP1I

O20

P5

FP1I

O13

R5

AB

15D

1A

B14

E4

AB

13E

3A

B12

F6

HIOVDDL5

VSS E13

COREVDDL2

AB

10F3

AB

6F1

AB

5G

5A

B4

G4

AB

3G

3A

B2

G2

HIOVDDJ4

VSS B12

DB

15H

2

DB

12H

1D

B11

J7

MC

LKO

N16

SC

KIO

N15

FP2I

O0

P14

FP2I

O1

P16

FP2I

O2

P15

VSS J9

FP2I

O3

R15

FP2I

O4

R14

FP2I

O7

P13

FP2I

O8

N12

VSS J8

PIO2VDDR11

FP2I

O9

P12

FP2I

O10

K10

FP2I

O11

T13

FP2I

O13

L10

FP1I

O17

R3

FP1I

O14

P4

FP1I

O11

T3

VSS E15

PIO1VDDT8

RE

SE

T#R

2

VSS F4

FP1I

O6

T7

FP1I

O0

L8

AB

16D

2

VSS K14

IOVDDM14

PW

M1

M13

AB

9G

7

FP1I

O18

T2

FP1I

O22

R4

PIO1VDDT6

FP1I

O12

R6

FP1I

O7

N7

VSS G13

FP2I

O27

T9

VSS H8

FP2I

O18

K9

FP2I

O20

R10

FP2I

O19

P10

PIO1VDDT4

FP2I

O17

N10

VSS H9

FP2I

O14

N11

FP2I

O12

R12

FP2I

O6

M11

FP2I

O5

T15

WS

ION

13

PW

M2

M12

COREVDDD6

SP

ICLK

L12

PIO2VDDT14

DB

8J2

VSS C2

BU

SC

LKJ1

HIOVDDE2

DB

7J5

DB

6K

5D

B5

K4

DB

4K

3D

B3

K1

DB

2K

2D

B1

K6

DB

0L1

VSS C7

COREVDDE16

HIOVDDG1

CS

#L3

M/R

#M

1

RD

#M

2

RD

/WR

#M

3

BE

0#M

4

BE

1#N

1

BS

#M

5

BU

RS

T#N

2

BD

IP#

N3

TEA

#P

2

WA

IT#

P1

IRQ

R1

VSS D11

SP

IDIO

L11

TES

TEN

L14

TDO

L15

TCK

K11

TDI

L16

TMS

K12

TRS

TK

13

VSS L4

CN

F2K

16C

NF1

K15

CN

F0J1

0

ME

MD

QM

3J1

1M

EM

DQ

M2

J12

ME

MD

QM

1J1

3M

EM

DQ

M0

J14

ME

MC

KE

J16

ME

MC

S#

J15

ME

MR

AS

#H

15

ME

MC

AS

#H

16

VSS L13

SDVDDH14

ME

MW

E#

H13

ME

MB

A1

H12

ME

MB

A0

H11

ME

MA

12G

16M

EM

A11

H10

ME

MA

10G

15M

EM

A9

G14

ME

MA

8F1

5

VSS M10

SDVDDE11

ME

MD

Q31

G12

ME

MD

Q15

G11

ME

MD

Q30

F14

ME

MD

Q14

F13

VSS N4

COREVDDN6

ME

MD

Q29

F12

ME

MD

Q13

G10

ME

MD

Q28

D13

ME

MD

Q12

D16

ME

MD

Q27

E14

VSS N8

SDVDDD14

ME

MD

Q11

C16

ME

MD

Q26

D15

ME

MD

Q10

B16

ME

MD

Q25

C15

ME

MD

Q9

C14

ME

MD

Q24

B15

SDVDDB10

VSS H5

ME

MD

Q8

B14

ME

MD

Q23

A14

ME

MD

Q7

E12

ME

MD

Q22

C13

ME

MD

Q6

B13

ME

MD

Q21

A13

ME

MD

Q5

F11

ME

MD

Q20

D12

SDVDDA15

COREVDDT12

VSS T16

ME

MC

LKA

12

VSS T1

ME

MD

Q4

C11

ME

MD

Q19

F10

ME

MD

Q3

G9

ME

MD

Q18

B11

ME

MD

Q2

E10

ME

MD

Q17

F9

ME

MD

Q1

A11

ME

MD

Q16

D10

ME

MD

Q0

C10

VSS R13

SDVDDF16

ME

MA

7E

9M

EM

A6

A10

ME

MA

5D

9M

EM

A4

G8

ME

MA

3C

9M

EM

A2

F8M

EM

A1

B9

ME

MA

0A

9

SC

LE

8

SD

AD

8

CM

1FIE

LDC

8

CM

1VR

EF

B8

CM

1HR

EF

F7

CM1VDDE7

CM

1DA

T7E

6C

M1D

AT6

D7

CM

1DA

T5A

8

CM

1CLK

OU

TA

7

VSS P6

CM

1CLK

INB

7

COREVDDC12

CM

1DA

T4D

5C

M1D

AT3

C6

CM

1DA

T2C

5C

M1D

AT1

C4

CM

1DA

T0C

3

OSCVSS B6

OS

CO

A6

OS

CI

A5

OSCVDDB5

PLL2VSS B4

VC

P2

A4

PLL2VDDA3

PLL1VSS B3

VC

P1

A2

PLL1VDDB2

S2D

1351

5PB

GA

256

U1

S2D

1351

5PB

GA

256

U1

SH

1.1

00 in

. Jum

per S

hunt

SH

1.1

00 in

. Jum

per S

hunt

C26

0.1u

F

C26

0.1u

F

R69

0R

690

R21

10

R21

10

C32

0.01

uF

C32

0.01

uF

L4 Ferr

iteL4 Fe

rrite

R19

90_

npR

199

0_np

C19

10uF

C19

10uF

SH

10.1

00 in

. Jum

per S

hunt

SH

10.1

00 in

. Jum

per S

hunt

R26

33 1

%R

2633

1%

C35

0.01

uF

C35

0.01

uF

R54

33 1

%R

5433

1%

R31

33 1

%R

3133

1%

R5

33 1

%R

533

1%

C47

0.01

uF

C47

0.01

uF

SH

15.1

00 in

. Jum

per S

hunt

SH

15.1

00 in

. Jum

per S

hunt

C1

0.1u

F

C1

0.1u

F

C48

0.01

uF

C48

0.01

uF

R36

33 1

%R

3633

1%

C55

0.1u

F

C55

0.1u

F

C8

0.1u

F

C8

0.1u

F

R62

33 1

%R

6233

1%

R73

0_np

R73

0_np

C12

0.01

uF

C12

0.01

uF

R20

90

R20

90

R42

33 1

%R

4233

1%

R55

33 1

%R

5533

1%

C61

0.01

uF

C61

0.01

uF

R46

33 1

%R

4633

1%

R6

33 1

%R

633

1%

R68

0R

680

R19

70_

npR

197

0_np

C25

0.1u

F

C25

0.1u

F

R56

0R

560

C45

0.01

uF

C45

0.01

uF




5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

ME

MD

Q4

ME

MD

Q27

ME

MD

Q21

ME

MD

Q2

ME

MD

Q19

ME

MD

Q7

ME

MD

Q31

ME

MD

Q13

ME

MD

Q3

ME

MD

Q24

ME

MD

Q30

ME

MD

Q22

ME

MD

Q1

ME

MD

Q15

ME

MD

Q11

ME

MD

Q10

ME

MD

Q8

ME

MD

Q23

ME

MD

Q16

ME

MD

Q26

ME

MD

Q14

ME

MD

Q25

ME

MD

Q9

ME

MD

Q0

ME

MD

Q12

ME

MD

Q6

ME

MD

Q5

ME

MD

Q18

ME

MD

Q29

ME

MD

Q28

ME

MD

Q20

ME

MD

Q17

ME

MA

5

ME

MA

2M

EM

A3

ME

MA

9

ME

MA

6

ME

MA

8

ME

MA

1M

EM

A0

ME

MA

10

ME

MA

7

ME

MA

11

ME

MA

4

ME

MA

7M

EM

A8

ME

MA

5

ME

MA

0M

EM

A1

ME

MA

4M

EM

A3

ME

MA

6

ME

MA

10M

EM

A11

ME

MA

2

ME

MA

9

ME

MB

A1

ME

MB

A0

ME

MW

E#

ME

MC

AS

#M

EM

RA

S#

ME

MC

S#

ME

MC

KE

ME

MC

LK

ME

MB

A0

ME

MC

AS

#M

EM

RA

S#

ME

MC

LK

ME

MB

A1

ME

MC

KE

ME

MW

E#

ME

MC

S#

ME

MA

12

ME

MA

12

AB

0

AB

4A

B3

3.3V

DD

3.3V

DD

3.3V

DD

3.3V

DD

3.3V

DD

HIO

VD

D

3.3V

DD

1.8V

DD

3.3V

DD

3.3V

DD

HIO

VD

D

GN

D3

GN

D3

HIO

VD

D

IOV

DD

ME

MD

Q[3

1:0]

1

ME

MD

Q[3

1:0]

1

ME

MA

[12:

0]1

ME

MA

[12:

0]1

ME

MB

A0

1M

EM

BA

11

ME

MC

S#

1

ME

MW

E#

1M

EM

CA

S#

1M

EM

RA

S#

1

ME

MD

QM

01

ME

MD

QM

11

ME

MD

QM

21

ME

MD

QM

31

ME

MC

KE

1M

EM

CLK

1

OS

CI

1

CLK

I1

OS

CO

1S

PIC

S#

1S

PIC

LK1

SP

IDIO

1

RE

SE

T#1,

3,5

BE

1#1,

3B

UR

ST#

1,3

BD

IP#

1,3

TEA

#1,

3

AB

[20:

0]1,

3,5

CN

F01

CN

F11

CN

F21

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

<Doc

>1.

0

SD

RA

M /

Flas

h / C

lock

s / R

eset

/ 1.

8V S

uppl

y

B

25

Thur

sday

, May

15,

200

8

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

<Doc

>1.

0

SD

RA

M /

Flas

h / C

lock

s / R

eset

/ 1.

8V S

uppl

y

B

25

Thur

sday

, May

15,

200

8

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

<Doc

>1.

0

SD

RA

M /

Flas

h / C

lock

s / R

eset

/ 1.

8V S

uppl

y

B

25

Thur

sday

, May

15,

200

8

SD

RA

M I/

F1-

2 32

BIT

2-3

16B

IT

Pla

ce a

0.0

1uF

and

a 0.

1uF

cap

on e

ach

VD

D p

ower

pin

of t

he tw

o S

DR

AM

chi

ps.

Pla

ce a

0.0

1uF

and

a 0.

1uF

cap

on e

ach

VD

DQ

pow

er p

in o

f the

two

SD

RA

M c

hips

.

TTL/

CM

OS

Osc

illat

or

This

resi

stor

is u

sed

topu

ll do

wn

CLK

I inp

ut w

hen

osci

llato

r is

not u

sed.

If an

osc

illat

or is

use

d,th

en th

is re

sist

or c

an b

ere

mov

ed.

CN

F3

CN

F4

CN

F5C

NF6

CN

F7

C87

0.1u

F

C87

0.1u

F

C64

10uF

C64

10uF

2 431

SW

2

SW

TA

CT-

SP

ST

SW

2

SW

TA

CT-

SP

ST

1234

8765

SW

1S

W4_

DIP

SW

4S

W1

SW

4_D

IPS

W4

R84

1kR84

1k

C76

0.1u

F

C76

0.1u

F

C99

0.01

uF

C99

0.01

uF

R90

150k

1%

R90

150k

1%

R10

30R

103

0

XIN

1X

OU

T4

NC

2N

C3

X1

MA

-506

20.

0000

M

X1

MA

-506

20.

0000

M

C88

0.01

uF

C88

0.01

uF

C82

0.1u

F

C82

0.1u

FR

107

0R10

70

R87

0R

870

C94

0.01

uF

C94

0.01

uF

C63

0.1u

FC

630.

1uF

R98

0_np

R98

0_np

R95

0_np

R95

0_np

C77

0.1u

F

C77

0.1u

F

NC

3

NC

4

NC

5N

C6

NC

11

NC

12N

C13

NC

14

CLK

16C

S#

7

DIN

15

DO

UT

8

HO

LD#

1

VCC

2

VS

S10

W#/

VP

P9

U2 M25

P32

-VM

F

U2 M25

P32

-VM

F

R10

40_

npR

104

0_np

C10

0

0.01

uF

C10

0

0.01

uF

R89

10k

R89

10k

C72

0.1u

F

C72

0.1u

F

TP1

TP1

C67

0.1u

F

C67

0.1u

F

R92

10k

R92

10k

C89

0.01

uF

C89

0.01

uF

C83

0.1u

F

C83

0.1u

F

C73

10uF

C73

10uF

C95

0.01

uF

C95

0.01

uF

A0

23A

124

A2

25A

326

A4

29A

530

A6

31A

732

A8

33A

934

A10

22A

1135

BA

121

BA

020

VSS

Q6

VSS

Q12

VSS

Q52

VSS

28VS

S41

VSS

54

VSS

Q46

VD

D1

VD

D14

VD

D27

VD

DQ

3

VD

DQ

9

VD

DQ

43V

DD

Q49

D0

2

D1

4D

25

D3

7

D4

8

D5

10D

611

D7

13

D8

42D

944

D10

45

D11

47D

1248

D13

50

D14

51

D15

53

DQ

ML

15D

QM

H39

WE

#16

CA

S#

17

RA

S#

18C

S#

19

CLK

38C

KE

37

NC

40

NC

/A12

36

SDRAM128Mb x 16-bit x 4banks

U3

128M

16 D

RA

M


U3

128M

16 D

RA

M

R10

50R

105

0

C66

18pF

C66

18pF

C78

0.1u

F

C78

0.1u

F

C69

0.1u

F

C69

0.1u

F

C10

1

0.01

uF

C10

1

0.01

uF

SH

16.1

00 in

. Jum

per S

hunt

SH

16.1

00 in

. Jum

per S

hunt

123JP16

SD

RA

M I/

F

JP16

SD

RA

M I/

F

C90

0.01

uF

C90

0.01

uF

C84

0.1u

F

C84

0.1u

F

R88

33 1

%R

8833

1%

IN1

OU

T3

GND 2

TAB 4

U5

MIC

3710

0-1.

8WS

U5

MIC

3710

0-1.

8WS

R99

0_np

R99

0_np

C96

0.01

uF

C96

0.01

uF

R96

0_np

R96

0_np

R10

60_

npR

106

0_np

C70

10uF

C70

10uF

C79

0.1u

F

C79

0.1u

F

R85

0R

850

OE

1

OU

T8

GN

D7

VD

D14

Y1

14-P

in D

IP

Y1

14-P

in D

IP

C71

0.1u

F

C71

0.1u

F

R9310k R9310k

R91

10k

R91

10k

R83

0R

830

C91

0.01

uF

C91

0.01

uF

C85

0.1u

F

C85

0.1u

FR

108

0_np

R10

80_

np

C74

0.1u

F

C74

0.1u

F

C97

0.01

uF

C97

0.01

uF

C80

0.1u

F

C80

0.1u

F

R86

0R

860

R82

1MR

821M

C92

0.01

uF

C92

0.01

uF

C86

0.1u

F

C86

0.1u

F

R10

10_

npR

101

0_np

R94

10k

R94

10k

C68

0.01

uF

C68

0.01

uF

R97

0_np

R97

0_np

C75

0.1u

F

C75

0.1u

F

A0

23A

124

A2

25A

326

A4

29A

530

A6

31A

732

A8

33A

934

A10

22A

1135

BA

121

BA

020

VSS

Q6

VSS

Q12

VSS

Q52

VSS

28VS

S41

VSS

54

VSS

Q46

VD

D1

VD

D14

VD

D27

VD

DQ

3

VD

DQ

9

VD

DQ

43V

DD

Q49

D0

2

D1

4D

25

D3

7

D4

8D

510

D6

11

D7

13

D8

42D

944

D10

45

D11

47D

1248

D13

50

D14

51D

1553

DQ

ML

15D

QM

H39

WE

#16

CA

S#

17

RA

S#

18C

S#

19

CLK

38C

KE

37

NC

40

NC

/A12

36


U4

128M

16 D

RA

M


U4

128M

16 D

RA

M

C98

0.01

uF

C98

0.01

uF

R10

00_

npR

100

0_np

C65

18pF

C65

18pF

C81

0.1u

F

C81

0.1u

FR

102

0R10

20

C93

0.01

uF

C93

0.01

uF




5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

AB

19A

B17

AB

9

AB

15A

B13

AB

11A

B12

AB

14

AB

4A

B6

AB

18A

B20

AB

3

AB

7A

B5

RD

/WR

#

BE

0#

DB

12D

B14

DB

1D

B3

DB

5D

B7

DB

8D

B10

DB

15D

B13

DB

11

DB

0

DB

9

DB

2D

B4

DB

6

AB

20A

B18

AB

16A

B14

AB

12A

B10

AB

8A

B7

AB

5A

B3

AB

1

AB

17A

B19

AB

0A

B2

AB

4A

B6

AB

9A

B11

AB

13A

B15

HE

AR

TBE

AT

EN

UM

ER

ATE

D

HE

AR

TBE

AT

EN

UM

ER

ATE

D

CS

#M

/R#

DB

13

DB

15D

B14

BE

1#R

D#

DB

11

DB

8

DB

12

DB

9D

B10

DB

6D

B7

DB

3D

B4

DB

5

AB

1A

B2

DB

2

DB

1D

B0

AB

0

BE

1#

RD

#

WA

IT#

IRQ

AB

16

CS

#M

/R#

BE

0#R

D/W

R#

IRQ

WA

IT#

AB

10A

B8

AB

2A

B1

HIO

VD

D

3.3V

DD

3.3V

DD

3.3V

DD

HIO

VD

DH

IOV

DD

_IN

RD

#1

BE

1#1,

2

BS

#1

DB

[15:

0]1

BU

SC

LK1

RD

/WR

#1

CS

#1

M/R

#1,

5

BE

0#1

TEA

#1,

2IR

Q1

WA

IT#

1B

DIP

#1,

2R

ES

ET#

1,2,

5

AB

[20:

0]1,

2,5

BU

RS

T#1,

2

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

<Doc

>1.

0

Hos

t con

nect

ors

B

35

Tues

day,

Aug

ust 1

9, 2

008

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

<Doc

>1.

0

Hos

t con

nect

ors

B

35

Tues

day,

Aug

ust 1

9, 2

008

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

<Doc

>1.

0

Hos

t con

nect

ors

B

35

Tues

day,

Aug

ust 1

9, 2

008

This resistor is used to pull

down BUSCLK input when it is

not used. If BUSCLK input is

used, then this resistor can

be removed.

Place these resistors as close as possible

to H3 and H4 headers.

R200 and R201 are not

resistors on PCB. They

are external wires

added to the board.

R202 and R203 are not

resistors on PCB. They

are external wires

added to the board.

R11

30_

npR

113

0_np

R12

80

R12

80

R14

60_

npR

146

0_np

TP2

TP2

R13

60_

npR

136

0_np

R13

30

R13

30

R12

00

R12

00

D1

LED

1D

1LE

D1

A K

R14

50_

npR

145

0_np

R13

10

R13

10

R11

10

R11

10

R15

727

0 1%

R15

727

0 1%

R13

00

R13

00

R11

70

R11

70

R13

90_

npR

139

0_np

R15

30_

npR

153

0_np

R15

20_

npR

152

0_np

R20

20

R20

20

R14

20_

npR

142

0_np

R11

40

R11

40

R12

20

R12

20

R11

90

R11

90 TP

GN

D1

TP_S

MT

TPG

ND

1TP

_SM

T

1

R14

70_

npR

147

0_np

R20

30

R20

30

H4

HE

AD

ER

_17X

2

H4

HE

AD

ER

_17X

2

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33

R15

927

0 1%

R15

927

0 1%

R14

90_

npR

149

0_np

P2

HE

AD

ER

_20X

2

P2

HE

AD

ER

_20X

2

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39

R13

80_

npR

138

0_np

R12

10

R12

10

R12

50

R12

50

R14

10_

npR

141

0_np

R15

40

R15

40

D3

3.3V

Pow

erD

33.

3V P

ower

A K

R13

20

R13

20

R10

90

R10

90

R11

50

R11

50

R12

30

R12

30

R15

50_

npR

155

0_np

R13

50_

npR

135

0_np

R14

40_

npR

144

0_np

R15

610

kR

156

10k

R11

60

R11

60

R14

80_

npR

148

0_np

R12

70

R12

70

H3

HE

AD

ER

_20X

2

H3

HE

AD

ER

_20X

22 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39

R13

40_

npR

134

0_np

TP3.

3VD

D1

TP_S

MT

TP3.

3VD

D1

TP_S

MT

1

R20

00

R20

00

R12

40

R12

40

R11

00

R11

00

R14

30_

npR

143

0_np

R15

10_

npR

151

0_np

R15

827

0 1%

R15

827

0 1%

R14

00_

npR

140

0_np

R11

80

R11

80

R11

20

R11

20

R20

10

R20

10

R12

60

R12

60

R12

90

R12

90

R13

70_

npR

137

0_np

R15

00_

npR

150

0_np

D2

LED

2D

2LE

D2

A K

P1

HE

AD

ER

_20X

2

P1

HE

AD

ER

_20X

2

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39




5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

FPD

AT4

FP2I

O4

FPD

AT2

FP2I

O2

FPD

AT3

FP2I

O3

FPD

AT1

FP2I

O1

FPD

AT0

FP2I

O0

FPD

AT6

FP2I

O6

FPD

AT9

FP2I

O9

FPD

AT5

FP2I

O5

FPD

AT8

FP2I

O8

FPD

AT7

FP2I

O7

FPD

AT1

1FP

2IO

11FP

DA

T10

FP2I

O10

FPD

AT1

4FP

2IO

14FP

DA

T13

FP2I

O13

FPD

AT1

2FP

2IO

12

FPFR

AM

EFP

2IO

25FP

LIN

EFP

2IO

24

FPD

AT1

5FP

2IO

15FP

SH

IFT

FP2I

O27

FPD

AT1

6FP

2IO

16FP

DA

T17

FP2I

O17

FPD

AT1

9FP

2IO

19

PO

LGM

A

FPD

AT2

1FP

2IO

21

CP

V

FPD

AT2

3FP

2IO

23

DE

XR FP

DA

T20

FP2I

O20

FP2I

O26

OE

FPD

AT2

2FP

2IO

22

FPD

RD

YFP

2IO

26

FP1I

O0

FP1I

O1

FP1I

O2

FP1I

O3

FP1I

O5

FP1I

O6

FP1I

O4

FP1I

O7

FP1I

O10

FP1I

O13

FP1I

O8

FP1I

O12

FP1I

O9

FP1I

O15

FP1I

O14

FP1I

O11

FP1I

O23

FP1I

O21

FP1I

O20

FP1I

O22

FP1I

O17

FP1I

O16

FP2I

O25

PO

LGM

AFP

1IO

11

DE

XR

FP1I

O14

CP

VFP

1IO

17

OE

FP1I

O18

LED

_DIM

_OU

TFP

1IO

19P

WM

1

LED

_DIM

_OU

T

FP2I

O18

FP2I

O21

FPS

O

FP2I

O24

FP2I

O18

FP2I

O19

FP2I

O20

PW

M1

SC

KIO

SD

OW

SIO

MC

LKO

WS

IO

SC

KIO

SD

O

MC

LKO

VB

AC

KLI

GH

TP

IO2V

DD

VB

AC

KLI

GH

T3.

3VD

D

PIO

1VD

D VB

AC

KLI

GH

T

PIO

1VD

D_I

NP

IO2V

DD

_IN

CM

1VD

D_I

NIO

VD

D_I

N

IOV

DD

FP2I

O[2

7:0]

1FP

1IO

[23:

0]1,

5

SC

KIO

1

PW

M2

1

WS

IO1

SD

A1,

5S

CL

1,5

PW

M1

1

MC

LKO

1

SD

O1

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

<Doc

>1.

0

LCD

, I2S

and

PW

M c

onne

ctor

s

B

45

Thur

sday

, May

15,

200

8

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

<Doc

>1.

0

LCD

, I2S

and

PW

M c

onne

ctor

s

B

45

Thur

sday

, May

15,

200

8

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

<Doc

>1.

0

LCD

, I2S

and

PW

M c

onne

ctor

s

B

45

Thur

sday

, May

15,

200

8

Adj

usta

ble

Ste

p U

p P

ower

Sup

ply

12V

@ 1

00m

A to

25V

@60

mA

Vou

t=1.

23x[

1+(R

17+R

20)/

R19

] (V

)

Pla

ce th

ese

resi

stor

s cl

ose

toH

8 co

nnec

tor.

Pla

ce th

ese

resi

stor

s cl

ose

toH

6 co

nnec

tor.

Pla

ce th

ese

resi

stor

s cl

ose

toH

7 co

nnec

tor.

R16

40

R16

40

R21

60_

npR

216

0_np

C10

310

uF 3

5VC

103

10uF

35V

VIN

5

/SH

DN

4G

ND

2

SW

1

FB3

U6

LM27

33Y

U6

LM27

33Y

R17

10

R17

10

R21

90_

npR

219

0_np

1 3

2

R17

520

0kR

175

200k

R17

410

kR

174

10k

R16

70_

npR

167

0_np

2 4 6 8 10

1 3 5 7 9

H9

PW

M/P

WR

PO

RT

H9

PW

M/P

WR

PO

RT

R17

3

120kR

173

120k

R17

20

R17

20

R16

80

R16

80

R16

90_

npR

169

0_np

R21

70_

npR

217

0_np

R17

713

.3k

1%R

177

13.3

k 1%

R16

00

R16

00

2 4 6 8 10 12 14 16 18 20 22 24

1 3 5 7 9 11 13 15 17 19 21 23

H8

I2S

PO

RT

H8

I2S

PO

RT

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39

H5

FP2

LCD

Con

nect

or

H5

FP2

LCD

Con

nect

or

C10

2

2.2u

F 10

VC10

2

2.2u

F 10

V

R17

00_

npR

170

0_np

R17

6

56k

R17

6

56k

AK

D4

MB

R05

40D

4M

BR

0540

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39

H6

FP1

LCD

Con

nect

or

H6

FP1

LCD

Con

nect

or

R16

20

R16

20

R16

30_

npR

163

0_np

R16

60

R16

60

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39

H7

FP2

Ext

ende

d LC

D C

onne

ctor

H7

FP2

Ext

ende

d LC

D C

onne

ctor

1

2

3

F2 AC

F451

832-

222

F2 AC

F451

832-

222

TP3

TP3

R21

80_

npR

218

0_np

L7 10uH

L7 10uH

R16

50_

npR

165

0_np

C10

4

150p

F

C10

4

150p

F

1

2

3

F1 AC

H32

C-3

33-T

F1 AC

H32

C-3

33-T

R16

10_

npR

161

0_np




5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

KB

C0

KB

C1

KB

C2

KB

R0

KB

R0

FP1I

O16

FP1I

O20

FP1I

O15

FP1I

O22

FP1I

O21

FP1I

O23

AB

20

KB

R1

KB

R2

KB

C0

KB

C1

KB

C2

AB

14A

B15

AB

16

AB

19

KB

R1

KB

R2

CM

1VD

D

CM

1VD

DH

IOV

DD

PIO

1VD

D

CM

1VD

D

CM

1CLK

OU

T1

SC

L1,

4S

DA

1,4

CM

1DA

T01

CM

1DA

T21

CM

1DA

T41

CM

1DA

T61

CM

1CLK

IN1

CM

1DA

T11

CM

1DA

T31

CM

1DA

T51

CM

1DA

T71

CM

1VR

EF

1C

M1H

RE

F1

CM

1FIE

LD1

RE

SE

T#1,

2,3

M/R

#1,

3

FP1I

O[2

3:0]

1,4

AB

[20:

0]1,

2,3

Title

Siz

eD

ocum

ent N

umbe

rR

ev

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e:S

heet

of

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Cam

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55

Thur

sday

, May

15,

200

8

Title

Siz

eD

ocum

ent N

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ev

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e:S

heet

of

<Doc

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era

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Thur

sday

, May

15,

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Title

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eD

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ent N

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0

Cam

era

i/f, K

eypa

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Thur

sday

, May

15,

200

8

Pla

ce th

ese

capa

cito

rs c

lose

to p

in 1

5 of

the

head

er.

If K

ypad

i/f f

rom

FP1I

O p

ins,

pop

ulat

eth

is re

sist

or

If K

ypad

i/f i

s fro

m M

/R#,

AB

pins

, pop

ulat

e th

is re

sist

or

Pla

ce th

ese

resi

stor

s as

clos

e to

the

S2D

1351

5 as

poss

ible

.

0 5

10

1 6

11

2 7

12

Silk

scre

enw

ith K

eypa

dM

atrix

Ord

er

AK

D8

MB

R05

40

D8

MB

R05

40

R19

50_

npR

195

0_np

AK

D13

MB

R05

40

D13

MB

R05

40

2 431

SW

11S

W T

AC

T-S

PS

TS

W11

SW

TA

CT-

SP

ST

2 431

SW

8S

W T

AC

T-S

PS

TS

W8

SW

TA

CT-

SP

ST

2 431

SW

5S

W T

AC

T-S

PS

TS

W5

SW

TA

CT-

SP

ST

R19

30_

npR

193

0_np

R18

10_

npR

181

0_np

AK

D10

MB

R05

40

D10

MB

R05

40

C10

5

1uF

C10

5

1uF

R18

60

R18

60

R18

210

kR

182

10k

C10

6

0.1u

F

C10

6

0.1u

F

R18

70

R18

70

AK

D7

MB

R05

40

D7

MB

R05

40

2 431

SW

10S

W T

AC

T-S

PS

TS

W10

SW

TA

CT-

SP

ST

AK

D12

MB

R05

40

D12

MB

R05

40

2 431

SW

7S

W T

AC

T-S

PS

TS

W7

SW

TA

CT-

SP

ST

R18

80

R18

80

R18

50

R18

50

2 431

SW

4S

W T

AC

T-S

PS

TS

W4

SW

TA

CT-

SP

ST

R19

00

R19

00

AK

D9

MB

R05

40

D9

MB

R05

40

R18

410

kR

184

10k

R18

90

R18

90

R17

82.

2kR

178

2.2k

1 3 5 7 9 11 13 15 17 19

2 4 6 8 10 12 14 16 18 20

H10

CA

ME

RA

1

H10

CA

ME

RA

1

R18

00

R18

00

R18

310

kR

183

10k

R19

20_

npR

192

0_np

AK

D5

MB

R05

40

D5

MB

R05

40

2 431

SW

9S

W T

AC

T-S

PS

TS

W9

SW

TA

CT-

SP

ST

AK

D6

MB

R05

40

D6

MB

R05

40

2 431

SW

6S

W T

AC

T-S

PS

TS

W6

SW

TA

CT-

SP

ST

R19

40_

npR

194

0_np

R17

92.

2kR

179

2.2k

AK

D11

MB

R05

40

D11

MB

R05

40

R19

60_

npR

196

0_np

2 431

SW

3S

W T

AC

T-S

PS

TS

W3

SW

TA

CT-

SP

ST

R19

10_

npR

191

0_np

Chapter 7 Board Layout



Figure 7-1: S5U13515P00C100 Board Layout - Top View



Figure 7-2: S5U13515P00C100 Board Layout - Bottom View

Chapter 8 References



8.1 Documents• Epson Research and Development, Inc., S2D13515 Hardware Functional Specification, document number

X83A-A-001-xx.

8.2 Document Sources• Epson Research and Development Website: http://www.erd.epson.com.



Change Record

X83A-G-001-01 Revision 1.1 - Issued: September 9, 2009

• section 4.8 Keypad Interface - add note “The keyboard is non-operational with the buttons SW3-SW11, mounted as they are on the board...” to start of section

X83A-G-001-01 Revision 1.0 - Issued: January 20, 2009

• Release as Revision 1.0

• section 3.1.2 CNF[7:3] - correct typo in table change “R104” to “R107”

• chapter 6 Schematic Diagrams - replace figure 6-3

X83A-G-001-00 Revision 0.03 - Issued: June 3, 2008

• globally add missing Figures

• globally add missing resistor numbers

• chapter 2 Features -in second bullet change “64MB” to “32 MB” and “32MB” to “16MB” respectively

• chapter 5 Parts List - add parts list data

• chapter 6 Schematic Diagrams - update all schematic diagrams

• chapter 7 Board Layout - add figures

X83A-G-001-00 Revision 0.02 - Issued: April 24, 2008

• section 2, changed package from QFP22 to PBGA

• section 2, changed “Headers for connection to cameras” to “Header for connection to cameras”

• section 2, removed “On-board video decoder allowing direct connection of an analog camera”

• section 2, changed on-board keypad from “5x5” to “3x3”

• section 4.4.1, changed the SDRAM size from 256Mbit to 128Mbit

• section 4.7.1, removed Analog Camera and Video Decoder section

• section 4.8, changed 5x5 keypad to 3x3 keypad and updated keypad diagram

• section 6, updated schematic diagrams

X83A-G-001-00 Revision 0.01 - Issued: February 11, 2008

• initial draft of the user manual

• minor edits and formatting

Document Code: X83A-G-001-01Issued 2009/01/20

International Sales Operations

AMERICA EPSON ELECTRONICS AMERICA, INC. 2580 Orchard Parkway San Jose, CA 95131,USA Phone: +1-800-228-3964 FAX: +1-408-922-0238

EUROPEEPSON EUROPE ELECTRONICS GmbH Riesstrasse 15, 80992 Munich,GERMANY Phone: +49-89-14005-0 FAX: +49-89-14005-110

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Beijing 100005, CHINAPhone: +86-10-6410-6655 FAX: +86-10-6410-7320

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EPSON HONG KONG LTD.20/F, Harbour Centre, 25 Harbour Road Wanchai, Hong Kong Phone: +852-2585-4600 FAX: +852-2827-4346 Telex: 65542 EPSCO HX

SHENZHEN BRANCH12F, Dawning Mansion, Keji South 12th Road,Hi-Tech Park, Shenzhen 518057, CHINAPhone: +86-755-2699-3828 FAX: +86-755-2699-3838

EPSON TAIWAN TECHNOLOGY & TRADING LTD.14F, No. 7, Song Ren Road, Taipei 110, TAIWANPhone: +886-2-8786-6688 FAX: +886-2-8786-6660

EPSON SINGAPORE PTE., LTD.1 HarbourFront Place, #03-02 HarbourFront Tower One, Singapore 098633 Phone: +65-6586-5500 FAX: +65-6271-3182

SEIKO EPSON CORP. KOREA OFFICE 50F, KLI 63 Bldg., 60 Yoido-dong Youngdeungpo-Ku, Seoul, 150-763, KOREA Phone: +82-2-784-6027 FAX: +82-2-767-3677

SEIKO EPSON CORP. SEMICONDUCTOR OPERATIONS DIVISION

IC Sales Dept.IC International Sales Group 421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone: +81-42-587-5814 FAX: +81-42-587-5117

Dongcheng District,