Microelectronics Reliability 54 (2014) 2604–2612

Contents lists available at ScienceDirect

Microelectronics Reliability

journal homepage: www.elsevier .com/locate /microrel

Robust FinFET SRAM design based on dynamic back-gate voltageadjustment

http://dx.doi.org/10.1016/j.microrel.2014.04.0150026-2714/� 2014 Elsevier Ltd. All rights reserved.

⇑ Corresponding author. Tel.: +98 21 8208 4920; fax: +98 21 8877 8690.E-mail address: afzali@ut.ac.ir (A. Afzali-Kusha).

Behzad Ebrahimi a, Ali Afzali-Kusha a,⇑, Hamid Mahmoodi b

a Nanoelectronics Center of Excellence, School of Electrical and Computer Engineering, College of Engineering, University of Tehran, Tehran, Iranb Department of Electrical and Computer Engineering, San Francisco State University, CA, USA

a r t i c l e i n f o a b s t r a c t

Article history:Received 3 October 2013Received in revised form 22 March 2014Accepted 29 April 2014Available online 24 May 2014

Keywords:SRAMDynamic back-gate designFinFETRobustLow power

In this paper, we propose a robust SRAM design which is based on FinFETs. The design is performed bydynamically adjusting the back-gate voltages of pull-up transistors. For the write operation, we use anextra write driver which sets the desired back-gate voltages during this operation. This approach consid-erably increases the write margin. During the hold state, the back-gates are precharged to the supplyvoltage using an extra precharge circuit. This decreases the static power. Finally, we use nMOS switchesto provide the optimum back-gate voltages during the read state. To minimize the area and power over-heads, an instance of the circuitry is used for each column. The performance of the proposed technique isassessed using mixed mode device/circuit simulations for a physical gate length of 22 nm. The resultsshow that the minimum operating voltage for six-sigma read and write yield is about 0.15 V lower thanthat of the recently proposed structures. In addition, the suggested SRAM shows significantly higher writemargin and lower static power compared to the recently proposed structures. The minimum operatingvoltage of our proposed structure can be lowered down to 0.5 V through some work function tuning tobalance the read and write stability. This minimum voltage is 0.1 V lower than the minimum operatingvoltage of the other structures with similar work function tunings.

� 2014 Elsevier Ltd. All rights reserved.

1. Introduction

To maximize the density, SRAM cells are realized using mini-mum sized transistors in each technology [1]. On the other hand,the shrinkage of the technology feature size to nano-scale regimehas adversely impacted the SRAM yield due to uncertainty in thedevice parameters induced by process variations. In addition, inthis regime, short channel effects more severely deteriorate theperformance of the SRAM cells. To overcome these problems,new device structures may be invoked. Among them, double gatetransistors have superior short channel characteristics and betterimmunity to process variations when compared to conventionalbulk CMOS transistors. These originate from the use of a thin sili-con film, lightly doped channel, and two gates for a better channelcontrol [2]. Among double gate transistors, FinFET structure is oneof the promising devices thanks to similarity of its fabrication pro-cess to that of the planar bulk CMOS [3]. Two gates of FinFET can betied together or used independently. The independent use of gatesoffers dynamic or static performance tunability yielding a great

flexibility for designers [4]. With a clever configuration, indepen-dent-gate structure may be used to merge series or parallel transis-tors in the logic reducing the number of transistors improvingsome of the characteristics (please see e.g., [5,6]). For example, inRef. [5], the proposed gates with independent-gate implementa-tions have lower input capacitance, number of Fins, and powerconsumption when compared to conventional tied-gate imple-mentations while achieving about the same performance. In addi-tion, recent advances in the manufacturing process permit theselective cut of the upper part of the gate allowing the implemen-tation of both independent-gate and tied-gate double gate FinFETson the same die [7]. This feature can also be utilized for the perfor-mance improvement of SRAM cells based on FinFETs. Theseimprovements include both stability and static power improve-ment. In Ref. [8], the authors proposed connecting the back-gateof access transistors to the adjacent bit-cell storage nodes. Usingthis technique, the access transistor corresponding to the nodestoring ‘‘0’’ (‘‘1’’) becomes weak (strong) during the read (write)operation and the cell stability is increased using the built-in feed-back [8]. In Ref. [9], a write wordline connected to the back-gate ofpull-up transistors was used to weaken the transistors during thewrite operation, improving the write margin. In Ref. [10], anapproach for finding the static back-gate voltages which maximize

Table 1Device parameters used for simulations.

Gate length, Lg (nm) 22Equivalent oxide thickness, toxe (Å) 11Body thickness, tsi (nm) 15Channel doping, Nbody (#/cm3) 1016

Fin height, Hfin (nm) 30Gate work function (eV) 4.6

B. Ebrahimi et al. / Microelectronics Reliability 54 (2014) 2604–2612 2605

the yield has been proposed. The fixed back-gate voltages wereobtained for read, write, and hold modes of SRAM operation.Finally, the use of back-gate voltage for the leakage reduction hasbeen proposed in Ref. [11]. It should be noted that the successfulfabrication of FinFET SRAM cells using both independent andtied-gate devices has been reported in Ref. [12].

In this work, we propose the use of back-gates of pull-up tran-sistors to enhance the stability of a SRAM cell. The voltages of theseback-gates are determined such that the read and write stabilitiesare maximized and the static power is minimized. We also proposea circuit for the dynamic biasing of the pull-up transistors. To min-imize the area overhead, the circuit for generating the dynamicvoltages is shared among all the cells in a column. The contribu-tions of this paper are as follows:

� Proposing a new dynamic back-gate biasing for improvingSRAM cell performance metrics in double gate FinFETtechnology.� Presenting a comparative analysis of the read SNM, read cur-

rent, write margin and standby power of the proposed designversus the schemes in Refs. [8,9], and demonstrating significantimprovements in write margin and standby power while main-taining competitive read SNM and read current.� Providing a comparative analysis of process variation sensitivity

of the proposed scheme versus the recently proposed schemes,proving significantly enhanced write margin yield and a com-petitive and satisfactory read SNM yield enabling us to lowerthe minimum operating voltage.

The rest of this paper is organized as follows. The FinFET struc-ture is described in Section 2. In Section 3, the SRAM design consid-erations are reviewed. Section 4 discusses the existing dynamicback-gate voltage schemes while Section 5 describes the proposeddynamic back-gate voltage technique. The results are discussed inSection 6 while Section 7 concludes the paper.

2. FinFET structure

In FinFET devices, the gates on either side of the fin can be tiedtogether or electrically isolated to allow an independent biasingscheme. This is achieved by removing the gate material in theregion directly on top of the fin [7,13]. In the tied-gate operatingmode (Fig. 1a), the two gates are biased together while in the inde-pendent-gate operating mode (Fig. 1b), they are biasedindependently.

We use a 22 nm FinFET technology with device parameters sim-ilar to those used in Ref. [9]. The parameters are listed in Table 1.The terminal contact resistances, which were included in the sim-ulations, were calculated based on the model presented in Ref.[14]. In this paper, the results were obtained using 2D SentaurusDevice Simulator [15] with the temperature T = 300 K. In the sim-ulations, the density gradient model along with high field

Fig. 1. Schematic structure of double gate FinFETs (a)

saturation for transport was used. The mobilities were calibratedusing the experimental data given in Ref. [16].

The results of the I–V characteristics obtained from these simu-lations were in good agreement with the results reported in Ref.[9]. Also, it should be noted that, in (100) wafers, for typical chan-nel orientation of (110), the difference between the electron andhole mobilities decreases compared to that of the conventionalbulk case. Thus, the midgap work function of 4.6 eV for both nFETand pFET results in comparable strengths for both nFET and pFET.Using this work function for both n- and p-type transistors withequal sizes, the threshold voltage of about 0.4 V was obtained forboth devices (results of device simulations). The strength ratio ofpFET–nFET was also obtained to be about 0.75. One also shouldnotice that the use of the high aspect ratio for the FinFETs makesusing different work functions (along the sidewalls of the fins)for n- and p-type transistors difficult [9,17]. Consequently, in thiswork, similar to [9], we assumed single gate material for both nFETand pFET (It is imperative to mention that this assumption shouldnot affect the comparative results presented in Section 6).

For the SRAM cell characteristics, we performed mixed modedevice/circuit simulations. It should be noted that in order to havea compact layout, we chose single fin devices.

3. SRAM design considerations

In this section, we describe different operational modes of theconventional 6T SRAM cell shown in Fig. 2 along with the desiredback-gate voltage of the transistors.

3.1. Read state

Consider the case that VL = ‘‘1’’ and VR = ‘‘0’’ (see Fig. 2). Duringthe read operation, bitlines are precharged to Vdd and the wordlineis set to Vdd. This operation raises VR to a value that is determinedby the voltage division between NR and AR. This voltage is denotedby Vread. If Vread becomes greater than the trip point voltage of PLand NL (Vtrip), the value of the cell flips and a destructive readoccurs. The stability in the read state is measured by the read staticnoise margin (SNM) [18].

To increase the read SNM, NR should be stronger than AR inorder to decrease Vread. Also, the leakage current of PR which isin the OFF state may increase the Vread value decreasing the read

tied-gate mode and (b) independent-gate mode.

Fig. 2. A conventional 6T SRAM cell.

Table 2Bitline voltages and desired back-gate voltages of transistors in different states fromstability (read and write) and static power (hold) perspective.

BP0 BP1 BN0 BN1 BA0 BA1 BL0 BL1

Read Vdd 0 Vdd 0 0 Vdd Vdd Vdd

Write 0 Vdd 0 Vdd Vdd Vdd Vdd 0Hold Vdd NI NI 0 0 NI Vdd Vdd

Fig. 3. Schematics of a 6T SRAM cell where the back-gates of the access transistorsare connected to the adjacent bit-cell storage nodes for providing the dynamicfeedback (ABG).

2606 B. Ebrahimi et al. / Microelectronics Reliability 54 (2014) 2604–2612

stability. To minimize the leakage, the absolute value of the thresh-old voltage of PR should be high. On the other hand, PL and ALshould be stronger than NL to increase Vtrip. Based on this discus-sion, the desired back-gate voltages of the transistors from the readstability perspective are Vdd, 0, Vdd, 0, Vdd, and 0 for NR, AR, PR, PL,AL, and NL, respectively. It is worth noting that, in addition to Vtrip

and Vread, the gain of the inverter transfer characteristics alsoimpacts the read SNM (higher gains would result in higher readSNMs) [18].

Another parameter in the read state is the access time for whichthe read current is used as a metric [9]. The read current is the cur-rent of the access transistor (AR) whose source is at Vread. From thisaspect, if NR and AR become strong and PR becomes weak, the readcurrent increases decreasing the access time [10]. While thisparameter is not included in our optimization in favor of the readstability, it will be included in our comparative study.

3.2. Write state

While writing a ‘‘1’’ into the cell that stores ‘‘0’’ (Fig. 2), the volt-age of BL is set to 0 and that of BR is set to Vdd, and the wordline isasserted. In this case, the node L is discharged through AL. If VL,which is determined by the voltage division between PL and AL,becomes lower than the trip point voltage of PR and NR, the writeoperation will be accomplished. The stability in the write state ismeasured by the write margin [19]. To increase the write margin,AL should be stronger than PL and Vtrip of PR–NR should be high.Hence, PR and AR should be stronger than NR. Also, the leakagecurrent of NL which is in the OFF state may help the discharge ofthe node L increasing the write margin. To maximize the leakage,the threshold voltage of NL should be low. Thus, the desiredback-gate voltages of the transistors from the write stability per-spective are Vdd, Vdd, Vdd, 0, Vdd, and 0 for AL, PL, NL, PR, AR, andNR, respectively.

3.3. Hold state

In most of the time, no read or write operation is performedplacing the array cells in the hold mode where the bitlines are pre-charged to Vdd and the wordline is set to 0. In this mode, the mostimportant parameter is the standby power [20]. In the case ofFig. 2, the transistors AR, PR, and NL are in the subthreshold regionsof operation, and hence, their subthreshold currents contribute tothe static power. In this state, to minimize the static power, theabsolute value of the threshold voltage of these transistors shouldbe high. Hence, the desired back-gate voltages of the transistorsfrom the static power view are 0, Vdd, and 0 for AR, PR, and NL,respectively. The back-gate voltages of other transistors are notimportant.

To summarize our discussion, in Table 2, the bitline voltagesand the desired back-gate voltage for different transistors in theSRAM cell of Fig. 2 are listed. In this table, BPX, BNX and BAX areused to resemble the back-gate voltages of the pull-up (P),

pull-down (N), and access (A) transistors, respectively, in the sidestoring the logic X which can be ‘‘0’’ or ‘‘1’’. Also, BLX denotes thebitline voltage near the node storing the logic X. NI stands fornot important.

4. Existing dynamic back-gate voltage techniques

The FinFET device has a superior short channel control com-pared to the planar bulk transistor. However, to have acceptableread and write stabilities in the SRAM cells implemented usingthese devices, the number of fins of the transistors should beincreased (e.g., increasing the fin numbers of pull-down (access)for increasing read (write) stability [9]). Another approach forincreasing the stabilities is to use the back-gate of transistors [8–11]. Using the back-gate, one also can lower the static power. Thisapproach has been invoked in Refs. [8,9] where the back-gate ofthe access transistors are connected to the adjacent bit-cell storagenodes as shown in Fig. 3. This scheme is referred to as ABG struc-ture here. For the ABG SRAM cell, the read SNM increases com-pared to the structure which is only composed of tied-gateFinFETs, referred to as DG structure here. In the ABG cell, however,the read current degrades owing to the zero back-gate bias of thedischarging access transistor. In the ABG cell, the desired back-gatevoltages for the read stability and static power (see Table 2) areapplied to the back-gates of all six transistors of the SRAM cell.

It has been shown that the read SNMs of the ABG and DG SRAMcells may become equal if the work functions of the gates in the DGstructure are increased compared to those in the ABG structure [9].In this case, the write margin also improves in the ABG cell as com-pared to that of the DG structure especially at low Vdd’s due to thestronger access transistor [9]. For the area comparison, the layoutsfor the structures are shown in Fig. 4 where we used the designrules for the FinFET technology reported in Ref. [21]. Similar to[9], we assumed the SOI FinFET technology where n-well to p-wellspacing rules can be avoided and the nFET and pFET drains can bedirectly connected. Compared to increasing the number of fins, theapproach connecting the back-gate of access transistors to theadjacent bit-cell storage nodes has the advantage of not increasingthe area [9,22]. This is also evident from Fig. 4b and c where thereis no extra contact for the back-gate. More specifically, there is onecontact for the back-gate of the access transistor and the gates ofthe pull-down and pull-up transistors.

Fig. 4. Layout for 6T SRAM cells (a) DG, (b) ABG with tied-gate pull-up and (c) ABG with independent-gate pull-up.

B. Ebrahimi et al. / Microelectronics Reliability 54 (2014) 2604–2612 2607

The authors in Ref. [9] suggested connecting the back-gate ofpull-up transistors to a Write Wordline (WWL). In this method,whose layout is shown in Fig. 4c, the area increases by about12.5% compared to that of the ABG structure with tied-gate pull-up due to the additional contact space required for WWL [22]. Thisline was assumed to route horizontally in a different metal layerthan that of the WL [9]. The WWL has been suggested to be setto Vdd during the write state and 0 or an intermediate value duringthe read and hold states [9]. One of the problems with thisapproach, as implied from Table 2, is that same back-gate voltagebias is used for both BP0 and BP1 in read and hold states. AssumingNI can be 0, the desired back-gate voltages are Vdd for BP0 and 0 forBP1. Therefore, to have one fixed value for both pull-up transistorsin both the operation modes, we should choose a compromisingvalue. In Ref. [9], the authors suggested 0.48 V for a technologyof 22 nm gate length when the supply voltage varied from 0.4 Vto 1.2 V. Moreover, the approach in Ref. [9] sets the back-gate biasof both pull-up transistors to Vdd during the write mode irrespec-tive of the data being written to the cell, whereas based on theresults presented in Table 2, it is most optimal for write marginenhancement to set the back-gate of the pull-up on the node stor-ing logic ‘‘0’’ (BP0) at zero bias and that of the pull-up on the nodestoring logic ‘‘1’’ (BP1) at Vdd. Additionally, the implementation ofthis approach requires some circuitry (which has some overhead)for the generation and distribution of the fixed voltage along withsetting the WWL to Vdd during the write and 0.48 V during the readand hold states.

5. Proposed dynamic back-gate voltage technique

In this work, we suggest a technique in which the back-gatevoltages of the pull-up transistors are dynamically adjusted. Thevalues of the voltages are set based on the desired values of eachstate. Table 2 suggests that, in the hold state, the back-gate voltageof the pull-up transistor whose drain stores logic ‘‘0’’ should be Vdd

and the back-gate voltage of the other pull-up transistor is notimportant. Hence, in our design the back-gates are precharged toVdd (as is done for the bitlines) to have the highest threshold

voltage for the pull-up transistors. In the write state, the pull-uptransistor whose drain stores logic ‘‘1’’, should be weak, and hence,its back-gate voltage should be set to Vdd. In this case, the otherpull-up transistor should be strong to have a high Vtrip, and hence,its back-gate voltage should be set to 0. The bias, however, turns onthe OFF state pull-up with the back-gate during the write opera-tion increasing the power consumption. First, note that, the useof the midgap work function metals for the gates yields highthreshold voltage transistors with rather small ON current (highresistance). Second, turning on the pull-up helps the write opera-tion reducing its required operation time. Thus, the time that weare required to apply this bias is reduced. Table 2 also suggestsin the read state, the pull-up transistor whose drain stores logic‘‘1’’ should have the back-gate voltage of 0. The back-gate voltageof the other pull-up transistor should be Vdd. These values are com-plement of the desired values for the write operation. Hence, wecannot fix the connection of the back-gates of the pull-up transis-tors to the corresponding storage nodes to avoid detrimental deg-radation of the write stability. Since the stored value is not knowna priori, we need to choose a fixed value for the back-gate voltagesof the pull-up transistors regardless of the stored value. In thiswork, we propose to set the value based on maximizing the readSNM.

We also leave pull-down transistors in the tied-gate mode,because it is the favorable mode from read stability and staticpower perspective as shown in Table 2. Also, write margin sensitiv-ity to pull-down threshold voltage is much smaller compared tothose of access and pull-up transistors [19]. The back-gates ofthe access transistors are also connected to the adjacent storagenodes (similar to the other ABG structures). This is the favorablecase from read stability and static power perspectives as shownin Table 2.

To set the desired back-gate voltages of the pull-up transistorsbased on the operation state of the SRAM cell, we propose the cir-cuit diagram for the SRAM array which is shown in Fig. 5. In theproposed scheme, the pull-up back-gate biases are data dependentand set based on the input data to be written to the cell using anadded write driver circuitry as shown in Fig. 5. In this case, propervalues of the bitlines and pull-up back-gate voltages should be set

Fig. 5. The proposed array design for dynamically biasing the back-gate of pull-uptransistors.

Fig. 6. Nominal write margin (CWLM) versus Vdd for different SRAM structures.

2608 B. Ebrahimi et al. / Microelectronics Reliability 54 (2014) 2604–2612

before the wordline is activated, while in the case of the conven-tional SRAM cell, the setting of the voltages are performed onlyfor the bitlines. Since the interconnect used for the back-gate volt-age has the same length (interconnect dominant capacitance [22])as that of the bitline, the setting of the voltages should be per-formed at about the same time. Sharing the added circuitry amongthe cells of each column makes its area and power overhead neg-ligible. The extra write driver typically induces a very small areapenalty [23] (about 0.5% for an array of 128 cells per column[24]). The hold state biasing of the back-gates, which lowers thestandby power as well, is performed by an extra precharge circuit,as shown in Fig. 5. As a rule of thumb, the area overhead of theextra precharge circuit should be much less than that of the writedriver circuit [25]. An optimum pre-generated back-gate voltagebias (Vopt) for the read state is applied to the back-gate lines viaa pair of nMOS switches (Fig. 5). These nMOS sizes are determinedto achieve the required voltage swing on the back-gate lines fromthe precharged value of Vdd set during the hold state (initial state)to the optimum value (Vopt) required for the read operation, withinthe read cycle. Therefore, these nMOS switches are expected tooccupy less area than that of the extra write driver due to the lowervoltage swing required on the back-gate lines and the longer timeavailable for this voltage swing to be completed. The optimumback-gate voltage bias (Vopt) can also be generated by a low Vdd

voltage reference (e.g., [26,27]). As the voltage reference is sharedfor the whole chip, its area and power penalty is negligible [26,27].

It should be noted that the layout of the proposed SRAM cellremains similar to Fig. 4c. The difference is that the pull-up back-gate lines are assumed to route vertically (on contrary to horizon-tally in the approach of [9]) in a different metal layer than that ofthe bitlines to eliminate the cross talk noise to the parallel bitlines.

It should be noted that SRAM stability and performance couldalso be improved using other means such as 6T SRAM cells withtwo-fin pull-down or 8T cell structures. Our design, however,would outperform these structures. In the case of the former cell,using sizing to improve the read stability worsens the write stabil-ity and vice versa (see e.g., [9]). For example, the two-fin pull-downapproach increasing the area by 16.6% [9] improves the read stabil-ity while deteriorates the write stability by about the same amount(see Fig. 6 in Ref. [9]), and hence, may not be a good choice forimproving both of the read and write stabilities especially at lowersupply voltages where the write stability is degraded more. Inaddition, it increases the power. On the other hand, increasingthe number of transistors, as is the case for the latter cell structure,increases the area considerably. For example, the 8T SRAM cell has30% more area compared to the former structure [28]. The areapenalty of our design is about one third of that of the 8T SRAM cell.

6. Results and discussion

In this part, we study the efficacy of the proposed scheme bycomparing its performance with those of the DG structure, theABG structure proposed in Ref. [8] where the independent-gatemode is used only for the access transistors, the ABG structure withback-gate voltage of 0 and Vdd for the pull-up transistors during theread/hold and write states, respectively [9], and the ABG structurewith back-gate voltage of 0.48 V and Vdd for the pull-up transistorsduring the read/hold and write states, respectively [9]. In the caseof the DG structure, to increase the read stability, we increase thegate work function to 4.75 eV. By increasing the gate work functionfurther, the read stability decreases instead of increasing due to thesevere subthreshold leakage current increase of the pMOS pull-upas discussed in Section 3. Next, we present the static characteristicsof one SRAM cell in each structure with the corresponding back-gate bias conditions.

6.1. Nominal study

First, we consider the write stability metric (write margin) forwhich different definitions have been suggested in the literature[19]. In this work, we use the difference between Vdd and the min-imum wordline voltage, namely, combined wordline margin(CWLM), that can cause a successful write operation as a metric[19]. It has been shown that this metric has a Gaussian distributionin the presence of process variations [19,29]. The write margin ofdifferent structures versus the supply voltage is depicted inFig. 6. The results reveal that our proposed structure has the high-est write margin among different structures even more than theABG structure, in which the back-gate of the pull-up transistorsare connected to Vdd. It should be noticed out the proposed struc-ture has an acceptable write margin even for Vdd’s as low as 0.5 V

Fig. 8. Nominal read SNM versus Vdd for different SRAM structures.

B. Ebrahimi et al. / Microelectronics Reliability 54 (2014) 2604–2612 2609

while the area is compact due to using FinFETs with one fin. Addi-tionally, to avoid the half-selected issue for the cells in the selectedrow, it has been suggested that the whole row is simultaneouslywritten [30]. Using this approach, in this work, we assume 8 cells(one byte) in each row for each SRAM sub-block [31]. On the otherhand, the half-selected cells in the same column as that of the cellbeing written have their wordlines deactivated. Hence, during theshort time of the write operation, the storage node voltages of thehalf-selected cells do not change considerably yielding high half-selected cell stability.

As discussed in Section 3.3, the static power is the most impor-tant metric in the hold state. In Fig. 7, we compare the static pow-ers of the structures. The results demonstrate that the DG structurehas about one order of magnitude higher static power than that ofthe ABG structure with tied-gate mode pull-up. This may be justi-fied by noting that, due to the higher gate work function in the DGstructure, the pull-up transistor has higher subthreshold leakagecurrent. In the case of the independent-gate mode pull-up, if theback-gate voltages of the pull-up transistors are set to 0, the sub-threshold leakage current will become unacceptably high. On theother hand, if the compromising value which considers the readstability and static power is used for the back-gates of the pull-up transistors, the subthreshold leakage will increase considerablyat high supply voltages. The results indicate that our proposedstructure and ABG structure with tied-gate pull-up transistors havethe least static power. The reason for the lower static power forthese structures is that the back-gate voltage of the OFF statepull-up transistor is Vdd resulting in a higher absolute value forthe threshold voltage.

In Fig. 8, we have plotted the nominal (without considering pro-cess variation impacts) read SNM versus the supply voltage for allthe structures. As evident from the figure, for the supply voltageslarger than 0.6 V, the ABG structure [8] has a higher read SNM thanthat of the DG structure in spite of increasing the gate work func-tion for the DG structure. Using the independent-gate mode oper-ation for the pull-up transistors decreases the read SNM. This maybe attributed to the smaller transconductance of independent-gateFinFET compared to that of the tied-gate one [4]. The smaller trans-conductance leads to a smaller gain for the inverter determiningthe transfer characteristic and consequently the read SNMbecomes smaller [18]. If the back-gate of the pull-up transistorsis connected to the ground, the read SNM decreases due to theincrease in the subthreshold leakage current of the pull-up transis-tors, especially at higher supply voltages. The back-gate of the pull-up transistors may be connected to an intermediate fixed voltage.As an example, this value was set to 0.48 V in Ref. [9]. In this case,however, the read SNM decreases due to the smaller transconduc-tance of the independent-gate pull-up transistors and alsodecrease in the value of Vtrip owing to weak pull-up at lower supplyvoltages. In the case of our proposed design, the back-gate voltagesfor the read and hold states can be different. Using the proposed

Fig. 7. Nominal static power versus Vdd for different SRAM structures.

circuit shown in Fig. 5, we can choose an optimum back-gate volt-age based on the supply voltage for the read state. We used simu-lations to find the optimum values for the maximum read SNM bysweeping the back-gate voltage between 0 and Vdd for each supplyvoltage. The optimum values considering the read stability arelisted in the inset of Fig. 8. Due to the process variations, the opti-mum value for a given Vdd may vary. To study the sensitivity of theread SNM to the optimum value, we changed the optimum valuesfor all the supply voltages studied in this work by 20% and mea-sured the read SNM. The results showed at most 2.5% change inthe value of the SNM. Hence, the preciseness of the voltage gener-ator is not of a critical concern. The results indicate that the readstability of our design is higher than those of the ABG structureswith fixed pull-up back-gate voltages of 0 and 0.48 V for the supplyvoltages between 0.4 V and 0.9 V while lower than those of the DGand ABG structures for the supply voltages between 0.7 V and0.9 V. The lower read stability may be attributed to the less trans-conductance of the independent-gate pull-up transistor withrespect to the tied-gate one which causes better stability for theDG and ABG structures at high supply voltages. In addition, theread SNM of the proposed technique, similar to that of the ABG[8], is the highest for the supply voltages from 0.4 V to 0.6 V.

The read currents for different structures are compared in Fig. 9.As is evident from the figure, the read currents of the ABG struc-tures (including our proposed structure) are more than that ofDG structure for lower Vdd’s. This may be attributed to the fact thatthe lower gate work function effect (lower threshold voltage) dom-inates the zero back-gate bias of the access transistor (higherthreshold voltage) in the case of the ABG structures. At higher sup-ply voltages, the read current of the ABG structure, in which theback-gates of the pull-up transistors are connected to ground,decreases because the subthreshold leakage of the OFF state pull-up transistor increases. This raises the value of Vread (the sourcevoltage of the access transistor) leading to a lower overdrive volt-age for the (discharging) access transistor, and hence, a smallerread current. At the highest supply voltage (Vdd = 0.9 V), the read

Fig. 9. Nominal read current versus Vdd for different SRAM structures.

Fig. 10. (a) Read SNM and (b) CWLM cell sigma yield versus the supply voltage fordifferent SRAM cell structures.

2610 B. Ebrahimi et al. / Microelectronics Reliability 54 (2014) 2604–2612

currents of the ABG structures are lower than that of the DG struc-ture because the zero back-gate bias dominates the lower gatework function. This implies that the use of the independent-gatestructure only slightly lowers the read speed for the highest Vdd.It should be noted that the midgap work function values used inthis work are more appropriate for low power applications. Forexample, the read current values are very close to those of a SRAMarray fabricated using a 28 nm low power SOC process [32].

6.2. Study of process variation effect

Now, we study the impact of the process variation on the SRAMcell structures discussed in this work. In addition to channel lengthand silicon thickness variations due to the line-edge roughness,there are other sources of variations including random dopant fluc-tuations as well as work function, fin height, and oxide thicknessvariations. As the experimental results presented in e.g., [33,34]show, the random dopant fluctuation can be ignored due to the factthat the body is lightly doped. Also, the work function variation canbe suppressed by using gate-last process where amorphous metalgate are deposited after the high-temperature annealing and acti-vation process steps [35]. On the other hand, since the real valuesof fin height and oxide thickness are not determined by the lithog-raphy resolution, their variations should not be critical (please seee.g., [33]). The actual values of the channel length and silicon thick-ness are dictated by the lithography resolution and hence theirvariations are of key concern (see e.g., [9,10,33]). It should be men-tioned that including other variation sources may be readily per-formed by extending the analysis given below. For this study, weassume that the channel length and silicon thickness have the vari-ations such that the standard variations, namely, rtsi and rLg,respectively, are 7% Lg [9]. The variation of read SNM and CWLMmay be very well modeled by a normal distribution [19,29]. There-fore, we assume that these metrics have Gaussian distributionswhich are functions of twelve random variables. Denoting the met-ric by y, we may write

y ¼ f ðx1; . . . ; x12Þ; ð1Þ

where x1,. . ., x12 are the Gaussian random variables with the aver-ages of g1, . . ., g12 and standard deviations of r1,. . ., r12. Thesetwelve random variables are channel lengths and silicon thick-nesses of six transistors of the SRAM cell. Hence, we can use the fol-lowing expression to find their statistical characteristics usingbivarient Taylor Series as [36]:

ly ¼ f g1; . . . ; g12ð Þ ð2Þ

r2y ¼

X12

i¼1

@f@xi

����gi

!2

r2i ð3Þ

Here, we used the cell sigma, the yield figure of merit of the SRAM,which is defined as the minimum amount of variation needed tocause a read or write failure. The cell sigma is given by the mean(l) divided by the standard deviation (r) [9]. Nowadays, six-sigma(6r) yield or larger is required for large SRAM arrays [9].

In Fig. 10, we have plotted the read SNM and CWLM cell sigmayields versus the supply voltage obtained from simulations andusing Eqs. (2) and (3). It should be noted that ly’s in Eq. (2) wereapproximated by their nominal values which were presented inFigs. 6 and 8. Also, since the variations of the read SNM and CWLMwere linearly proportional to the variations of the random vari-ables (xi) [19,29], the derivatives in (3), of/oxi, were easily foundby using the metric values through the simulations at some valuesof xi near the nominal values (gi). As is evident from the figure, ourproposed structure and the ABG structure with pull-up back-gatevoltages equal to 0 have over six-sigma read yield for supply

voltages as low as 0.5 V. This is due to the high nominal readSNM and less sensitivity to device parameters especially at lowsupply voltages. As expected the write yield degrades considerablyfor low supply voltages. Among these structures, only our pro-posed structure has over six-sigma write yield down to Vdd equalto 0.55 V (0.15 V below the minimum of the other structures).For our structure, at Vdd = 0.5 V, the write margin cell sigma isslightly lower than six. To have six-sigma write yield, one maylower gate work function of the transistors to 4.57 eV to increasethe writability. This work function tuning makes the access (aswell as pull-down) nMOS stronger while making the pull-up pMOSweaker. These strength changes improves the write yield such thatboth the read and write cell sigma yields become above six. In thiscase, the read current increases by 56% while the static power alsoincreases by 47% compared to the case of no work function tuning.The static power is still 23% lower than that of the structure (with-out work function tuning) when the supply voltage of 0.6 V is used.Therefore, if a proper work function tuning can be performed, onemay use Vdd = 0.5 V to lower the static power (as well as thedynamic power due to a lower supply voltage). With similar workfunction tuning, we used the gate work function of 4.61 eV,4.54 eV, 4.49 eV, and 4.61 eV for the DG, ABG, ABG with pull-upback-gate voltage of 0 during the read/hold states, and ABG withpull-up back-gate voltage of 0.48 V during the read/hold states,respectively. This resulted in the minimum operating voltage of0.65, 0.65, 0.6, and 0.7 V, respectively. These numbers suggest thatthe proposed structure still could operate with the supply voltagewhich is 0.1 V lower than that of the other structures. Next, weconsider the SNM cell sigma yield for the half-selected cells inthe same column of the selected cell shown in Fig. 11. For the readoperation (Fig. 11b), the yields for all the structures are very high.In the case of the write operation, while the half-selected disturb isthe worst for our proposed structure, it is still higher than six. Itshould be noted that as the wordlines of half-selected cells areinactive, the storage node voltages of the half-selected cells donot have enough time for changing their values for threatening

Fig. 11. Half-selected SNM cell sigma during (a) write and (b) read versus thesupply voltage for different SRAM cell structures.

B. Ebrahimi et al. / Microelectronics Reliability 54 (2014) 2604–2612 2611

the reliability (SNM, which is a static parameter, is a pessimisticmetric) (see e.g., [37]).

6.3. Dynamic energy consumption

In this part, we study the energy consumptions of the structuresper read and write operations. In the structures considered in thiswork, the main sources of the dynamic power consumption are thevoltage changes of the long wordline, bitlines, and pull-up back-gate lines. The increased static currents of the cells during the readand write operations (including those induced due to the applica-tion of the back-gate biases) can be neglected as the cells are in thehold state most of the time while the read and write times are veryshort. To perform this study, we assumed a SRAM block with 8 cellsin each row [31] and 128 cells in each column [24] and the linecapacitance was taken as 0.25 fF/lm to account for the dominantinterconnect capacitance as well as the drain/gate contact capaci-tance [22]. Hence, we included the additional parasitic capaci-tances for the pull-up back-gate lines as well as the bitlines. Theresults for the energy consumptions of all the structures versus

Fig. 12. (a) Write energy for one byte (solid lines) and read energy (dotted lines)versus Vdd for different SRAM structures.

the supply voltage are plotted in Fig. 12. As is observed from theresults the proposed structure consumes more dynamic energycompared to those of the other structures. This is due to the morevoltage switchings of the lines connected to the back-gates of thepull-up transistors. Since the main contributor to the total powerof SRAM is the static power [20,33], the larger dynamic energyfor the proposed structure may not be considered as major short-coming. It should be noticed that since our structure could operateat lower minimum supply voltages, the dynamic power may belowered by lowering the supply voltage wherever the correspond-ing speed reduction can be tolerated. The supply voltage reductionalso lowers the static power.

7. Conclusions

We proposed a dynamic back-gate design for the pull-up tran-sistors of SRAM cells to increase the cell stability during the readand write states while decreasing the static power during holdstate. The optimization was performed by dynamically adjustingthe voltages of the back-gates of the pull-up transistors in the cell.The voltages were determined in order to have maximum stabilityduring the read and write states and minimum static power duringthe hold state. During the write operation, we used an extra writedriver which sets the desired back-gate voltage of pull-up transis-tors to considerably increase the write margin. During the holdstate, to decrease the static power, the back-gates were prechargedto the supply voltage using an extra precharge circuit. The read sta-bility degradation was prevented using proper back-gate voltagesgenerated using nMOS switches. To reduce the area and poweroverheads, the added circuitry was shared for each column. Also,the proposed structure had the highest write margin among thestructures considered in this work. The half-selected issue for thecells in the selected row has been avoided by writing the wholerow simultaneously. The half-selected cells in the same columnof the selected cell had high stability during read and write opera-tions. Therefore, the proposed cell may be used for the applicationswhere writing the whole row simultaneously is possible. For thecell with single fin FinFETs, the minimum operating voltage forsix-sigma yield obtained to be about 0.55 V which was 0.15 Vlower than that of a recently proposed structure. In addition, ourstructure had much less static power. The minimum operatingvoltage of the proposed structure could be lowered to 0.5 V bysome work function tuning while the minimum operating voltagefor all other structure was 0.6 V or higher using similar work func-tion tunings.

Acknowledgement

The first two authors acknowledge the financial support by theIranian National Science Foundation (INSF).

References

[1] Agarwal K, Nassif S. The impact of random device variation on SRAM cellstability in sub-90-nm CMOS technologies. IEEE Trans Very Large Scale Integr(VLSI) Syst 2008;16(1):86–97.

[2] Neudeck GW. An overview of double-gate MOSFETs. Proc BGIM 2003:214–7.[3] Tang SH, et al. FinFET-a quasiplanar double-gate MOSFET. In: Proc ISSCC Dig.

Techn. Papers; 2001. p. 118–9.[4] Datta A et al. Modeling and circuit synthesis for independently controlled

double gate FinFET devices. IEEE Trans Comput-Aided Des Integr Circuits Syst2007;26(11):1957–66.

[5] Rostami M, Mohanram K. Dual-Vth independent-gate FinFETs for low powerlogic circuits. IEEE Trans Comput-Aided Des 2011;30(3):337–49.

[6] Tawfik SA, Kursun V. Low-power and compact sequential circuits withindependent-gate FinFETs. IEEE Trans Electron Dev 2008;55(1):60–70.

[7] Liu YX et al. Cointegration of high-performance tied-gate three-terminalFinFETs and variable threshold-voltage independent-gate four-terminal

2612 B. Ebrahimi et al. / Microelectronics Reliability 54 (2014) 2604–2612

FinFETs with asymmetric gate-oxide thicknesses. IEEE Electron Dev Lett2007;28(6):517–9.

[8] Yamaoka M et al. Low power SRAM menu for SOC application using Yin-Yang-feedback memory cell technology. Proc Symp VLSI Circuit Dig 2004:288–91.

[9] Carlson A et al. SRAM read/write margin enhancements using FinFETs. IEEETrans Very Large Scale Integr (VLSI) Syst 2010;18(6):887–900.

[10] Ebrahimi B, Rostami M, Afzali-Kusha A, Pedram M. Statistical designoptimization of FinFET SRAM using back-gate voltage. IEEE Trans Very LargeScale Integr (VLSI) Syst 2011;19(10):1911–6.

[11] Endo K et al. Independent-double-gate FinFET SRAM for leakage currentreduction. IEEE Electron Device Lett 2009;30(7):757–9.

[12] Endo K et al. Enhancing SRAM performance by advanced FinFET device andcircuit technology collaboration for 14 nm node and beyond. Proc Symp VLSITechnol 2013:T214–5.

[13] Mathew L et al. CMOS vertical multiple independent gate field effect transistor(MIGFET). IEEE SOI Conf Dig 2004:187.

[14] Tekleab D, Samavedam S, Zeitzoff P. Modeling and analysis of parasiticresistance in double-gate FinFETs. IEEE Trans Electron Dev2009;56(10):2291–6.

[15] Synopsys Inc., Mountain View, CA. Sentaurus Device Simulator, Version Z-2007.3. 2007.

[16] Chowdhury M, Trivedi VP, Fossum JG, Mathew L. Carrier mobility/transport inundoped-UTB DG FinFETs. IEEE Trans Electron Dev 2007;54(5):1125–31.

[17] Muralidhar R, Cai J, Frank DJ, Oldiges P, Lu D, Lauer I. Meeting the challenge ofmultiple threshold voltages in highly scaled undoped FinFETs. IEEE TransElectron Dev 2013;60(3):1276–8.

[18] Seevinck E, List R, Lohstroh J. Staic-noise margin analysis of MOS SRAM cells.IEEE JSSC 1987;SC-22:748–54.

[19] Makino H et al. Re-examination of SRAM cell write margin definitions in viewof predicting distribution. Trans Circuits Syst II: Brief Express2011;58(4):230–4.

[20] Kim CH, Kim JJ, Mukhopadhyay S, Roy K. A forward body-biased-low-leakageSRAM cache: device and architecture considerations. Proc Int Symp Low PowerElectron Des; 2003. p. 6–9.

[21] Salahuddin S, Jiao H, Kursun V. A novel 6T SRAM cell with asymmetrically gateunderlap engineered FinFETs for enhanced read data stability and write ability.Proc ISQED 2013:353–8.

[22] Kang M et al. Asymmetric independent-gate MOSFET SRAM for high stability.IEEE Trans Electron Dev 2011;58(9):2959–65.

[23] Ney A et al. A design-for-diagnosis technique for SRAM write drivers. Proc Date2008:1480–5.

[24] Chang MF, Chen YC, Chen CF. A 0.45-V 300-MHz 10T flow through SRAM withexpanded write/read stability and speed-area-wise array for sub-0.5-V chips.IEEE Trans Circuits Syst II, Exp Briefs 2010;57(12):980–5.

[25] Cheng SP, Huang SY. A low-power SRAM for Viterbi decoder in wirelesscommunication. IEEE Trans Consum Electron 2008;54(2):290–5.

[26] Jing X et al. A 0.5 V nanoWatt CMOS voltage reference with two high PSRRoutputs. Proc IEEE Int Symp Circuits Syst 2012:2837–40.

[27] Annema A et al. A sub-1V bandgap voltage reference in 32 nm FinFETtechnology. Proc IEEE Int Solid-State Circuits Conf Dig Tech Pap 2009:332–3.

[28] Chang L et al. Stable SRAM cell design for the 32 nm node and beyond.Symp.VLSI Technol Dig Tech Pap 2005:128–9.

[29] Wang J, Calhoun BH. Minimum supply voltage and yield estimation for largeSRAMs under parametric variations. IEEE Trans Very Large Scale Integr (VLSI)Syst 2011;19(11):2120–5.

[30] Chun KC, Jain P, Lee JH, Kim CH. A 3T gain cell embedded DRAM utilizingpreferential boosting for high density and low power ondie caches. IEEE JSolid-State Circuits 2011;46(6):1495–505.

[31] Chang IJ, Kim J, Park SP, Roy K. A 32 kb 10T subthreshold SRAM array with bit-interleaving and differential read scheme in 90 nm CMOS. Proc IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Pap 2008:388–9.

[32] Wang J et al. Non-Gaussian distribution of SRAM read current and designimpact to low power memory using voltage acceleration method. Symp VLSITechnol (VLSIT) 2011:220–1.

[33] Lu D, Niknejad A, Hu C, Lin C. Compact modeling in variations of finFET sramcells. Des Test Comput 2010;27(2):45–50.

[34] Endo K et al. Variability analysis of TiN metal-gate FinFETs. IEEE Electron DevLett 2010;31(6):546–8.

[35] Matsukawa T et al. Suppressing Vt and Gm variability of FinFETs usingamorphous metal gates for 14 nm and beyond. Proc IEEE IEDM 2012:8.2.1–4.

[36] A. Papoulis Probability, random variables and stochastic process. New York:McGraw-Hill; 2002.

[37] Lee ZC, Ho KM, Kong ZH, Kim TT. NBTI/PBTI-aware wordline voltage controlwith no boosted supply for stability improvement of half-selected SRAM cells.Proc IEEE Int Soc Des Conf 2012:200–3.