Robust

Low

Power

VLSI

Combined SRAM Read/Write Assist Techniques for Near/Sub-Threshold Voltage Operation

Farah B. Yahya,

Harsh N. Patel, Vikas Chandra, Benton H. Calhoun

1

Internet of Things

2 Image by Alicia Klinefelter

Internet of Things

Source: A. Klinefelter, ISSCC 2015

3

IoT specific SoCs harvest energy and operate in sub-threshold to reduce energy/power consumption

Accelerators

4-Channel,

16-tap FIR

16-pt,

Complex

FFT

CORDIC

4-Channel

AFE

8-bit SAR

ADC

WuRx

4kB DMEM

2kB Tx

Buffer

Multiplier/

MAC

Histogram

(1-3)

Heart rate

(R-R) and

AFIB

ADPLL

Tx

FSM

DC-DC

Converter

Power Management

Radios

Sensing

Timer (1)

Clocking

Var. Voltage

SPI Pads

(0.4-3.3V)

TEG

Solar

SPI

(master)

MSP430

LCU

2kB LCU

Instr Mem

2kB MSP

Instr Mem

Bus

Abitration

64B SPI

FIFO

DMA

Clk/Pwr.

Gate Ctrl

Bus Controllers

SYS. INTERRUPT

4GHz

400MHz –

2.4GHz

31.25kHz

Timer (2)

Boost

Converter w/

MPPT

UWBTx

XO

SYS. CLK

SYS. VDD

DPM

CTRLR

CTRLR

CTRLR

Internet of Things

Source: A. Klinefelter, ISSCC 2015

4

Memory consumes a significant portion of the digital power.

SRAM Challenges

Large impact of variations in subthreshold causes read and write failures.

5

SRAM Challenges

Half selected cells also experience disturb during a read/write operation which might corrupt their data

6

SRAM Challenges

Static margins are used as metrics Performance is not a constraint for most IoT SoCs.

For high performance platforms, we are assuming DVFS .

Two technologies were studied: Commercial 130nm and sub-20nm FinFET. High-VT devices were used in the 130nm bit-cell.

Monte-Carlo simulations at the worst case corner for each operation was performed.

7

SRAM Challenges

8

For 130nm bit-cell, write cannot be guaranteed below 0.8V and half select disturbs will occur below 0.8V

400 500 600 700 8000

50

100

150

200

250

VDD (mV)

Ma

rgin

s(a) 130nm CMOS

300 400 500 600 700 8000

50

100

150

200

250

VDD (mV)M

arg

ins

(b) FinFET

WM Write-HSNM Read-HSNM RSNM

HS VMIN

= 0.4V

HS VMIN

= 0.7V

Write VMIN

= 0.5V

Write VMIN

> 0.8V

SRAM Challenges

9

For FinFET bit-cell, write cannot be guaranteed below 0.5V and half select disturbs will occur below 0.4V

400 500 600 700 8000

50

100

150

200

250

VDD (mV)

Ma

rgin

s(a) 130nm CMOS

300 400 500 600 700 8000

50

100

150

200

250

VDD (mV)M

arg

ins

(b) FinFET

WM Write-HSNM Read-HSNM RSNM

HS VMIN

= 0.4V

HS VMIN

= 0.7V

Write VMIN

= 0.5V

Write VMIN

> 0.8V

SRAM Challenges

10

Applying a write assist technique improves the write VMIN but not the HS VMIN

400 500 600 700 8000

50

100

150

200

250

VDD (mV)

Ma

rgin

s(a) 130nm CMOS

300 400 500 600 700 8000

50

100

150

200

250

VDD (mV)M

arg

ins

(b) FinFET

WM Write-HSNM Read-HSNM RSNM

HS VMIN

= 0.4V

HS VMIN

= 0.7V

Write VMIN

= 0.5V

Write VMIN

> 0.8V

Current Approaches

Using higher VDD for SRAMs,

Using alternative bit-cell topologies,

Using a read-before-write approach,

Implementing banks with one word per row,

Simultaneously applying a read assist technique with a write assist technique.

11

This talk…

Write Assist Techniques

Read Assist Techniques

Combined Read/Write

12

Write Assist Techniques

Assist techniques: WL boosting (BWL), NegBL, and Lowering Column VDD (LCVDD)

Assist was applied as a percentage of the VDD.

Impact on the Write Margin across VDD.

Impact on the Half Select Margins across VDD.

13

Write Assist - WM

For the 130nm bit-cell, high percentages of assist are needed to lower the write VMIN down to 0.4V

14

300 400 500 600 700 8000

50

100

150

200

250

VDD (mV)

WM

(a) 130nm CMOS

300 400 500 600 700 800

20

40

60

80

100

120

140

160

180

VDD (mV)W

M

(b) FinFET

NegBL BWL LCVDD

10%

20%

30%

40%

10%

Write V

MIN =0.35VWrite

VMIN

=0.4V

Write Assist - WM

BWL provides the highest improvement in write margin at VDD > 550mV

15

300 400 500 600 700 8000

50

100

150

200

250

VDD (mV)

WM

(a) 130nm CMOS

300 400 500 600 700 800

20

40

60

80

100

120

140

160

180

VDD (mV)W

M

(b) FinFET

NegBL BWL LCVDD

10%

20%

30%

40%

10%

Write V

MIN =0.35VWrite

VMIN

=0.4V

Write Assist - WM

LCVDD provides the highest improvement in write margin at VDD < 550mV

16

300 400 500 600 700 8000

50

100

150

200

250

VDD (mV)

WM

(a) 130nm CMOS

300 400 500 600 700 800

20

40

60

80

100

120

140

160

180

VDD (mV)W

M

(b) FinFET

NegBL BWL LCVDD

10%

20%

30%

40%

10%

Write V

MIN =0.35VWrite

VMIN

=0.4V

Write Assist - WM

The FinFET bitcell exhibits similar behavior but only 10% of assist is needed to reduce the write VMIN to 0.35V

17

300 400 500 600 700 8000

50

100

150

200

250

VDD (mV)

WM

(a) 130nm CMOS

300 400 500 600 700 800

20

40

60

80

100

120

140

160

180

VDD (mV)W

M

(b) FinFET

NegBL BWL LCVDD

10%

20%

30%

40%

10%

Write V

MIN =0.35VWrite

VMIN

=0.4V

Write Assist - SNM

For 130nm bitcell, row HS VMIN is raised by BWL from 700mV to above 800mV.

20

300 400 500 600 700 8000

50

100

150

200

250

VDD (mV)

SN

M

(a) 130nm CMOS

300 400 500 600 700 800

50

100

150

200

250

VDD (mV)

SN

M

(b) FinFET

HSNM HSNM-NegBL HSNM-LCVDD RSNM RSNM-BWL

40%LCV

DD & NegBL

significantly degradeCol. HS V

MIN

BWL raises Row HS V

MIN >0.8V

10%LCV

DD & NegBL

reduce HSNM

BWL raises Row HS V

MIN

Write Assist - SNM

For FinFET, BWL increases the row HS VMIN to 0.55V

21

300 400 500 600 700 8000

50

100

150

200

250

VDD (mV)

SN

M

(a) 130nm CMOS

300 400 500 600 700 800

50

100

150

200

250

VDD (mV)

SN

M

(b) FinFET

HSNM HSNM-NegBL HSNM-LCVDD RSNM RSNM-BWL

40%LCV

DD & NegBL

significantly degradeCol. HS V

MIN

BWL raises Row HS V

MIN >0.8V

10%LCV

DD & NegBL

reduce HSNM

BWL raises Row HS V

MIN

Write Assist - SNM

For 130nm bitcell, applying 40% LCVDD increases the column HS VMIN to 0.75V.

22

300 400 500 600 700 8000

50

100

150

200

250

VDD (mV)

SN

M

(a) 130nm CMOS

300 400 500 600 700 800

50

100

150

200

250

VDD (mV)

SN

M

(b) FinFET

HSNM HSNM-NegBL HSNM-LCVDD RSNM RSNM-BWL

40%LCV

DD & NegBL

significantly degradeCol. HS V

MIN

BWL raises Row HS V

MIN >0.8V

10%LCV

DD & NegBL

reduce HSNM

BWL raises Row HS V

MIN

Write Assist - SNM

For 130nm bitcell, applying 40% NegBL increases the column HS VMIN above 0.8V.

23

300 400 500 600 700 8000

50

100

150

200

250

VDD (mV)

SN

M

(a) 130nm CMOS

300 400 500 600 700 800

50

100

150

200

250

VDD (mV)

SN

M

(b) FinFET

HSNM HSNM-NegBL HSNM-LCVDD RSNM RSNM-BWL

40%LCV

DD & NegBL

significantly degradeCol. HS V

MIN

BWL raises Row HS V

MIN >0.8V

10%LCV

DD & NegBL

reduce HSNM

BWL raises Row HS V

MIN

Write Assist - SNM

For FinFET bitcell, applying 10% NegBL or LCVDD degrades the margins but does not raise the VMIN

24

300 400 500 600 700 8000

50

100

150

200

250

VDD (mV)

SN

M

(a) 130nm CMOS

300 400 500 600 700 800

50

100

150

200

250

VDD (mV)

SN

M

(b) FinFET

HSNM HSNM-NegBL HSNM-LCVDD RSNM RSNM-BWL

40%LCV

DD & NegBL

significantly degradeCol. HS V

MIN

BWL raises Row HS V

MIN >0.8V

10%LCV

DD & NegBL

reduce HSNM

BWL raises Row HS V

MIN

Write Assist Summary

Write assist improves the write VMIN at the cost of HS VMIN

At low VDDs, LCVDD provides the highest improvement in the WM.

25

130nm (40% WA) FinFET (10% WA) (in mV) Write VMIN HS VMIN Write VMIN HS VMIN

No Assist >800 700 500 400

NegBL 450 >800 400 400

LCVDD 400 750 350 400

BWL 400 >800 350 550

Read Assist Techniques

Assist techniques: WL Underdrive (UDWL), NegBL, and Raising VDD (RVDD)

Assist was applied as a percentage of the VDD.

Impact on the Half Select Margins across VDD.

Impact on the Write Margin across VDD.

26

Read Assist - RSNM

For the 130nm bit-cell, high percentages of assist are needed to reduce the HS VMIN to 450mV.

27

300 400 500 600 700 800

10

20

30

40

50

60

70

80

90

100

110

VDD (mV)

RS

NM

(a) 130nm CMOS

300 400 500 600 700 800

10

20

30

40

50

60

70

80

90

VDD (mV)R

SN

M

(b) FinFET

RSNM RSNM-UDWL RSNM-RVDD

10%

20%

10%

HSV

MIN=0.45V

HSV

MIN=0.3V

Read Assist - RSNM

For both bit-cells, RVDD shows the most improvement in the row HS VMIN.

28

300 400 500 600 700 800

10

20

30

40

50

60

70

80

90

100

110

VDD (mV)

RS

NM

(a) 130nm CMOS

300 400 500 600 700 800

10

20

30

40

50

60

70

80

90

VDD (mV)R

SN

M

(b) FinFET

RSNM RSNM-UDWL RSNM-RVDD

10%

20%

10%

HSV

MIN=0.45V

HSV

MIN=0.3V

Read Assist - WM

For 130nm bitcell, Write VMIN is already above 0.8V.

For FinFET bitcell, both read assist tech. degrades the write VMIN, but UDWL shows more degradation

29

300 400 500 600 700 8000

20

40

60

80

100

120

140

VDD (mV)W

M

FinFET

WM WM-RVDD WM-UDWL

Read Assist degrades Write V

MIN

Read Assist Summary

Read assist improves the HS VMIN at the cost of write VMIN

At low VDDs, RVDD provides the highest improvement in the RSNM.

30

130nm (20% RA) FinFET (10% RA) (in mV) Write VMIN HS VMIN Write VMIN HS VMIN

No Assist >800 700 500 400

RVDD >800 450 550 300

UDWL >800 500 650 300

Proposed Solution

RVDD-NegBL UDWL-NegBL UDWL-LCVDD

WL No change Under-driven Under-driven

BL Negative bias Negative bias No change

VDD Boosted for Array

No change Lowered for column

31

Write Delay

NegBL improves the write delay but when high percentages of assist are used Row & Col. HS limit VMIN

32

400 500 600 700 80010

-1

100

101

102

103

VDD (mV)

Write

Dela

y(a) 130nm CMOS

10% NegBL 20% NegBL 30% NegBL 40% NegBL

200 400 600 80010

-2

10-1

100

101

102

VDD (mV)W

rite

Dela

y

(b) FinFET

Col. HS Limit % NegBL

Row HS Limit V

MIN to 0.65V

Row HS Limit V

MIN to 0.35V

Col. HS Limit V

MIN to 0.3V

Proposed - RVDD-NegBL

For 130nm bitcell, applying 10% RVDD with 30% NegBL reduces the array VMIN to 600mV.

33

550 600 650 700 750 800

100

101

(a) 130nm CMOS

VDD (mV)

Write

De

lay

200 400 600 80010

-2

10-1

100

101

VDD (mV)

Write

De

lay

(b) FinFET

0% RVDD 10% RVDD 15% RVDD 20% RVDD 30% RVDD 40% RVDD

ArrayV

MIN

ArrayV

MIN

10% RVDD

& 30% NegBL:

reduces HS failures but not HS V

MIN

15% RVDD

& 40% NegBL: reduces HS V

MIN

& write VMIN

10% RVDD

&

30% NegBL:reduces HS V

MIN

20% RVDD

& 30% NegBL:

raises Write VMIN

30% RVDD

& 40% NegBL:

reduces Write VMIN

40% RVDD

& NegBL:

raises Write VMIN

Proposed - RVDD-NegBL

For the FinFET bitcell, applying 15% RVDD with 40% NegBL reduce the VMIN down to 300mV.

40

550 600 650 700 750 800

100

101

(a) 130nm CMOS

VDD (mV)

Write

De

lay

200 400 600 80010

-2

10-1

100

101

VDD (mV)

Write

De

lay

(b) FinFET

0% RVDD 10% RVDD 15% RVDD 20% RVDD 30% RVDD 40% RVDD

ArrayV

MIN

ArrayV

MIN

10% RVDD

& 30% NegBL:

reduces HS failures but not HS V

MIN

15% RVDD

& 40% NegBL: reduces HS V

MIN

& write VMIN

10% RVDD

&

30% NegBL:reduces HS V

MIN

20% RVDD

& 30% NegBL:

raises Write VMIN

30% RVDD

& 40% NegBL:

reduces Write VMIN

40% RVDD

& NegBL:

raises Write VMIN

UDWL-NegBL

Applying 10% UDWL will not reduce VMIN.

Applying 20% UDWL will increase the VMIN.

41

550 600 650 700 750 800

100

101

VDD (mV)

Write

Dela

y(a) 130nm CMOS

300 400 500 600 700 80010

-2

10-1

100

101

102

VDD (mV)W

rite

Dela

y

(b) FinFET

0% UDWL 10% UDWL 20% UDWL

20% UDWL &30% NegBL:increases write V

MIN & not

enough to reduceHS V

MIN

10% UDWL &30% NegBL:not enough toreduce HSV

MIN

20% UDWL &30% NegBL:degrades writeV

MIN

10% UDWL & 30% NegBL:reduces HS V

MIN

but increases write V

MIN

Array V

MIN=0.35V

Array V

MIN=0.65V

UDWL-LCVDD

For 130nm bitcell, starting with 30% LCVDD applying 10% UDWL will reduce the write & HS VMIN but degrade the read VMIN

42

550 600 650 700 750 800

101

102

(a) 130nm CMOS

VDD (mV)

Write

Dela

y

300 400 500 600 700 80010

-2

10-1

100

101

102

VDD (mV)W

rite

Dela

y

(b) FinFET

0% UDWL 10% UDWL 20% UDWL

Insufficient Read Differential

10% UDWL &30% LCV

DD:

reduces HS VMIN

ArrayV

MIN=0.65V

ArrayV

MIN=0.35V

20% UDWL &30% LCV

DD:

increases write VMIN

UDWL-LCVDD

For FinFET bitcell, applying 10% UDWL will not reduce the write & HS VMIN .

Applying 20% UDWL degrades the write VMIN . 43

550 600 650 700 750 800

101

102

(a) 130nm CMOS

VDD (mV)

Write

Dela

y

300 400 500 600 700 80010

-2

10-1

100

101

102

VDD (mV)W

rite

Dela

y

(b) FinFET

0% UDWL 10% UDWL 20% UDWL

Insufficient Read Differential

10% UDWL &30% LCV

DD:

reduces HS VMIN

ArrayV

MIN=0.65V

ArrayV

MIN=0.35V

20% UDWL &30% LCV

DD:

increases write VMIN

Summary

44

Array VMIN (mV)

% lower VMIN vs. NA

% lower VMIN vs. WA

130nm CMOS

Proposed 600 >25% >20%

[6][7] 650 >19% >13%

[6] 650 >19% >13%

FinFET

Proposed 300 40% 25%

[6][7] 350 30% 13%

[6] 350 30% 13%

The proposed combination allows the most reduction in array VMIN.

Assist per Corner

The worst case write corner is different than the worst case HS corner.

Thus controlling the assist percentage by corner allows more improvement in VMIN.

130nm bitcell

45

Corner NegBL RVDD VMIN (mV) TT 10% 0% 450

SS 10% 0% 450

FF 0% 10% 450

SF 40% 0% 450

FS 0% 20% 450

Assist per Corner

The worst case write corner is different than the worst case HS corner.

Thus controlling the assist percentage by corner allows more improvement in VMIN.

FinFET bitcell

46

Corner NegBL RVDD VMIN (mV) TT 10% 0% 300

SS 10% 0% 300

FF 10% 0% 300

SF 30% 0% 300

FS 10% 15% 300

Thank You! Questions?

47

550 600 650 700 750 800

100

101

(a) 130nm CMOS

VDD (mV)

Write

De

lay

200 400 600 80010

-2

10-1

100

101

VDD (mV)

Write

De

lay

(b) FinFET

0% RVDD 10% RVDD 15% RVDD 20% RVDD 30% RVDD 40% RVDD

ArrayV

MIN

ArrayV

MIN

10% RVDD

& 30% NegBL:

reduces HS failures but not HS V

MIN

15% RVDD

& 40% NegBL: reduces HS V

MIN

& write VMIN

10% RVDD

&

30% NegBL:reduces HS V

MIN

20% RVDD

& 30% NegBL:

raises Write VMIN

30% RVDD

& 40% NegBL:

reduces Write VMIN

40% RVDD

& NegBL:

raises Write VMIN

300 400 500 600 700 800

10

20

30

40

50

60

70

80

90

100

110

VDD (mV)

RS

NM

(a) 130nm CMOS

300 400 500 600 700 800

10

20

30

40

50

60

70

80

90

VDD (mV)

RS

NM

(b) FinFET

RSNM RSNM-UDWL RSNM-RVDD

10%

20%

10%

HSV

MIN=0.45V

HSV

MIN=0.3V

300 400 500 600 700 8000

50

100

150

200

250

VDD (mV)

WM

(a) 130nm CMOS

300 400 500 600 700 800

20

40

60

80

100

120

140

160

180

VDD (mV)

WM

(b) FinFET

NegBL BWL LCVDD

10%

20%

30%

40%

10%

Write V

MIN =0.35VWrite

VMIN

=0.4V

Backup Slides

48

SNM Sensitivity

At high VDDs, the RSNM is most sensitive to PGL and PDR

49

SNM Sensitivity

The RSNM is most sensitive to PGL and PDR at all voltages BWL will negatively impact the RSNM.

50

SNM Sensitivity

The HSNM is most sensitive to changes in PDR and PUR at high VDDs, but at low VDDs PGR starts to play an important role.

51