RISC Processor Design Description

8/13/2019 RISC Processor Design Description

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Presented by

P.SIVA NAGENDRA REDDY

(11741D5715)Under the Guidance of

Mr.A.G.MURALI KRISHNA,M.E

Assistant Professor


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Convolution is an important signal processing application which

is used in filter design.


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Most PC's use CPU based on this architecture. For instanceIntel and AMD CPU's are based on CISC architectures.

Typically CISC chips have a large amount of different and

complex instructions.


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Greater overhead in decoding instructions, therefore

slowdown of execution.

A large variety of addressing modes.

Designing the chips requires more work.

Higher power consumption.


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The philosophy behind RISC is that almost no one uses

complex instructions as used by CISC. Apple for instance

uses RISC chips.

Therefore fewer, simpler and faster instructions would be

better, than the large, complex and slower CISC instructions.


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Small instruction set.

Load/store architecture.

Fixed length coding and hardware decoding.

Large register set.


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CISC:

Consider a program to multiply two bits we write

mov ax, 10

mov bx, 5

mul bx, ax

The total clock cycles for the CISC version might be:

(2 movs 1 cycle) + (1 mul 30 cycles) = 32 cycles


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RISC

Simple instructions, few in

number

Fixed length instructions

Complexity in compiler

Only Load/Store instructions

access memory

Few addressing modes

CISC

Many complex instructions.

Variable length instructions.

Complexity in microcode

Many instructions can

access memory

Many addressing modes


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Each of the register is of 16-bits width capacity.

The bit widths of each unit are as follows:

Instruction Unit : 16 bits

Execution Unit : 8 bits

Memory Unit : 16 bits

Op-code Width : 5 bits


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The Program Counter (PC) is a 16-bit latch that holds the

memory address of location, from which the next instruction

will be fetched by the processor.


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Arithmetic and Logic unit:

The arithmetic and logic unit (ALU) performs all arithmetic andlogical operations.


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Register File:

The register file consists of 8 general purpose registers of 16-bitscapacity each.

These register files are utilized during the execution of arithmetic

and data-centric instructions.

Clock Control Unit:

Efficient phase scheduling is required to optimize the throughput

and the energy consumption of the processor.


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Instruction Decoder Unit:

Instruction set is limited yet comprehensive.

Since opcode is only 5 bits wide, it was

decided to keep the number of instructions supported

within 32 for easier implementation.


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16-BIT INSTRUCTION FORMAT:


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Device Utilization Summary(estimated values):Logic Utilization Used available Utilization

Number of Slices 886 4656 19%

Number of Slice Flip Flops 232 9312 2%

Number of 4input LUTs 1705 9312 18%

Number of bonded IOBs 34 232 14%

Number of MULT18XSIOs 1 20 5%

Number of GCLKs 1 24 4%


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High speed

Low power

Area efficient

Operation-specific design possibilities


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Time period: 5ns (Maximum Frequency: 200MHz)

TOOLS USED:

Software Tool: XILINX 14.3

Programming Language :Verilog HDL


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The design of a single cycle 16-Bit non-pipelined RISC

processor for its application towards convolution application

has been presented. The processor has been designed for

executing the instruction set comprising of 27 instructions in

total.


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In the future we can add some more Digital Signal Processing

applications like FFT and DFT with the help of 32 instructions .


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[1] Robert S. Plachno, VP of Audio A True Single Cycle RISC Processor

without Pipelining. ESS Design White Paper RISC Embedded

Controller.

[2] Youngjoon Shin, Chanho Lee, and Yong Moon, A Low Power 16-Bit

RISC Microprocessor Using ECRL Circuits, ETRI Journal, Volume 26,

Number 6, December 2004.

[3] Yasuhiro Takahashi, Toshikazu Sekine, and Michio Yokoyama, Design of

a 16-bit Non-pipelined RISC CPU in a Two Phase Drive Adiabatic

Dynamic CMOS Logic, International Journal of Computer and Electrical

Engineering, Vol. 1, No. 1, April 2009 1793-8198.

[4] V. B. Saambhavi and V. S. Kanchana Bhaaskaran, A 16-Bit RISC

Microprocessor Using DCPAL Circuits. International Journal of AdvancedEngineering and Technology (IJAET), E-ISSN-0976-3945, Vol.II, Issue I,

January-March 2011, pp. 154-162

[5] J.S. Denker, A Review of Adiabatic Computing, IEEE Symp. Low

Power Electronics, 1994, pp. 94-97.


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RISC Processor Design Description