PROJECT INCLUDES

Designing of 16-bit RISC processor and modeling

Verilog HDLBridging to RISC from CISCDigital simulation of simple and complex

blocksFuture RISK of RISC

RISC

WHAT IS RISC? Reduced instruction set computing CPU design-Simplified instructions can provide higher

performance Opposing architecture –CISC Load-Store architecture -All values for an operation need to

be loaded from memory and be present in registers Android and iPad tablets provided a wide user base for

RISC-based systems RISC families include- DEC Alpha, AMD 29k, ARC, ARM,

Atmel AVR, Blackfin, Intel i860 and i960, MIPS, Motorola 88000, PA-RISC, Power (including PowerPC), SuperH and SPARC

HISTORY & DEVELOPMENT 1960:1970 -First RISC Architecture Term RISC -David Patterson of the Berkeley RISC project -

1980 CDC 6600 designed by Seymour Cray in 1964-Forerunner of

modern RISC systems Michael J. Flynn views the first RISC system as the IBM801

-1980 Public RISC design programs run by DARPA VLSI Program BRP delivery:RISC-I processor in 1982 & RISC-II in 1983(R2

is 3 times faster than R1) PA-RISC-1986 & SPARC-1987 In 1990 IBM develops RISC inspired by SPARC

INSTRUCTIONSSmall & Highly-optimized set of instructionsSimplified-Can provide higher performance Typically have separate instructions for I/O

and data processing

NOW! RISC

“Reduced instruction set computer" is the mistaken idea.

RISC have a larger set of instructions than many CISC CPUs

ADDITIONAL INFO CEERI. In particular, two projects at Stanford University

and University of California, Berkeley are most associated with the popularization of the concept. Stanford's design would go on to be commercialized as the successful MIPS architecture, while Berkeley's RISC gave its name to the entire concept, commercialized as the SPARC. Another success from this era were IBM's efforts that eventually lead to the Power Architecture