Resizing Signed Integers

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Digital Logic Design. Chapter 3 6 March © 20

KU EECS 140/141

Digital Logic Design: An Embedded Systems Approach Using VHDL

Chapter 3

Numeric Basics

Portions of this work are from the book, Digital Logic Design: An EmbeddedSystems Approach Using VHDL, by Peter J. Ashenden, published by MorganKaufmann Publishers, Copyright 2007 Elsevier Inc. All rights reserved.

Digital Logic Design. Chapter 3 2

Numeric Basics Representing and processing numeric

data is a common requirement

unsigned integers

signed integers

fixed-point real numbers

floating-point real numbers

complex numbers




KU EECS 140/141


Unsigned Integers

Non-negative numbers (including 0)

Represent real-world data

e.g., temperature, position, time, …

Also used in controlling operation of adigital system

e.g., counting iterations, table indices

Coded using unsigned binary (base 2)representation

analogous to decimal representation


Binary Representation Decimal: base 10

12410 = 1×102 + 2×101 + 4×100

Binary: base 2 12410

= 1×26+1×25+1×24+1×23+1×22+0×21+0×20

= 11111002

In general, a number x is represented usingn bits as xn –1, xn –2, …, x0, where

00

22

11 222 x x x x n

n

n

n +++= −−

−−








KU EECS 140/141


Truncating Unsigned Numbers

To truncate from m bits to n bits

Discard leftmost bits

Value is preserved if discarded bits are 0

Result is x mod 2n

x(0)

…x(1)

x(n —1)

y(0)

…

…

y1)

y(n —1)

y(m —2)

y(m —1)

y(n)

x <= y(3 downto 0);

x <= resize(y, 4);


Unsigned Addition Performed in the same way as decimal

1 0 1 0 1 1 1 1 0 0

1 1 1 0 0 0 1 1 1 0

0 0 1 1 0 1 0 0 1 0

0 0 1 1 1 1 0 0 0 0

0 1 0 0 1

0 0 11 1 0

1 1 1 0 1

1 1 0 0 1

overflowcarrybits




KU EECS 140/141


Addition Circuits

Half adder

for least-significant bits

Full adder

for remaining bits

000 y xs ⊕=

001 y xc ⋅=

( ) iiii c y xs ⊕⊕=( ) iiiiii c y x y xc ⋅⊕+⋅=+1 11111

10011

10101

01001

10110

01010

01100

00000

ci+1sici yi xi


Ripple-Carry Adder Full adder for each bit, c0 = 0

overflow Worst-case delay

from x0, y0 to sn

carry must ripple through interveningstages, affecting sum bits

full

adder

xi

si

ci

ci+ 1

yi

full

adder

x0

s0

c0

c1

y0

full

adder

x1

s1

c2

y1

full

adder

xn –1

sn –1

sn

cn –1

cn

yn –1




KU EECS 140/141


Improving Adder Performance

Carry kill:

11111

11011

10101

01001

10110

01010

01100

00000

ci+1sici yi xi

Carry propagate:

Carry generate:

iii y xk ⋅=

iii y x p ⊕=

iii y xg ⋅=

Adder equations

iii c ps ⊕= iiii c pgc ⋅+=+1


Fast-Carry-Chain Adder Also called Manchester adder

Xilinx FPGAsinclude thisstructure

xi

gi p

i k

i

si

ci

ci+ 1

yi

xi

pi

si

ci

ci+ 1

yi

0

1

+V




KU EECS 140/141


Carry Lookahead

iiii c pgc ⋅+=+1

0001 c pgc ⋅+=

( ) 001011000112 c p pg pgc pg pgc ⋅⋅+⋅+=⋅+⋅+=

00120121223 c p p pg p pg pgc ⋅⋅⋅+⋅⋅+⋅+=

001230123

1232334

c p p p pg p p p

g p pg pgc

⋅⋅⋅⋅+⋅⋅⋅+⋅⋅+⋅+=


Carry-Lookahead Adder Avoids chained carry circuit

Use multilevel lookahead for wider numbers

x0

g0 p

0

p3

s3

c0

c3

c4

y0

x1

g1 p

1

y1

x2

g2 p

2

y2

x3

g3 p

3

y3

p2

s2

c2 p

1

s1

c1 p

0

s0

carry-lookahead generator




KU EECS 140/141


Other Optimized Adders

Other adders are based on otherreformulations of adder equations

Choice of adder depends on constraints

e.g., ripple-carry has low area, so is ok forlow performance circuits

e.g., Manchester adder ok in FPGAs thatinclude carry-chain circuits


Adders in VHDL Use operations from numeric_std

li r ry ieee; use ieee.numeric_std. ll;...

sign l x, y, s: unsigned(7 downto 0);...

s <= a + b;

sign l tmp_result : unsigned(8 downto 0);

sign l c : std_logic;...

tmp_result <= ('0' & a) + ('0' & b);

c <= tmp_result(8);

s <= tmp_result(7 downto 0);




KU EECS 140/141


Unsigned Subtraction

As in decimal

1 0 1 0 0 1 1 0

0 1 0 1 1 1 0 0

0 – 1 0 0 1 0 1 0

0 1 0 1 1 0 0 0

borrowbits


Subtraction Circuits For least-significant bits

For remaining bits

000 y xd ⊕=

001 y xb ⋅=

( ) iiii b y xd ⊕⊕=

( ) iiiiii b y x y xb ⋅⊕+⋅=+111111

0001100101

01001

10110

11010

11100

00000

bi+1sibi yi xi




KU EECS 140/141


Adder/Subtracter Circuits

Many systems add and subtract

Trick: use complemented borrows

( ) iiii b y xd ⊕⊕=

( ) iiiiii b y x y xb ⋅⊕+⋅=+1

( ) iiii c y xs ⊕⊕=

( ) iiiiii c y x y xc ⋅⊕+⋅=+1

Addition Subtraction

Same hardware can perform both For subtraction: complement y, set 10 =b


Adder/Subtracter Circuits

Adder can be any of those we have seen

depends on constraints

y0

y1

yn –1

y0

c0

cn

y1

yn –1

…

…

…

…

x0

x1

xn –1

x0

x1

xn –1

… s0

s1

sn –1

sn –1

/d n –1

s1

/d 1 s

0/d

0

…

adder

add/sub

ovf/und




KU EECS 140/141


Subtraction in VHDL

li r ry ieee; use ieee.std_logic_1164. ll, ieee.numeric_std. ll;

entity adder_subtracter isport ( x, y : in unsigned(11 downto 0);

s : out unsigned(11 downto 0);mode : in std_logic;error : out std_logic );

end entity adder_subtracter;

rchitecture behavior of adder_subtracter is

sign l s_tmp : unsigned(12 downto 0);

egin

s_tmp <= ('0' & x) + ('0' & y) when mode = '0' else

('0' & x) - ('0' & y);

s <= s_tmp(11 downto 0);

error <= s_tmp(12);

end rchitecture behavior;


Increment and Decrement Adding 1: set y = 0 and c0 = 1

iii c xs ⊕= iii c xc ⋅=+1

These are equations for a half adder

Similarly for decrementing: subtracting 1

half

adder

xi

si

ci

ci+ 1 half

adder

x0

s0

c1

half

adder

x1

s1

c2half

adder

xn –1

sn –1

sn

cn –1

cn

+V




KU EECS 140/141


Increment/Decrement in VHDL

Just add or subtract 1

sign l x, s: unsigned(15 downto 0);...

s <= x + 1; -- increment x

s <= x – 1; -- decrement x

Note: 1 (integer), not '1' (bit)


Equality Comparison XNOR gate: equality of two bits

Apply bitwise to two unsigned numbers

x0

eq …

y0

x1

y1

x n –1

yn –1

…

eq <= '1' when x = y else '0';

In VHDL, x = y gives aboolean result

false or true

can't assign to a std_logic

signal




KU EECS 140/141


Inequality Comparison

Magnitude comparator for x > y x

n –1

gt

xn –1

> yn –1

xn –1

= yn –1

xn –2

> yn –2

xn –2

= yn –2

yn –1

xn –2

yn –2

x1 > y

1

x1…0

> y1…0

xn –2…0

> yn –2…0

x 1 = y 1

x1

y1

x0 > y

0 x

0

y0

… … …


Comparison Example in VHDL Thermostat with target termperature

Heater or cooler on when actualtemperature is more than 5° from target

entity thermostat is

port ( target, actual : in unsigned(7 downto 0);heater_on, cooler_on : out std_logic );

end entity thermostat;

rchitecture rtl of thermostat is

egin

heater_on <= '1' when actual < target - 5 else '0';

cooler_on <= '1' when actual > target + 5 else '0';

end rchitecture rtl;




KU EECS 140/141


Scaling by Power of 2

This is x shifted left k places, with k bitsof 0 added on the right

logical shift left by k places

e.g., 000101102 × 23 = 000101100002

Truncate if result must fit in n bits overflow if any truncated bit is not 0

00

22

11 222 x x x x n

n

n

n +++= −−

−−

( ) 010

22

11 2)0(202222 ++++++= −−+

−−+

−

k k nk

n

nk

n

k x x x x


Scaling by Power of 2

This is x shifted right k places, with k

bits truncated on the right

logical shift right by k places

e.g., 011101102 / 23 = 011102

Fill on the left with k bits of 0 if resultmust fit in n bits

00

22

11 222 x x x x

n

n

n

n +++= −−

−−

k

k k

k n

n

k n

n

k x x x x x x

−−−

−−−

−−− ++++++= 222222/ 0

11

022

11




KU EECS 140/141


Scaling in VHDL

shift_left and shift_right operations

result is same size as operand

y <= shift_left(s, 2);

s = 000100112 = 1910

y = 010011002 = 7610

y <= shift_right(s, 2);

s = 000100112 = 1910

y = 0001002 = 410


Unsigned Multiplication

yi x 2i is called a partial product

if yi = 0, then yi x 2i = 0

if yi = 1, then yi x 2i is x shifted left by i

Combinational array multiplier AND gates form partial products

adders form full product

( )0

02

21

1

00

22

11

222

222

x y x y x y

y y y x xy

n

n

n

n

n

n

n

n

+++=

+++=

−−

−−

−−

−−




KU EECS 140/141


Unsigned

Multiplication

Adders can be any ofthose we have seen

Optimized multiplierscombine parts ofadjacent adders

x0

y1

x1

xn –1

y0

c0

cn

y1

yn –1

yn –2

…

……

xn –2

x0

x1

xn –2

… s0

s1

s2

xn –1

…

sn –1

… s1

s2

…

… … …

sn –1

adder

x0

y2

x1

xn –1

y0

c0

cn

y1

yn –1

yn –2

…

…

…

…

xn –2

x0

x1

xn –2

s0

xn –1

…

adder

… s1s2

…sn –1

x0

y0

x1

xn –1

y0

c0

cn

y1

yn –1

yn –2

…

…

…

…

xn –2

x0

x1

xn –2

s0

xn –1

adder

… s1

s2

…

sn –1

x0 y

n –1 x

1 x

n –1

y0

c0

cn

y1

yn –1

yn –2

…

…

…

…

xn –2

p0

p1

p2

pn –1

pn

pn+1

p2n –2

p2n –1

x0

x1

xn –2

s0

xn –1

adder


Product Size Greatest result for n-bit operands:

( )1221222)12)(12( 122 −−=+−−=−− +nnnnnnn

Requires 22n bits to avoid overflow

Adding n-bit and m-bit operands

requires n + m bits

sign l x : unsigned(7 downto 0);sign l y : unsigned(13 downto 0);

sign l p : unsigned(21 downto 0);...

p <= x * y;




KU EECS 140/141


Other Unsigned Operations

Division, remainder

More complicated than multiplication

Large circuit area, power

Complicated operations are oftenperformed sequentially

in a sequence of steps, one per clock cycle

cost/performance/power trade-off


Gray Codes Important for position encoders

Only one bit changes at a time

10001501007

10011401016

10111301115

10101201104

11101100103

11111000112

1101900011

1100800000

CodeSegmentCodeSegment

See book for n -bit Gray code




KU EECS 140/141


Signed Integers

Positive and negative numbers (and 0)

n-bit signed magnitude code

1 bit for sign: 0 ⇒ +, 1 ⇒ –

n – 1 bits for magnitude

Signed-magnitude rarely used forintegers now

circuits are too complex

Use 2s-complement binary code


2s-Complement Representation

Most-negative number

1000…0 = –2n –1

Most-positive number

0111…1 = +2n –1 – 1

xn –1 = 1 ⇒ negative,

xn –1 = 0 ⇒ non-negative

Since

00

22

11 222 x x x x

n

n

n

n +++−= −−

−−

1222 102 −=++ −− nn




KU EECS 140/141


2s-Complement Examples

00110101 = 1×25 + 1×24 + 1×22 + 1×20 = 53

10110101 = –1×27 + 1×25 + 1×24 + 1×22 + 1×20

= –128 + 53 = –75

00000000 = 0

11111111 = –1

10000000 = –128

01111111 = +127


Signed Integers in VHDL Type signed from numeric_std

li r ry ieee; use ieee.numeric_std. ll;...

s : signed(15 downto 0);

Types signed and unsigned are distinctsign l s1 : unsigned(11 downto 0);

sign l s2 : signed(11 downto 0);...

s1 <= s2; -- illegal

s1 <= unsigned(s2); -- s2 is known to be non-negative...

s2 <= signed(s1); -- s1 is known to be less than 2**11






KU EECS 140/141


Resizing Signed Integers

To extend a negative number

Add leading 1 bits

See textbook for proof

e.g., –7510 = 10110101 = 111110110101

To truncate a negative number

Discard leftmost bits, provided

discarded bits are all 1

sign bit of result is 1


Resizing Signed Integers In general, for 2s-complement integers

Extend by replicating sign bit

sign extension

Truncate by discarding leading bits

Discarded bits must all be the same, and the same asthe sign bit of the result

sign l x : signed (7 downto 0);sign l y : signed (15 downto 0);...

y <= resize(x, y'length);...

x <= resize(y, x'length);

x(0)

…x(1)

x(n —1)

y(0)

…

…

y1)

y(n —1)

y(m —2)

y(m —1)

y(n)






KU EECS 140/141


Signed Addition

Perform addition as for unsigned

Overflow if cn –1 differs from cn

See textbook for case analysis

Can use the same circuit for signed andunsigned addition

021

12 …−

−− +−=

n

n

n x x x 021

12 …−

−− +−=

n

n

n y y y

02021

11 2)(…… −−

−−− +++−=+

nn

n

nn y x y x y x

yields cn –1


Signed Addition Examples

no overflow

positive overflow negative overflow

0 1 0 0 1 0 0 0

1 0 1 1 0 0 0 1

0

72:

105: 1 1 0 1 0 0 1

0 1 0 0 1 0 0 0

1 1 0 0 0 0 0 1

1 0 1 0 0 0 0 1

1

–63:

–32:

–95:

1 1 0 0 0 0 0

1 1 0 0 0 0 0 0

1 1 0 0 0 0 0 1

0 1 1 0 0 0 0 1

1

–63:

–96: 0 1 0 0 0 0 0

1 0 0 0 0 0 0 0

1 1 0 1 0 1 1 0

1 1 0 1 1 1 1 0

0

–42:

–34:

8: 0 0 0 1 0 0 0

0 0 0 0 0 0 0 0

0 0 1 0 1 0 1 0

0 0 1 0 0 0 1 0

1

42:

34:

–8: 1 1 1 1 0 0 0

1 1 1 1 1 0 0 0

0 1 0 0 1 0 0 0

0 1 1 1 1 0 0 1

0

72:

49:

121:

0 1 1 0 0 0 1

0 0 0 0 0 0 0 0

no overflow no overflow

no overflow




KU EECS 140/141


Signed Addition in VHDL

Result of + is same size as operands

sign l v1, v2 : signed(11 downto 0);sign l sum : signed(12 downto 0);...

sum <= resize(v1, sum'length) + resize(v2 sum'length);

To check overflow, compare signs

sign l x, y, z: signed(7 downto 0);

sign l ovf : std_logic;...

z <= x + y;

ovf <= (not x(7) nd not y(7) nd z(7))or (x(7) nd y(7) nd not z(7));


Signed Subtraction

Use a 2s-complement adder

Complement y and set c0 = 1

1)( ++=−+=− y x y x y x

y0

y1

yn –1

y0

c0

cn

y1 yn –1

…

…

…

…

x0

x1

xn –1

x 0 x 1 x n –1

… s0

s1

sn –1

sn –1

/d n –1

s1

/d 1 s

0/d

0

…

cn –1

adder

add/sub

nsigned ovf/und

signed

ovf




KU EECS 140/141


Other Signed Operations

Increment, decrement

same as unsigned

Comparison

=, same as unsigned

>, compare sign bits using

Multiplication

Complicated by the need to sign extend

partial products Refer to Further Reading

11 −− ⋅ nn y x


Scaling Signed Integers Multiplying by 2k

logical left shift (as for unsigned)

truncate result using 2s-complement rules

Dividing by 2k

arithmetic right shift

discard k bits from the right, and replicate

sign bit k times on the left e.g., s = "11110011" -- –13

shift_right(s, 2) = "11111100" -- –13 / 22




KU EECS 140/141


Fixed-Point Numbers

Many applications use non-integers

especially signal-processing apps

Fixed-point numbers

allow for fractional parts

represented as integers that are implicitlyscaled by a power of 2

can be unsigned or signed


Positional Notation In decimal

210110 10410210010124.10 −− ×+×+×+×=

In binary

1021012

2 25.5212021202101.101 =×+×+×+×+×= −−

Represent as a bit vector: 10101

binary point is implicit




KU EECS 140/141


Unsigned Fixed-Point

n-bit unsigned fixed-point

m bits before and f bits after binary point

f

f

m

m x x x x x −−

−−

−− +++++= 2222 1

10

01

1

Range: 0 to 2m – 2 – f

Precision: 2 – f

m may be ≤ 0, giving fractions only

e.g., m= –2: 0.0001001101


Signed Fixed-Point n-bit signed 2s-complement fixed-point

m bits before and f bits after binary point

f

f

m

m x x x x x −−

−−

−− +++++−= 2222 1

10

01

1

Range: –2m –1 to 2m –1 – 2 – f

Precision: 2 – f

E.g., 111101, signed fixed-point, m = 2 11.11012 = –2 + 1 + 0.5 + 0.25 + 0.0625

= –0.187510




KU EECS 140/141


Choosing Range and Precision

Choice depends on application

Need to understand the numericalbehavior of computations performed

some operations can magnify quantizationerrors

In DSP

fixed-point range affects dynamic range

precision affects signal-to-noise ratio Perform simulations to evaluate effects


Fixed-Point in VHDL Use numeric_bit with implied scaling

Use proposed fixed_pkg package

Currently being standardized by IEEE

Types ufixed and sfixed

Arithmetic operations, resizing, conversion

li r ry ieee_proposed; use ieee_proposed.fixed_pkg. ll;entity fixed_converter isport ( input : in ufixed(5 downto -7);

output : out sfixed(7 downto -7) );end entity fixed_converter;




KU EECS 140/141


Fixed-Point Operations

Just use integer hardware

e.g., addition:

f f f y x y x 2/)22( ×+×=+

Ensure binary pointsare aligned

x0

10-bit

adder

… …a

– 4

a – 5

a – 6

a – 7

x7

a3

x8

x9

y0 … …

b – 4

y7b3

b4

b5

c – 4

c3

c4

c5

…

y8

y9

s0 …

s7

s8

s9


Floating-Point Numbers Similar to scientific notation for decimal

e.g., 6.02214199×1023, 1.60217653×10 –19

Allow for larger range, with samerelative precision throughout the range

6.02214199×1023

mantissa radix exponent




KU EECS 140/141


IEEE Floating-Point Format

s: sign bit (0 ⇒ non-negative, 1 ⇒ negative)

Normalize: 1.0 ≤ | M | < 2.0

M always has a leading pre-binary-point 1 bit, so

no need to represent it explicitly (hidden bit )

Exponent: excess representation: E + 2e –1 –1

s exponent mantissa

e bits m bits

12 1

2.1)1(2 +− −

×××−=×= eexponent E mantissas M x


Floating-Point Range Exponents 000...0 and 111...1 reserved

Smallest value

exponent: 000...01 ⇒ E = –2e –1 + 2

mantissa: 0000...00 ⇒ M = 1.0

Largest value

exponent: 111...10 ⇒ E = 2e –1 – 1

mantissa: 111...11 ⇒ M ≈ 2.0

Range:11 222 22

−−

<≤+− ee

x




KU EECS 140/141


Floating-Point Precision

Relative precision approximately 2 –m

all mantissa bits are significant

m bits of precision

m × log102 ≈ m × 0.3 decimal digits


Example Formats IEEE single precision, 32 bits

e = 8, m = 23

range ≈ ±1.2 × 10 –38 to ±1.7 × 1038

precision ≈ 7 decimal digits

Application-specific, 22 bits

e = 5, m = 16

range ≈ ±6.1 × 10 –5 to ±6.6 × 104

precision ≈ 5 decimal digits






KU EECS 140/141


Floating-Point Operations

Considerably more complicated thaninteger operations

E.g., addition

unpack, align binary points, adjust exponents

add mantissas, check for exceptions

round and normalize result, adjust exponent

Combinational circuits not feasible

Pipelined sequential circuits


Floating-Point in VHDL Use proposed float_pkg package

Currently being standardized by IEEE

Types float, float32, float64, float128

Arithmetic operations, resizing, conversion

Not likely to be synthesizable

Rather, use to verify results of hand-

optimized circuits





Summary

Unsigned:

Signed:

Octal and Hex short-hand

Operations: resize, arithmetic, compare

Arithmetic circuits trade offspeed/area/power

Fixed- and floating-point non-integers

Gray codes for position encoding

00

22

11 222 x x x x n

n

n

n +++= −−

−−

00

22

11 222 x x x x n

n

n

n +++−= −−

−−

Documents

Resizing Signed Integers