Reconﬁgurable Analog to Digital Converters for Low Power …13880/FULLTEXT01.pdf · TRITA-ICT/ECS AVH 08:04 ISSN 1653-6363 ISRN KTH/ICT/ECS AVH-08/04–SE ISBN 978-91-7178-932-7

Reconfigurable Analog to Digital Converters for Low

Power Wireless Applications

E. MARTIN I. GUSTAFSSON

Doctoral Dissertation

KTH - Royal Institute of Technology

Stockholm, Sweden, 2008

TRITA-ICT/ECS AVH 08:04ISSN 1653-6363ISRN KTH/ICT/ECS AVH-08/04–SEISBN 978-91-7178-932-7

KTH School of Information andCommunication Technology

Isafjordsgatan 39SE-164 40 Kista

SWEDEN

Akademisk avhandling som med tillstånd av Kungl Tekniska högskolan framläggestill offentlig granskning för avläggande av Teknologie Doktorsexamen i Elektronikoch datorsystem måndagen den 2 juni 2008 klockan 15:00 i sal N1, Electrum 3,Kungl Tekniska högskolan, Isafjordsgatan 28, Kista.

© E. Martin I. Gustafsson, June 2008

Tryck: Kista Snabbtryck AB

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Abstract

The commercialization of Marconi’s radio transmission and reception, along with thedevelopment of integrated circuits in the 1960’s have facilitated many new consumer prod-ucts for wireless communication, where the mobile phones or handsets are one. Thesehandsets started out as a portable phone, mounted in cars, and have with time addedadditional services as Short Message Service, and have today become a media center withglobal positioning, and high-speed internet connection. This has been possible with theuse of multistandard radios, that can receive and transmit information using many dif-ferent wireless communication standards. Many of these handsets have one dedicatedintegrated radio chain for each communication standard used, which results in a largeand expensive integrated circuit for these modern handsets. The challenge of today is tomake modern handsets cheaper, smaller, and lower in power consumption. The powerconsumption is an issue of particular importance since the capacity of the available powersources do not increase with the demands of the handsets. One proposed method to dothis is to move towards Software Defined Radio, where software of the handset control asingle reconfigurable radio, and set which communication standard that the handset is touse. In this way, the handset can be reconfigured to communicate in the most power ordata efficient way, depending on the choice of the user. The area of the Software DefinedRadio receiver is also smaller than the parallel chains that are implemented today, whichreduces the cost of production. The Software Defined Radio receiver is very challengingto design, since there is a large number of wireless communication standards, sometimeseven within the same frequency bands. This make the reception of a weak desired signaldifficult, when there may be a strong interferer in the same frequency band. A key com-ponent in the Software Defined Radio receiver is the Analog to Digital Converter. Thedevelopment of new wireless communication standards requires higher performance of theAnalog to Digital Converter in the receiver. This performance is hard to achieve, whenthe power consumption should be low, and the area should be small, especially in themodern integrated circuit technologies.

This thesis put the development of the communication industry into a historical per-spective, and gives a review of the fundamental development of wireless communicationapplications. The fundamental concepts and implementations of Analog to Digital Con-verters for multistandard wireless receiver chains are also covered. Finally two case studieson the design of multistandard Analog to Digital Converters for Software Defined Radioapplications are presented. These Analog to Digital Converters implement different meth-ods of reconfiguration in order to comply with the requirements of the standards. Thefirst case study is to the knowledge of the author the first reported reconfigurable Analogto Digital Converter for Wireless Personal Area Networks, that can be reconfigured fromBluetooth to the UWB communication standard. This is done by changing the archi-tecture of the Analog to Digital Converter from Sigma Delta type to flash type. Thisreconfigurable Analog to Digital Converter is implemented at transistor level. The secondcase study investigates the limits of circuit level reconfigurability in an algorithmic Ana-log to Digital Converter. It is found that the requirements of two wireless communicationstandards can be covered with the use of smart circuit design techniques. The performanceof this Analog to Digital Converter has been validated with experimental measurements.

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List of Publications

[1] Liang Rong, Martin Gustafsson, Ana Rusu, Mohammed Ismail, “SystematicDesign of a Flash ADC for UWB Applications”, in Proceedings of ISQED2007, San Jose, USA, pp. 108 - 112, March, 2007.

[2] A. Rusu, Martin Gustafsson, Delia de Llera Rodriguez Gonzalez, MohammedIsmail, “Flexible ADCs for Wireless Mobile Radios” in Proceedings of ECCTD2007, Sevilla, Spain, pp. 172 - 175, August, 2007.

[3] Martin Gustafsson, Ana Rusu, Mohammed Ismail, “Behavioral Modeling of aProgrammable UWB/Bluetooth ADC” in Proceedings of ICECS 2007, Mar-rakech, Morocco, pp. 1159 - 1162, December, 2007.

[4] Martin Gustafsson, Ana Rusu, Mohammed Ismail, “Systematic Design of aHigh-Speed Capacitive Interpolative Flash ADC”, Submitted to Analog Inte-grated Circuits and Signal Processing, Springer, 2007.

[5] Martin Gustafsson, Ana Rusu, Mohammed Ismail, “Design of a Reconfig-urable ADC for UWB/BT Radios”, Accepted for publication in proceedings ofNEWCAS 2008, Montreal, Canada, June, 2008.

[6] Martin Gustafsson, Ana Rusu, Mohammed Ismail, Harald Neubauer, JohannHauer, “A Flexible Algorithmic ADC for Wireless Sensor Nodes”, Submittedto ICECS 2008, Valetta, Malta, August, 2008.

[7] Martin Gustafsson, Ana Rusu, Mohammed Ismail, Harald Neubauer, JohannHauer, “A Programmable Algorithmic ADC for Low-Power Wireless Ap-plications”, Submitted to Analog Integrated Circuits and Signal Processing,Springer, 2008.

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Publications not Included in this Thesis

[8] Martin Gustafsson, Jonny Johansson, Jerker Delsing, “A CMOS amplifierfor Piezo-Electric Crystal Interfaces”, In proceedings of MIXDES, Stettin,Poland, pp. 125 - 129, June, 2004.

[9] Martin Gustafsson, Jonny Johansson, Jerker Delsing, “Relative UltrasoundMeasurement Circuit“, in Proceedings of WISP, Faro, Portugal, pp. 322 -327, September, 2005.

[10] Martin Gustafsson, “Integrated Low Power Ultrasound Sensor Interfaces“,Licentiate Thesis, Luleå University of Technology, November, 2005.

[11] Jonny Johansson, Martin Gustafsson, Jerker Delsing, “An autonomous low-power transmit/receive ASIC with on-chip high voltage generation for piezo-electric transducers“, Elsevier Sensors and Actuators A: Physical, Vol 125,pp. 317 - 328, January, 2006.

[12] Martin Gustafsson, Ana Rusu, Mohammed Ismail “A Survey of Reconfig-urable ADCs for Low-Power Wireless applications“, In proceedings of SSoCC,Kålmarden, Sweden, May 2006, (Non-reviewed).

[13] Martin Gustafsson, Ana Rusu, Mohammed Ismail, “A Reconfigurable ADCfor UWB/Bluetooth”, In Proceedings of SSoCC, Fiskebäckskil, Sweden, May,2007, (Non-reviewed).

[14] Kangqiao Zhao, Saifullah Amir, Xiaozhou Meng, Muhammad Ali, MartinGustafsson, Ana Rusu, Mohammed Ismail, “Circuit implementation of a Re-configurable Successive Approximation ADC”, Submitted to ICECS 2008,Valetta, Malta, August, 2008.

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Acknowledgments

I would like to start this thesis by express my gratitude to Docent Ana Rusu, forthe encouragement, support, and inspiration. I would also like to thank ProfessorMohammed Ismail for accepting me as a student, for his triedless encouragementswhen things were at delicate states. Furthermore I would like to thank Saul Ro-driguez Duenas for all the good discussions during my two years at KTH. I wouldnot have gotten this far without your help. I would like to thank Adam Strak, Deliade Llera Rodriguez Gonzalez, Fredrik Jonsson, and Jad Atallah for all the supportand for making my time at KTH as pleasant as it has been.

Education is something that happens on the inside, it is when you change yourway of thinking, and doing things. This process of change is slow, and usuallyprogresses beyond ones normal perception, thus leaving you completely unaware ofthe change you have made, and the progress you currently is making. A momentof recollection, such as writing a summary of the work you have been doing for thelast two years bring these things to your attention.

This process of change is something that your environment is aware of, as oneis thrown between hope and despair. For helping me come this far I have devotedthis thesis to my family, but I would like to mention a few of my friends: Michaeland Anna, Jens, Hans, Alexander, Sus, Dennis, Niclas, Khashayar.

I would like to thank Per Larsson-Edefors, Daniel Eckerbert, Roger Malmberg andLena Peterson for all the support and inspiration in the early stages of my work.

I also would like to thank Jerker Delsing, Per Lindgren, Jonny Johansson, GustafStenberg, Jokke, Linus, Jonas Ekman, C, Magnus Berndtsson, Jerry, and Kalevifor the time at LTU.

I would like to thank Harald Neubauer, Hans Hauer, Jose-Angel Diaz Madrid,Joseph Sauerer and Andrés García-Alonso for making my stay in Germany fruitful.

Finally I would like to mention Allan Olson, Hans-Erik Backram, Marcus Movér,Mats Carlsson, and Jan Lindberg and thank them for the good cooperation duringmy final year.

Martin Gustafsson, March 2008

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Abbreviations and Acronyms

ADC Analog to Digital ConverterAMPS Advanced Mobile Phone SystemBPSK Binary Phase Shift KeyingBT Bluetooth (Not a standard definition)BW BandWidthCDMA Code Division Multiple AccessCCK Complementary Code KeyingCI Capacitive InterpolationCMOS Complementary Metal Oxide SemiconductorCT Continuous TimeDAC Digital to Analog ConverterDCM Dual Carrier ModulationdB deciBeldBc deciBel relative to carrierdBm deciBel related to a 50 Ohm loadDC Direct CurrentDLL Delay Locked LoopDNL Differential Non-LinearityDR Dynamic RangeDVB Digital Video BroadcastingECG Electro Cadio GramENOB Effective Number of BitsF Noise FactorFDD Frequency Domain DuplexingFIR Finite Impulse ResponseFOM Figure of MeritGBW Gain and 3-dB BandWidth productGFSK Gaussian Frequency Shift KeyingGMSK Gaussian Minimum Shift KeyingGPS Global Positioning SystemGSM Global System for Mobile communicationIF Intermediate FrequencyINL Integral Non-LinearityI/Q In-phase and Quadrature-phaseLNA Low Noise AmplifierLO Local OscillatorLSB Least Significant BitMASH Multi stAge Noise sHapingMBPS Mega Bits Per SecondMiM Metal Insulator Metal

viii

Mote Sensor nodeMSB Most Significant BitMSPS Mega Samples Per SecondNF Noise FigureNSD Noise Spectral DensityNTF Noise Transfer FunctionOFDM Orthogonal Frequency Domain MultiplexingPA Power AmplifierPCB Printed Circuit BoardPLL Phase Locked LoopPSD Power Spectral DensityQ Quantization intervalQAM Quadrature Amplitude ModulationQPSK Quadrature Phase Shift KeyingRF Radio FrequencySAR Successive Approximation RegisterSC Switched CapacitorSDR Software Defined RadioSFDR Spurious Free Dynamic RangeΣ∆ Sigma DeltaSlice One of the ADCs in a parallel ADC structureSINAD SIgnal to Noise And Distortion RatioSMS Short Message ServiceSQNR Signal to Quantization Noise RatioSR Software RadioSNDR Signal to Noise and Distortion RatioSTF Signal Transfer FunctionTDD Time Division DuplexingTHD Total Harmonic DistortionUWB Ultra WideBandVCO Voltage Controlled OscillatorWCDMA Wideband Code Division Multiple AccessWiMAX Worldwide interoperability for Microwave AccessWLAN Wireless Local Area NetworkWPAN Wireless Personal Area Network

Contents

Contents ix

List of Figures xii

1 Introduction 11.1 Development of the Communications industry . . . . . . . . . . . . . 11.2 Motivation of this work . . . . . . . . . . . . . . . . . . . . . . . . . 41.3 Systematic design approach . . . . . . . . . . . . . . . . . . . . . . . 61.4 Thesis outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71.5 Author’s contributions . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2 Multistandard radio receivers 112.1 Radio Receiver Architectures . . . . . . . . . . . . . . . . . . . . . . 11

2.1.1 The super heterodyne receiver . . . . . . . . . . . . . . . . . 112.1.2 Homodyne receivers . . . . . . . . . . . . . . . . . . . . . . . 132.1.3 Low IF receivers . . . . . . . . . . . . . . . . . . . . . . . . . 172.1.4 Quadrature receivers . . . . . . . . . . . . . . . . . . . . . . . 17

2.2 Radio Receiver Trends . . . . . . . . . . . . . . . . . . . . . . . . . . 192.2.1 Software Radio . . . . . . . . . . . . . . . . . . . . . . . . . . 192.2.2 Software Defined Radio . . . . . . . . . . . . . . . . . . . . . 21

2.3 Wireless communication standards . . . . . . . . . . . . . . . . . . . 222.4 Analog to Digital Converters for Multistandard Receivers . . . . . . 24

3 Analog to Digital Converters: Overview 273.1 ADC fundamentals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.1.1 Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273.1.2 Quantization . . . . . . . . . . . . . . . . . . . . . . . . . . . 283.1.3 ADC performance measures . . . . . . . . . . . . . . . . . . . 293.1.4 Figures of Merit . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.2 Flash ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353.2.1 The folding technique . . . . . . . . . . . . . . . . . . . . . . 353.2.2 The interpolation technique . . . . . . . . . . . . . . . . . . . 383.2.3 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . 38

ix

x CONTENTS

3.2.4 Trends . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413.3 Sigma Delta ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.3.1 Oversampling . . . . . . . . . . . . . . . . . . . . . . . . . . . 423.3.2 Noise shaping . . . . . . . . . . . . . . . . . . . . . . . . . . . 433.3.3 Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . 453.3.4 Implementations . . . . . . . . . . . . . . . . . . . . . . . . . 493.3.5 Trends . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

3.4 Pipelined ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523.4.1 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . 543.4.2 Trends . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

3.5 Algorithmic ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573.5.1 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . 583.5.2 Trends . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

3.6 Successive Approximation Register ADCs . . . . . . . . . . . . . . . 623.6.1 DAC based SAR . . . . . . . . . . . . . . . . . . . . . . . . . 623.6.2 Charge Redistribution SAR . . . . . . . . . . . . . . . . . . . 633.6.3 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . 643.6.4 Trends . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

3.7 Time interleaving of ADCs . . . . . . . . . . . . . . . . . . . . . . . 653.7.1 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . 65

3.8 Multistandard ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . 673.8.1 Overpower ADC design . . . . . . . . . . . . . . . . . . . . . 673.8.2 Parallel ADC design . . . . . . . . . . . . . . . . . . . . . . . 673.8.3 Reconfigurable ADC design . . . . . . . . . . . . . . . . . . . 68

4 Analog to Digital Converters: Reconfigurability 714.1 Reconfigurability in ADCs . . . . . . . . . . . . . . . . . . . . . . . . 714.2 Architectural reconfigurability . . . . . . . . . . . . . . . . . . . . . . 73

4.2.1 A reconfigurable Σ∆ ADC [74] . . . . . . . . . . . . . . . . . 734.2.2 A reconfigurable pipelined ADC [5] . . . . . . . . . . . . . . . 744.2.3 The architectural reconfigurability case study . . . . . . . . . 76

4.3 Circuit reconfigurability . . . . . . . . . . . . . . . . . . . . . . . . . 764.3.1 Circuit level reconfiguration in a Σ∆ ADC [74] . . . . . . . . 774.3.2 Circuit reconfiguration of a flash ADC [99] . . . . . . . . . . 784.3.3 The circuit reconfigurability case study . . . . . . . . . . . . 79

5 Architectural Reconfigurability: A Case Study 815.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 815.2 The reconfigurable BT/UWB receiver . . . . . . . . . . . . . . . . . 815.3 Reconfigurable ADC design for BT/UWB . . . . . . . . . . . . . . . 84

5.3.1 Sigma Delta ADC . . . . . . . . . . . . . . . . . . . . . . . . 845.3.2 Reconfigurable flash ADC . . . . . . . . . . . . . . . . . . . . 85

5.4 Implementation of the ADC for Bluetooth mode . . . . . . . . . . . 865.5 Implementation of ADC for UWB mode . . . . . . . . . . . . . . . . 91

xi

5.6 Simulation results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 965.6.1 Bluetooth mode . . . . . . . . . . . . . . . . . . . . . . . . . 975.6.2 UWB mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 985.6.3 Simulation results from both UWB and BT modes . . . . . . 100

6 Circuit Reconfigurability: A Case Study 1036.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1036.2 The reconfigurable ADC specifications for Bluetooth and CDMA2000-

1X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1066.3 Algorithmic ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

6.3.1 Flexibility in algorithmic ADCs . . . . . . . . . . . . . . . . . 1096.4 Behavioral modeling of algorithmic ADC . . . . . . . . . . . . . . . . 1106.5 Circuit implementation of algorithmic ADC . . . . . . . . . . . . . . 113

6.5.1 Amplifier design . . . . . . . . . . . . . . . . . . . . . . . . . 1146.6 Simulation results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1146.7 Silicon implementation . . . . . . . . . . . . . . . . . . . . . . . . . . 1166.8 Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

6.8.1 Measurement setup . . . . . . . . . . . . . . . . . . . . . . . . 1176.8.2 Measurement results . . . . . . . . . . . . . . . . . . . . . . . 118

7 Conclusions 123

Bibliography 125

List of Figures

1.1 The Puldhu transmitter station of Marconi’s experiment in 1902[29] . . 21.2 Kilby’s integrated circuit, from the American Institute of Physics: Emilio

Segre Visual Archives . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.3 Early cellular phone from Motorola, the DynaTAC 8000X portable cel-

lular phone, 1984. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.4 Wireless communication standards overview . . . . . . . . . . . . . . . . 5

2.1 The single conversion super heterodyne receiver [59] . . . . . . . . . . . 12

2.2 The signals through a super heterodyne receiver . . . . . . . . . . . . . 142.3 The homodyne receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . 152.4 The signals through a homodyne receiver . . . . . . . . . . . . . . . . . 162.5 The signals through a low-IF receiver . . . . . . . . . . . . . . . . . . . 18

2.6 The quadrature low-IF receiver . . . . . . . . . . . . . . . . . . . . . . . 192.7 Software Radio receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . 202.8 SRD Zero IF receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.9 ADC specifications overview for a Zero-IF receiver . . . . . . . . . . . . 242.10 ADC specifications overview for a Zero-IF receiver . . . . . . . . . . . . 25

3.1 A continuous-time and continuous-amplitude ECG signal . . . . . . . . 283.2 A discrete-time and continuous-amplitude ECG signal . . . . . . . . . . 29

3.3 A continuous-time and discrete-amplitude ECG signal . . . . . . . . . . 303.4 A discrete-time and discrete-amplitude ECG signal . . . . . . . . . . . . 303.5 Static ADC errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.6 A 3 bit flash ADC implemented with comparators and a resistive ladderreference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.7 A 3 bit folding flash ADC, with only 4 two-input comparators. . . . . . 37

3.8 A 4-bit interpolating ADC with a 1-to-4 interpolation scheme . . . . . . 393.9 An illustration of interpolation in a flash ADC. Three new responses are

created with the use of this 1 to 4 interpolation, as shown in Fig. 3.8 . . 403.10 The concept of oversampling . . . . . . . . . . . . . . . . . . . . . . . . 423.11 A first order Σ∆ modulator, shown with quantizer in a) and with quan-

tizer as a noise representation in b) . . . . . . . . . . . . . . . . . . . . . 43

xii

List of Figures xiii

3.12 The noise shaping in different order of Σ∆ modulators . . . . . . . . . . 443.13 The SQNR for different quantizer resolutions and loop order versus OSR 453.14 A second order feedback Σ∆ modulator block diagram . . . . . . . . . . 463.15 A second order feedforward Σ∆ modulator block diagram . . . . . . . . 473.16 Input signal histogram comparison for a feedforward modulator in a)

and a feedback modulator in b) . . . . . . . . . . . . . . . . . . . . . . . 473.17 The 2-1 MASH architecture . . . . . . . . . . . . . . . . . . . . . . . . . 483.18 The steps in a discrete time SC delaying integrator . . . . . . . . . . . . 503.19 A block diagram of a second order continuous time feedback modulator 503.20 A block diagram of a pipelined ADC . . . . . . . . . . . . . . . . . . . . 523.21 A block diagram of a pipelined stage . . . . . . . . . . . . . . . . . . . . 533.22 The processing of an input signal in a 4-stage, 1 bit per stage pipelined

ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533.23 A magnified image of the input from the 4-stage, 1-bit pipelined ADC,

with the associated digital values for the 4-bit conversion . . . . . . . . 543.24 A SC implementation of a 1-bit pipeline stage . . . . . . . . . . . . . . . 553.25 An algorithmic ADC block diagram . . . . . . . . . . . . . . . . . . . . 583.26 A SC implementation of an algorithmic 1-bit ADC . . . . . . . . . . . . 593.27 A SC implementation of the double capacitor technique in algorithmic

ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603.28 Timing diagram of algorithmic ADC operating with time scaling . . . . 603.29 A SC implementation of the double capacitor and double sampling tech-

nique in algorithmic ADCs . . . . . . . . . . . . . . . . . . . . . . . . . 613.30 A simplified timing diagram for the sampling time maximization and

time scaling scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613.31 A block diagram of a DAC based SAR ADC. . . . . . . . . . . . . . . . 623.32 A block diagram of a charge redistribution based SAR ADC. . . . . . . 633.33 A block diagram of time interleaved ADCs. . . . . . . . . . . . . . . . . 66

4.1 Block diagram of the MASH ADC [74] . . . . . . . . . . . . . . . . . . . 744.2 Block diagram of the reconfigurable pipeline [5] . . . . . . . . . . . . . . 754.3 Bias current generation for different modes of operation to amplifiers in

[74] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 784.4 Block diagram of reconfigurable flash ADC [99] . . . . . . . . . . . . . . 794.5 Preamplifier schematic in reconfigurable flash ADC [99] . . . . . . . . . 80

5.1 Handset applications for a BT/UWB transceiver . . . . . . . . . . . . . 825.2 Block diagram of Reconfigurable BT/UWB ADC . . . . . . . . . . . . . 845.3 Block diagram of possible reconfigurability in a CI flash ADC . . . . . . 865.4 Energy per quantization step for flash ADCs . . . . . . . . . . . . . . . 875.5 Block diagram of the 1-to-2 capacitive interpolation scheme . . . . . . . 885.6 Implemented amplifier for the BT Σ∆ ADC . . . . . . . . . . . . . . . . 895.7 Root locus plot for coefficients k1=1.75, b1=1, and b2=0.8 . . . . . . . 905.8 Block diagram of Reconfigurable CI flash ADC . . . . . . . . . . . . . . 91

xiv List of Figures

5.9 Behavioral model of interpolating amplifier from Matlab/Simulink . . . 925.10 Input signal amplitude error caused by sampling clock jitter . . . . . . . 935.11 Behavioral model of signal generator including jitter a) as suggested by

[64], and b) as suggested by [36] . . . . . . . . . . . . . . . . . . . . . . 945.12 Implemented amplifier for the BT Σ∆ ADC . . . . . . . . . . . . . . . . 955.13 Layout of CI flash ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 975.14 Normalized PSD plot from a two-tone test at behavioral level of ADC

in BT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 985.15 Normalized PSD plot from a two-tone test at circuit level of ADC in BT

mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 995.16 Normalized PSD plot from a two-tone test at behavioral level of ADC

in UWB mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 995.17 Normalized PSD plot from a two-tone test at circuit level of ADC in

UWB mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1005.18 SINAD versus input signal voltage for both modes of operation from

behavioral modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1015.19 SINAD versus input signal voltage for both modes of operation from

circuit level simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

6.1 Sensor nodes in landslide early warning system . . . . . . . . . . . . . . 1046.2 Mote block diagram with transceiver . . . . . . . . . . . . . . . . . . . . 1056.3 Overview of the performance of Pipelined, Algorithmic, Σ∆ and SAR

ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1086.4 Overview of the performance of Pipelined, Algorithmic, Σ∆, and SAR

ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1086.5 Detailed block diagram of algorithmic ADC . . . . . . . . . . . . . . . . 1106.6 Amplifier step response depending on non-idealities . . . . . . . . . . . . 1116.7 2-pole amplifier response with different phase margins . . . . . . . . . . 1126.8 Telescopic amplifier with gain boosting . . . . . . . . . . . . . . . . . . . 1146.9 Dynamic range simulation results from behavioral model for Bluetooth

and CDMA2000-1X modes . . . . . . . . . . . . . . . . . . . . . . . . . 1156.10 Power spectral density plot of a full scale input in CDMA2000-1X mode

from behavioral simulation . . . . . . . . . . . . . . . . . . . . . . . . . 1156.11 Power spectral density plot of a full scale input in CDMA2000-1X mode

from schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1166.12 Die micrograph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1176.13 Photo of the test Printed Circuit Board for the characterization of the

algorithmic ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1186.14 SINAD of ADC over range of reconfiguration . . . . . . . . . . . . . . . 1196.15 Dynamic range measurement with 200 kHz input signal . . . . . . . . . 1206.16 PSD plot of a 200 kHz input signal in CDMA2000-1X mode . . . . . . . 120

Chapter 1

Introduction

1.1 Development of the Communications industry

Imagine one day an invention is created, making one or both of the distance com-munications controlled by the Swedish Bureau of Telegraphy, irrelevant. Today fu-turistic scenarios describe the wireless pocket telephone that is every man’s property.Without paying too much attention to these fancies, it is however not unthinkablethat our means of long distance communication can change. This change can be ofsuch magnitude that the equipment owned by the Swedish Bureau of Telegraphy, isturned into a worthless pile of rubbish.- Freely after H. Rydin in 1914 (Original publication in Swedish)

This is how Rydin described the futuristic fantasies, right at the end of the FirstWorld War. These lines were published in a book written as a tribute to the bankerMarcus Wallenberg on his 50:th birthday.

If Rydin by the time of writing was aware of the wireless telegraph and the demon-strations that both Marconi and Popov already had made in the end of the nine-teenth century is unknown. Popov and Marconi started at about the same timeto transmit text messages with the wireless telegraph, and both are known as thefathers of the wireless telegraph. Neither Popov nor Marconi really made a techno-logical invention with their communication as such, it was rather an implementa-tion of the already established knowledge in the academia. Popov, who came fromthe Russian academia, developed a demonstrator that communicated the message“Heinrich hertz” in 1896 [59]. Marconi on the other hand came from a rich Italianfamily, with no academic background in line with Popov. His dedicated interest,engineering skills and solid funding allowed him to build a wireless telegraph thatwith the help of his parents, attracted the attention of the British authorities [59].This attention awarded him a patent, and the possibility to continue his experi-ments, now in a company based in Great Britain, which evidently lead to the first

1

2 CHAPTER 1. INTRODUCTION

transatlantic communication in 1902 [29]. The Puldhu transmitter station used inthis first communication is shown in Fig. 1.1.

Figure 1.1: The Puldhu transmitter station of Marconi’s experiment in 1902[29]

These systems were still in their cradle in 1914, and the development of the com-ponents for these wireless systems were large and extremely high in power. Thisstrongly limited the deployment of electronics in many areas. How Rydin visionedthe pocket size electronic system is very difficult to understand, until 33 years later,when the transistor was invented at Bell Labs in 1947 by Bardeen, Brattain, andShockley. Several research companies were interested in this development, and in1959 the integrated circuit (IC) was invented at both Texas Instruments by Kilby,and at Fairchild Semiconductor by Noyce. Both of them filed for patents, and bothof them were also granted patents, Noyce in 1961, and Kilby in 1964. Kilby’s inte-grated circuit is shown in Fig. 1.2

In the 1960’s, ICs were in their cradle, and Rydin’s now almost 50-year old visionwas still far away from becoming real. The electronic industry exploded in the late1960’s and onwards, and this lead to smaller integrated circuits with more func-tionality to a lower cost, for each integrated circuit generation that was created.This was described by Gordon Moore in 1965 as “Moore’s law” [48]. The wirelesstelephones were now based in cars, to support the weight of the electronics and toprovide power for the device. Experiments were going on how to extend the rangeand provide services for a mass market, but the interest of the authorities was stilllacking.

The first commercial cellular phone call was made 14 years later in Tokyo, in 1979,and one year later in the United States. By this time the cellular infrastructures

1.1. DEVELOPMENT OF THE COMMUNICATIONS INDUSTRY 3

Figure 1.2: Kilby’s integrated circuit, from the American Institute of Physics:Emilio Segre Visual Archives

had already been built in both countries. One early cellular phone, from 1984 isshown in Fig. 1.3.

Figure 1.3: Early cellular phone from Motorola, the DynaTAC 8000X portablecellular phone, 1984.

Today, the fancies told by Rydin back in 1914 are true since more than a decade.The development of this wireless pocket phone, or handset is heading for new chal-lenges. The handset was originally developed to provide telephone calls, but sincethe integration of the Short Message Service (SMS) into the Global Standard ofMobile communication (GSM) in the mid 1980’s, the additional services of handsetshave been growing fast. Today a high-end handset can have features like music, FMradio, TV, high-speed Internet, Global positioning, etc. The communication of thehandset can be of one or many standards, e.g. over one of the generations of mobilecommunication (2G, 2.5G, 3G a.s.o.), or directly over wireless high-speed Internetconnections, provided by one of many network service providers. The applicationsof the wireless communication is not limited to only the handset, but many other


small electronic devices use wireless communication to transmit and receive data,which was something that Rydin could not foresee in 1914.

The abundance of wireless communication standards is also problematic for thedevice. The available frequency spectrum for wireless communication is limited,and thus more standards are competing to provide services, sometimes even in thesame frequency spectrum.

This means that small and sensitive signals need to be filtered and demodulatedfrom the ether that used to be quiet (except from around Marconi’s transmitters),but is filled with strong wireless communication traffic today. In addition to thesestrong interferers, the high mobility of the handset can cause heavy fading of thesignal. This makes the receiver the most interesting part in the multistandard de-vice.

The industry implements a new receiver for each standard that is added to themultistandard device, and this new receiver is added next to the other ones ona single IC [69]. For a multistandard device as the high-end handsets are today,this IC becomes large, which is impractical from a cost-of fabrication perspective.The large number of analog and digital blocks also increase the power consumptionof the IC, if not proper care is taken to ensure that everything is powered downproperly. An illustration of such a multistandard receiver is shown in Fig. 1.4.

This receiver is also impractical since many of the features needed in these paralleltransceivers are similar, and could be reused between several standards.

The increase in power consumption is problematic, since the energy density ofrechargeable power sources do not increase as fast as the power consumption ofthe electronics does. This implies that the devices become heavier and larger toaccommodate the larger power sources, which decreases the portability. These aretwo factors why the reduction of power consumption in multistandard receivers iscritical to allow high-end products to become cheaper, smaller and thus availableto a broader potential market.

1.2 Motivation of this work

This thesis addresses the design of reconfigurable Analog to Digital Converters(ADCs) for low power multistandard wireless receivers. The multistandard wire-less receivers that are implemented today are parallel, which makes them large insize [69], which increase the cost of fabrication, and the power consumption of theintegrated circuit due to the leakage currents. The push for longer standby andoperation times of these applications force the power consumption of the electronicsto be reduced.

1.2. MOTIVATION OF THIS WORK 5

LNA

VGA

VGA

ADC

ADC

I

Q

Multi-

Band

Generator

90o Baseband

processing

LNA

VGA

VGA

ADC

ADC

I

Q

Multi-

Band

Generator

90o Baseband

processing

LNA

VGA

VGA

ADC

ADC

I

Q

Multi-

Band

Generator

90o Baseband

processing

WLAN

GSM

WCDMA

Data out

Data out

Data out

Dat

a pro

cess

ing

Figure 1.4: Wireless communication standards overview

The ADC requirements for modern wireless communication standards are pushedupwards in sampling frequency and dynamic range. One example of this is when the3G mobile standard was developed, the CDMA2000 was abandoned in most places,in privilege of the WCDMA communication, which requires more bandwidth of theADC. The sampling frequency of the ADC for a zero-Intermediate Frequency (IF)receiver changed from 1.25 MHz up to 5 MHz, for an In-phase/Quadrature-phase(I/Q) receiver.

The ADC performance does not scale with process as the digital performance does,and new techniques are needed to improve the ADC performance. This is em-phasized by trends like Software Radio, where the receiver is an antenna, a FrontEnd Module (FEM), and an ADC. In this application, the ADC needs to cover avery wide bandwidth at high resolution. In the Software Defined Radio (SDR), thereceiver is built with reconfigurable blocks, and the ADCs have to be made recon-


figurable in sampling rate and dynamic range. This without introducing significantoverhead in either leakage currents or area, compared to a customized solution.

This thesis investigates ADC reconfigurability, with the focus on achieving the spec-ifications set by Zero-IF multistandard SDR receivers, in two low-power wirelessapplications.

1.3 Systematic design approach

Reconfigurable ADCs are complex systems that can be difficult to design, sincemany architectures and parameters need to be evaluated to find an optimal solu-tion, before the real design effort can start. The experienced ADC designers knowhow the design should start, simply because they have done it many times before,and with their experience they can quickly estimate the important circuit specifica-tions. For the beginners, it is hard to know how to start. This is where behavioralmodeling of ADCs comes in handy. This design methodology have been used for along time for Sigma Delta ADCs, but it has not been used to the same extent forother ADC architectures.

The procedure starts with the design of a high-level model of the ADC, in an envi-ronment where circuit implementation issues, such as biasing can be disregarded.This creates a rapid understanding of the functionality of the ADC, and allows anoptimal solution to be found, along with circuit block specifications [37, 64, 89, 90].

The method with which the work in this thesis has been performed is:

1. Design high-level ideal ADC model

2. Gradually introduce circuit based non-idealities

3. Find circuit block specifications for the building blocks, and verify the im-plications of these non-idealities to the system level, e.g. through SINADmeasurements

4. Implement VerilogA/AHDL models in Cadence, and validate the system levelspecifications, now with bias voltages

5. Implement the circuit blocks to the specifications, and gradually replace theVerilogA/AHDL models with circuit blocks

6. Validate the system level specifications by using co-simulations, where thecritical blocks are represented as circuits, and the non-critical blocks as Ver-ilogA/AHDL models

1.4. THESIS OUTLINE 7

7. Finally validate system specifications at circuit level

8. Freeze schematics and start layout

9. Validate layout with post-layout simulations

10. Tape-out, fabrication and measurements

This method will save time, since only the critical blocks of the ADC are repre-sented by the complex circuit description, and the other blocks are represented asVerilogA/AHDL models.

1.4 Thesis outline

Chapter 1 is the introduction of the thesis, where the area of integrated circuitsand wireless communication is put into a historical perspective. The motivation ofthe thesis is given, the method with which the work has been conducted, as well asa summary of the scientific contributions.

Chapter 2 describes radio receivers in more detail, and also reconfigurable radioreceivers. With the base of these reconfigurable receivers, the ADC specificationsfor a number of wireless communication standards are also given. Based on thesedifferent specifications, an overview of multistandard ADC solutions are presented.

Chapter 3 discusses the fundamentals of analog to digital conversion, and givesa refresher of the basic concepts for a few ADC architectures that provide a highdegree of flexibility. The Sigma Delta ADCs are discussed in particular, along withflash, pipeline, and algorithmic ADCs. The chapter is concluded with a discussionabout multistandard ADCs, and design approaches for multistandard ADCs.

Chapter 4 is devoted to reconfigurability in ADCs. The concepts of architec-tural and circuit reconfiguration are explained, and two examples are presentedin more detail on each level of reconfiguration. It introduces the case studies ofChapters 5 and 6.

Chapter 5 is a case study on an architectural reconfigurable ADC, where a novelADC that can be reconfigured between Bluetooth and WiMedia OFDM Ultra Wide-Band (UWB) standards is proposed.

Chapter 6 is a case study of circuit level reconfigurability in ADCs, and showshow an algorithmic ADC can be configured for many applications, and among theseto be used in a SDR receiver targeted for the Bluetooth and the CDMA2000-1Xcommunication standards.


Chapter 7 presents the conclusions of the thesis.

1.5 Author’s contributions

This thesis is based on the publications in the list of publications. The content andcontribution of the publications are as follows:

In [1] the need of accurate behavioral modeling in the systematic design of a Ca-pacitive Interpolation (CI) flash ADC is demonstrated. Behavioral modeling hadpreviously mainly been used for Sigma Delta ADCs, but this work illustrates thefeasibility to implement this for flash ADCs as well. The author wrote and pre-sented the paper, based on the work of Liang Rong.

In [2] the feasibility of a reconfigurable ADC that covers all the present wirelesscommunication standards is presented. The technique to solve this is presented,along with simulation results from the behavioral model of the ADC for all modesof operation. The author proposed the solution on how to reconfigure the ADCarray to include the UWB standard, and wrote two sections of the paper.

In [3] the behavioral modeling results of a reconfigurable ADC that covers Blue-tooth and UWB communication standards are demonstrated. It is illustrated howthe reconfiguration between these standards can be achieved, and simulation re-sults from the behavioral model in both modes of operation are shown. The authorproposed the solutions and wrote the paper.

In [4] a new amplifier model for high-speed ADCs, a more accurate jitter model forflash ADCs, and the implementation results of the full systematic design flow of aCI flash ADC for UWB applications are presented. The author implemented themodels, the circuits, and wrote the paper.

In [5] the circuit implementation of the reconfigurable Bluetooth/UWB ADC isdemonstrated. It is shown that the concept from [3] is feasible, and that it can beimplemented at circuit level. The author implemented the models, the circuits andwrote the paper.

In [6] the behavioral modeling is extended to algorithmic ADCs, and it is shownthat an accurate model can be build. The circuit implementation is done based onthe behavioral level simulation results. Secondly, reconfigurability is investigatedfor algorithmic ADCs. The author wrote the paper, and implemented models andcircuits.

1.5. AUTHOR’S CONTRIBUTIONS 9

In [7] the measurement results of the flexible algorithmic ADC presented in [6]are shown. The measurement setup is presented, along with measurements of therange of reconfigurability for a given sampling rate. The author wrote the paper,and performed the measurements.

Chapter 2

Multistandard radio receivers

2.1 Radio Receiver Architectures

One of the central steps in making Rydin’s vision for the handset come true, wasto drastically reduce the size and power consumption of the radio that Marconiused. The pulses sent by the transmitter stations quickly faded with distance, andwere easily drowned in the noise generated in the receiver. This called for moreadvanced receivers, and a new way to receive signals was discovered by Armstrongduring his service in France during 1918 [2]. It was named the super heterodynereceiver.

2.1.1 The super heterodyne receiver

The earliest reports on the super heterodyne receiver dates back to 1918, wherethe full details of the system were not made public until late 1919 [6]. In thosedays, some recent improvements to the super heterodyne receiver were presented,along with enhancements that made this type of receiver a success [6]. The nameheterodyne comes from super hetero- which means very different, and -dyne whichmeans tone. A block diagram of a super heterodyne receiver for audio applicationsis shown in Fig. 2.1. This receiver is a dual conversion receiver, which means thatthere are two frequency conversion steps that takes place. The frequency conversionis changing the Radio Frequency (RF) input, to two Intermediate Frequency (IF)signals, IF1 and IF2.

There are several components involved to transform the input RF signal into thedesired audio signal at the end of the receiver, shown in Fig. 2.1. The blocks in thereceiver from left to right are:

Antenna it receives the signal. The antenna is adjusted to receive the desiredfrequency band.

11

12 CHAPTER 2. MULTISTANDARD RADIO RECEIVERS

LNA IF-A

Local

Oscillator1

Demod.Audio

processing

Tuning

1 2 3

5

6 7 8 12 Audio

out4

Ban

d s

elec

t

Imag

e re

ject

Ch

ann

el s

elec

t

Local

Oscillator2

9

10

Ch

ann

el s

elec

t

11

Tuning

Figure 2.1: The single conversion super heterodyne receiver [59]

Band select filter of the Front End Module (FEM). This filter makes the firstselection of the input signal, and may also be used in the duplexing process, if thereis a transmitter that is using the same antenna.

Low Noise Amplifier (LNA) provides the first gain in the chain. This is usuallyimplemented as a narrow band block, that should add very little noise to the signal.

Image reject bandstop filter rejects the image band, in order to reduce theeffect of interferers and noise coming from the image band.

Mixer 1 performs the first frequency down-conversion. The image reject filtermakes sure that the signal is kept clean from noise and interferers. The mixer isusually a wide-band block.

Frequency generator (LO1) generates the first reference signal for the frequencydown conversion. This Local Oscillator (LO) could be trimmed by external com-ponents and gauges, in order to fine tune the receiver to the right frequency.

Channel select bandpass filter 1 removes the cross products created in themixer, and the RF and LO leakage that is coupled across the terminals of themixer. It also attenuates the in-band interferers before the amplification.

IF1 amplifier is the second stage of amplification. Low noise levels are impor-tant in this amplifier, since the signal levels can still be low.

Mixer 2 creates the final frequency down conversion. Now the signal is convertedinto the region where it can be detected by the demodulator.

Frequency generator (LO2) performs the second frequency down conversion.The frequency of this second LO can be tuned, in order to compensate for drift andother undesired effects.

2.1. RADIO RECEIVER ARCHITECTURES 13

Channel select bandpass filter 2 removes the cross products created in thesecond mixer, and performs further attenuation of in-band interferers.

Demodulator finally converts the received signal to the desired information.

Audio processing amplifies and filters the audio signal to provide the desirablefrequency content (Equalization).

The signals through the receiver chain are shown in Fig. 2.2, where it can be seenhow the frequency and amplitude in the spectrum changes at each node in Fig. 2.1.The signals shown in the figure are simplified, and e.g. the effects of the mixer 2on the LO1 is neglected. Proper care have to be taken in the selection of the LOfrequencies, so that the downconversion in mixer 2 of LO1 does not fall into theimage bands.

There are two central performance measures in a receiver chain, sensitivity andselectivity. Sensitivity is a measure on how small signals the receiver chain candetect and process. Selectivity is a measure on how well the receiver can distin-guish the signal from a noisy background. The background can, as in part 1 ofFig. 2.2, contain other strong signals that do not contain relevant information forthe reception of the desired signal. These signals are called interferers, or blockers.If the receiver is not properly designed, then these strong signals can saturate thereceiver, in such a way that the desired signal cannot be processed, thus blockingthe receiver. The linearity of the receiver is also important, in order not to createintermodulation products inside the receiver chain that may block the signal. Toavoid these internal blockers to be created, strict specifications are given for thelinearity of the blocks, especially at the end of the receiver chain where the signalshave been amplified many times. The noise performance, or how much noise thedifferent blocks add to the signal, is also important. This is particularly true forthe first blocks in the receiver chain, where the signal levels can be small.

The super heterodyne receiver has previously been implemented in many typesof applications, and a few examples are given in e.g. [86].

2.1.2 Homodyne receivers

In contrast to the heterodyne receivers, the homodyne receivers (homo = same,dyne = tone) use the same LO frequency to mix the signal down into zero frequencywith one down conversion only. These receivers are also called direct conversion re-ceivers. By using the same LO and RF frequencies, the image frequency problem isavoided. This was originally proposed by Colebroak in 1924 [27]. This architecturemade the receiver less complex, since there was only one down conversion, which


f (Hz)

A (V)

1f (Hz)

A (V)

2

Band select

filter

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gain

fs

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LO1)

Demod...trees of green, red roses too,I see them bloom...

12

f (Hz)

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reject

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select 1fLO1

7f (Hz)

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fLO1

8

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)

10

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fIF2

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fLO1

9

fIM2

= fLO2

+ (fLO2

- fIF1

)

fLO2

fIM2

f (Hz)

A (V)

Channel

select 2

fLO1

11

fLO2

fIF2

Figure 2.2: The signals through a super heterodyne receiver

required a lower number of components. The implementation of this architecturewas not straight-forward, and the central difficulties were e.g. DC offset, and driftand inaccuracy of the components. The invention of the Phase Locked Loop (PLL)by the French scientist Bellescise in 1932 [18] later opened the door for improvementand further deployment of the homodyne receiver. A block diagram of a homodynereceiver for audio applications is shown in Fig. 2.3.


LNA IF-A

Local

Oscillator

Demod.Audio

processing

Tuning

1 2 3

4

5 6 7 8 Audio

out

Figure 2.3: The homodyne receiver

Some of the blocks in the homodyne receiver are the same as in the heterodyne re-ceiver, when going through the receiver chain from left to right, e.g. the antenna,the band select filter, the LNA, and the mixer. The other blocks in the chainhave small differences:

Frequency generator or LO, is set to the same frequency as the RF signal,in order to mix the received signal directly into the baseband.

Baseband filter provides the majority of the filtering after the mixer, includ-ing the mixer cross products that are not LO leakage to the RF port, and also thein-band interferers that may exist.

Baseband lowpass amplifier provides gain at baseband, and does some fur-ther filtering of the input signal, since it has an inherent low-pass characteristic.

At the end of the chain, the demodulator and the audio processing is a bitdifferent, but the function of the blocks are the same.

The signals processed through the receiver chain are shown in Fig. 2.4, where itcan be seen that there is no longer an image frequency problem.

The same performance requirements for sensitivity, linearity, noise and selectiv-ity that applies to the heterodyne receiver also applies for the homodyne receiver.There are several benefits associated with the homodyne receiver. The decreasein complexity and the absence of the image frequency were already mentioned.Furthermore, the required low-pass channel filter is easier to implement than theIF band-pass filter, since it requires fewer poles to realize the same out-of-band at-tenuation. It also operates at lower frequency, which also can reduce the filter order.

The main design challenges for the homodyne receiver are:

Local oscillator stability this was alleviated to some extent by the invention


f (Hz)

A (V)

1f (Hz)

A (V)

2

Band select

filter

f (Hz)

A (V)

3

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gain

fs

fs

fs

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fs - f

LO = 0

5

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low-pass filter

fLO

6

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amplification

fLO

7

Demod...for me and you,and I think to myself...

8

f (Hz)

A (V)

4fs

fLO

No image

problem

Figure 2.4: The signals through a homodyne receiver

of the PLL.

Flicker noise or 1/f noise is low frequency noise, which is inversely proportionalto the frequency [46]. It was originally discovered by Johnson in 1925. It is lowerin Bipolar Junction Transistors (BJTs), compared to Complementary Metal OxideSemiconductor (CMOS) transistors, and it is a concern in homodyne receivers, dueto the low frequencies used.

Direct Current (DC) offset mainly comes from the self mixing of the LO signal.This occurs in the mixer, since there is a leakage of the LO signal to the RF input.This causes problems like saturation of the baseband filters and amplifiers after themixer in the receiver chain. It can also cause distortion of the signal since there


may be information at zero frequency. This can be avoided by making sure thatthere is sufficient isolation between the ports of the mixer. Sophisticated DC offsetcancellation loops can today deal with the varying DC amplitudes which occurs inmodern communication systems, due to even order intermodulation distortion [66].

One architecture that avoids the low-frequency issues is the low-IF receiver.

2.1.3 Low IF receivers

The low-IF receiver works like a single conversion super heterodyne receiver, asexplained in Section 2.1.1. The signal is down-converted to a low frequency bandnear DC, and the low frequency problems are thus avoided. There are mainly twobenefits of the low-IF receiver; the filter implementation is straight forwards, sincethe required bandwidths are small, and there is no information in the DC band thatcan be corrupted with DC offsets, which allows the DC value to be blocked. Thesignals through a low-IF receiver, which has a similar block diagram as the singleconversion super heterodyne receiver shown in Fig. 2.1, are shown in Fig. 2.5. Inthis figure it can be seen that the IF band is much closer to DC, but it does notoverlap DC.

One aspect that has not been discussed much in the chapter so far is the modu-lation. The early radio stations used Amplitude Modulation (AM) or FrequencyModulation (FM), or variations of these to transmit the radio signals. The strongpoint of these modulation schemes were that the receiver could be very simple. Thedownside was that the data rate was very low and sensitive to non-idealities. Inaddition, a lot of transmitter power was wasted in the carrier signal in AM stations.As more data was to be transmitted over wireless communication links, new mod-ulation schemes were invented to increase the efficiency. Some of these modulationschemes were analog, e.g. Single Side Band-Suppressed Carrier (SSB-SC), and latersome of them were based on the robust digital modulation schemes. Common forboth of them was that they required more from the transmitter and the receiver.The information was no longer only encoded in either phase or amplitude, but inboth. In order to differentiate the two, the quadrature receiver (and transmitter)were developed.

2.1.4 Quadrature receivers

The transmitter in most digital modulation schemes, e.g. Quadrature AmplitudeModulation (QAM), use simultaneous phase- and amplitudemodulation. Thephase modulation is done with the use of two orthogonal sinusoidal signals (sinand cos). These signals also have to be generated in the receiver to demodulatethe signal [88]. A receiver (or a transmitter) that uses these orthogonal referencesis called a quadrature receiver (or transmitter). A block diagram of a quadrature


f (Hz)

A (V)

1f (Hz)

A (V)

2

Band select

filter

f (Hz)

A (V)

3

LNA

gain

fs

fs

fs

f (Hz)

A (V)

4

fs

Image

band fLO

fIM

fIM

= fLO

- (fs - f

LO)

f (Hz)

A (V)

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Down

conversion

fLO

fIM

fIF

= (fs - f

LO)

5

f (Hz)

A (V)

fIF

Channel select

filter

fLO

6

f (Hz)

A (V)

fIF

Channel

amplification

fLO

7

Demod...I see skies of blue,and clouds of white...

8

Figure 2.5: The signals through a low-IF receiver

receiver is shown in Fig. 2.6, where two parallel receiver chains can be seen. Thetop receiver chain is called the quadrature receive chain, and it has a 90 degreesphase shift added to it. The second receiver chain is called the in-phase receivepath. This allows both the amplitude and the phase information to be extracted.This can also be used for high-IF and zero-IF receiver architectures. For furtherinformation and explanation, look in [88, 101]. A second change from the previousarchitectures is that the signal processing now has shifted from the analog domain,with equalizers and audio amplifiers, to ADCs, where the signal processing is donein the digital domain.

All of this development happened for many years ago, and it continues with into

2.2. RADIO RECEIVER TRENDS 19

LNA

VGA

VGA

ADC

ADCI

Q

LO

90o Baseband

processing

Figure 2.6: The quadrature low-IF receiver

smaller radios having more functionalities. To summarize the trends in modernreceiver architectures, a small overview is given.

2.2 Radio Receiver Trends

There are two modern trends in radio receiver architectures, and they are Soft-ware Radio (SR) and Software Defined Radio (SDR). There is no clear distinctionbetween the two approaches today, since many of the definitions comes from thehigher levels of the radio standards, and the physical implementation is a level ofabstraction where both of these explanations could fit. To make a distinction be-tween the two concepts from a feasibility standpoint, and as a motivation why thiswork only targets one of the two approaches the following two sections will describethe two terms in more detail.

2.2.1 Software Radio

Software radio is a vision of moving the analog to digital conversion up in frequencyand as close to the antenna as possible, in order to reduce the number of analogcomponents that are needed in the design. This concept is illustrated in Fig. 2.7,where three blocks are shown in the receive path, the FEM, the ADC and the signalprocessing, which in this case is digital down conversion and demodulation.

The strongest benefit of the Software Radio, is that the majority of the RF signalprocessing is done in the digital domain. Even if this digital part is large and com-plex, it will decrease in size with new CMOS generations. It can also be set to anyfrequency within the range of the ADC and FEM. But at the same time, this isalso the limitation. The ADCs cannot be made fast enough and sensitive enough tomake this vision practical. The analog performance does not scale with technologyas the digital does.


ADCSignal

processing

Digital control

Data out

L1 NF

ADC

Figure 2.7: Software Radio receiver

One example of a Software Radio ADC specification is for a WCDMA system.The noise floor of the antenna needs to be at -99 dBm, to fulfill the Bit Error Rate(BER) requirement for the standard. This allows the total Noise Figure (NF) of thereceiver to be 9 dB [10]. This NF specification implies that the noise contributedby the receiver chain, (the FEM and the ADC in this case), can degrade the signalby 9 dB. The ADC in this scenario should have a sampling rate of 4.4 GHz, sincethe WCDMA band ends at 2.2 GHz. One tutorial on ADC performance related toNoise Figure (NF) is [11]. The NF of the ADC can be determined from the Friisformula [88], where the total noise factor Ftot for this receiver is determined by

Ftot = L1 +F2 − 1

1/L1, (2.1)

where Ftot is the noise factor of the receiver (10NF/10), L1 is the loss in the FEM,and F2 is the ADC noise factor. Assume that half of the noise is contributed bythe FEM, and half comes from the ADC, then L1 = 10log(109/10/2) = 5.9 dB.This is a high figure for a single-standard FEM, but since this is supposed to bea wide-band component it has to support both Time Division Duplexing (TDD)as well as Frequency Division Duplexing (FDD) it can be a realistic figure. Thisleaves the other half of the noise to be associated to the ADC, and its noise figurecan be determined in the same way

Ftot − L1 =F2 − 1

1/L1, (2.2)

which can be simplified to

Ftot − L1

L1+ 1 = F2 =

7.94 − 3.97

3.97+ 1 = 2.0, (2.3)

2.2. RADIO RECEIVER TRENDS 21

which is 3 dB. A few more assumptions have to be made regarding the ADC inaddition to the sampling rate, and one of them is the full-scale voltage, and its RootMean Squared (RMS) value. A common ADC has a 1 V peak to peak full-scalevoltage, which gives a RMS full-scale voltage of +4 dBm. In order to establish theSNR of the ADC, the input noise is assumed to be only the noise in a 50 Ohmresistor, which is -174 dBm/Hz, and the ADC NF is 3 dB, which implies that theoutput noise spectral density (NSD) of the ADC is -171 dBm/Hz. Now the SNRof the ADC over the whole band can be determined by [11]

SNR = Pfull−scale − NSDADC − 10 · log(

fsamp

2

)

, (2.4)

where SNR is the Signal to Noise Ratio of the ADC, NSDADC is the -171 dBm/Hzfrom above, Pfull−scale is the ADC full scale power, and fsamp is the ADC samplingfrequency. This results in a SNR of 81.6 dBs. To this some margin needs to beadded, since the quantization noise is not completely white, and a margin of 5 dBis suggested [11]. This total dynamic range of about 87 dBs can be achieved by a14-bit ADC.

The fastest ADCs with 14 bit resolution that is reported has a sampling rate of125 MHz [3], but the Effective Number Of Bits (ENOB) is only about 12.7 at 62.5MHz. This ADC still has to increase the sampling frequency by a factor of 35, andto keep the SNDR at the full 14 bits up to 2.2 GHz. The design challenge is huge,and the processes are simply not ready for this kind of ADCs today.

What about Software Defined Radio, what is it, and is it more feasible today?

2.2.2 Software Defined Radio

The second vision for the future is SDR, where there is a single reconfigurable re-ceiver chain that consists of reconfigurable blocks, as shown in Figure 2.8. Theseblocks have software settings that control to which of the available communicationstandards the receiver should be adjusted. This is in contrast with the SR, whereany frequency could be freely selected. If a new standard is desired, the only mod-ification that has to be made is to download new software to the handset, whichdescribes how the receiver should be configured to receive this new standard.

Let us do the same calculation experiment for WCDMA ADC again. Now the sig-nal is mixed down to baseband, with a zero-IF receiver, and the required dynamicrange of the ADC in the last stage of the receiver can be about 10 bits [28, 91],with a sampling frequency of 10 MHz. Such converters exist today.

This implies that the concept of SDR is more feasible today from an ADC de-sign perspective. The ADC design challenges on the other hand occur as the ADCin this receiver needs to be reconfigured between many different standards.


LNA ADC

Multi-

Band

Generator

Baseband

processing

Digital control

Data out

Figure 2.8: SRD Zero IF receiver

A lot has been mentioned about wireless communication standards, and thus asummary of a few communication standards for handsets, without any intention ofbeing complete, is presented in the following section.

2.3 Wireless communication standards

There is a large variety of available wireless communication standards. A few ofthe relevant standards for handsets is given in Table 2.1, where a few parametersof the standards is presented [2, 22, 25, 26, 40, 41, 43, 44, 47, 59, 85]. There area number of abbreviations in the table, where some of them are associated withthe names of the standards, and some are the modulation schemes. A list of theabbreviations in the table is given below, where a reference is given to where moreinformation about the abbreviation can be found:

GSM Global Standard for Mobile communications [25].

WCDMA Wideband Code Division Multiple Access [26].

WLAN Wireless Local Area Network [40, 41, 43].

WiMAX Worldwide Interoperability for Microwave Access [44, 47].

UWB Ultra WideBand, defined by the WiMedia Alliance [22]

GFSK Gaussian Frequency Shift Keying [101].

GMSK Gaussian Minimum Shift Keying, used in GSM [25].

2.3. WIRELESS COMMUNICATION STANDARDS 23

Table 2.1: Wireless standards overview

Name Freq. Bands Data rate Modulation Channel(MHz) (MBPS) Sep. (MHz)

GSM 890-915 0.270 GMSK 0.2935-960

1710-17851805-1880

Bluetooth 2400-2480 2 GFSK 1WCDMA 1920-1980 3.84 QPSK 5

2110-2170WLAN 5150-5350 5.5 to 54 BPSK/OFDM 20802.11.a 5425-5675 QPSK/OFDM

5725-5875 16/64 QAM/OFDM

802.11.b 2400-2484 1 to 11 CCK 5

802.11.g 2400-2497 54 BPSK/OFDM 30QPSK/OFDM

WiMAX 2502-2625 1 to 25 QPSK/OFDMA 1.75 to 203500-3800 3 to 50 16 QAM/OFDMA 1.75 to 20

6 to 75 64 QAM/OFDMA 1.75 to 20UWB 3100-10600 53 to 200 QPSK/OFDM 528

320 to 480 DCM/OFDM

QPSK Quadrature Phase Shift Keying [101].

BPSK Binary Phase Shift Keying [101].

QAM Quadrature Amplitude Modulation [101], there are two variations mentionedin the table, 16 QAM and 64 QAM, where the number only indicates how manypoints there are in the communication constellation.

OFDM Orthogonal Frequency Division Multiplexing [43, 44].

OFDMA Orthogonal Frequency Division Multiple Access [44].

CCK Complementary Code Keying [41].


DCM Dual Carrier Modulation [22].

This selection of wireless communication standards presents only a few of the onesthat are related to wireless handsets. A more complete list can be found in [2],and to some extent in [59], where more details about some of these standards arepresenter.

A few of the wireless communication standards are now more familiar, but whatrequirements do these standards pose on the ADCs in the back end of the receiverchains?

2.4 Analog to Digital Converters for MultistandardReceivers

ADCs have been designed for Zero-IF receivers for these standards for a number ofyears. The specifications for these ADCs have been reported with large variationswhich depend on the variation of the full receiver chain for which they are intended.A selection of these specifications are summarized in Fig. 2.9 [28, 31, 32, 37, 74, 91,90, 110].

105

106

107

108

109

20

40

60

80

100

120

Wireless standard overview

Required Bandwidth (Hz)

Rep

ort

ed A

DC

DR

(dB

V)

GSM

BT

WCDMA

WLAN

WiMAX

UWB

Figure 2.9: ADC specifications overview for a Zero-IF receiver

These results are presented as a dynamic range-bandwidth figure, which is basedon a link budget analysis done as a foundation for the respective work. The spanof these standards is huge, from the 100 dB over 100 kHz for GSM, up to 30 dBover 528 MHz for UWB.

The ADCs that are built to meet the requirements of two or more of these stan-dards, are called multistandard ADCs. The dynamic range-bandwidth informationpresented in Fig. 2.9 stems from papers that are discussing multistandard ADCs,

2.4. ANALOG TO DIGITAL CONVERTERS FOR MULTISTANDARD RECEIVERS25

and these ADCs cover the standards in the way presented in Fig. 2.10.

105

106

107

108

109

20

40

60

80

100

120

Wireless standard overview

Required Bandwidth (Hz)

Rep

ort

ed A

DC

DR

(dB

V)

GSM

BT WCDMA

WLAN

WiMAX

UWBVeldhoven03/Farahani04/Morgado07

Rusu06/Gerosa06

Gustafsson07

Rusu07

CDMA2000

Figure 2.10: ADC specifications overview for a Zero-IF receiver

There is a lot of work done in multistandard ADCs for wireless communication stan-dards, and the ADCs mentioned here are applying reconfigurability to cover manystandards. There are other ways to implement a multistandard ADC, but beforestepping into more details about multistandard ADCs and reconfigurable ADCs, agood background of ADCs is needed. The next chapter presents an overview of theanalog to digital conversion, and moving on to ADC architectures, and ending upwith multistandard ADCs.

Chapter 3

Analog to Digital Converters: Overview

3.1 ADC fundamentals

This chapter discusses the fundamentals of the analog to digital conversion andADC architectures in detail.

The purpose of an analog to digital conversion is to translate a signal that iscontinuous in time and amplitude to a signal that is discrete in time and amplitude.This translation is done in two steps, the time translation which is called sampling,and the amplitude translation which is called quantization. Both of these transla-tions have to be done in a proper way, in order not to loose important information inthe process. Measures of these two translations are the most central to characterizean ADC. The time resolution is given by the sampling rate, and the amplitude res-olution is given by the number of levels that the digital representation of the signalhas. This digital representation can be done in many ways, e.g. binary codes, graycodes, binary-coded-decimal, 2’s complement, etc. [42].

The maximum range of the analog input signal to an ADC is called the full scalevoltage, and this range is usually divided into 2N intervals, where N is the numberof bits of the ADC. The size of each interval is Q Volt, which also is known as thequantization step, and is given by

Q =VFS

2N, (3.1)

where VFS is the full scale voltage, and N is the ADC resolution in bits.

3.1.1 Sampling

The process of translating a continuous-time signal into a discrete-time signal iscalled sampling. A signal continuous in time (and amplitude) is shown in Fig. 3.1,where a signal from an Electro Cardio Graph (ECG) is shown in the time- andfrequency- domains.

27

28 CHAPTER 3. ANALOG TO DIGITAL CONVERTERS: OVERVIEW

P

R

T

Amp (V)

Time (sec)

Frequency (Hz)

Power (V2)

0

Figure 3.1: A continuous-time and continuous-amplitude ECG signal

When this signal is sampled, some information is lost, since the signal is no longerrepresented by a value at every instance of time. The amount of information that islost depends on the selection of the sampling frequency, in relation to the frequencycontent of the sampled signal. The sampling process can only accurately process in-formation that is up to half of the sampling frequency, called the Nyquist frequency(fs/2). If there is frequency content in the signal that is higher than the Nyquistfrequency it should be filtered out with a low-pass filter (called anti-aliasing filter),in order to avoid folding (or aliasing) of the signal. This folding can also in somecases be desired, e.g. in sub-sampling systems.

The same ECG signal is now sampled at an appropriate rate, to ensure that all therelevant power in the spectrum falls well below the Nyquist frequency. The resultin time and frequency domains are shown in Fig. 3.2, where it can be seen thatthe signal changes, especially in the frequency domain. The frequency spectrumcontain the desired signal, and copies of the signal at the frequencies 1/T, -1/T,2/T, -2/T a.s.o.

3.1.2 Quantization

Quantization is the translation of an continuous-amplitude signal to an discrete-amplitude signal. This discrete-amplitude signal can easily be represented digitally.The ECG signal in both Fig. 3.1, and 3.2 are continuous-amplitude signals. Sincea digital representation of a signal consists of discrete steps, the range of interest

3.1. ADC FUNDAMENTALS 29

P

R

T

Amp (V)

Time (sec)T 2T 3T ...

Frequency (Hz)

Power (V2)

0 1/T 2/T-1/T-2/T

Figure 3.2: A discrete-time and continuous-amplitude ECG signal

is divided into sections, where each section is associated with a number, as shownin Fig. 3.3. The quantization also introduces errors or noise in the frequency do-main, since a range of continuous-amplitude inputs are represented by the samediscrete-amplitude value. This noise can be assumed to be white [86], that is witha uniform power per Hz, over the whole band of interest.

When this continuous-time discrete-amplitude signal is sampled, the quantiza-tion noise folds into the sampled signal band, since it is not limited to the Nyquistfrequency, keeping the same integrated power. This is illustrated for the ECG sig-nal in Fig. 3.4, where it can be seen that spectral copies of the sampled input signaloccurs at multiples of the sampling frequency, e.g. at 1/T, 2/T, and so on. At thispoint the signal can be represented by a sequence of numbers, e.g. for this binarycode [ 00112, 00112, 00112, 01002, 01002, ... ], and easily stored in a digital memory.

As it can be seen in Fig. 3.4 the signal is no longer the same as in the origi-nal in Fig. 3.1, as an effect of the time and amplitude discretization. In addition tothese effects, there are also errors that are introduced by the non-idealities of theADC. How accurate the final result is depends on the performance of this ADC.

3.1.3 ADC performance measures

The accuracy of the ADC, or the ADC performance can be measured in a numberof ways. The most important ways to characterize the ADC performance are bymeasurements of:


P

R

T

Amp (V)

Time (sec)

0001

0000

0010

0100

0011

0101

0111

0110

1000

Code #

Frequency (Hz)

Power (V2)

0

Noise floor due to

quantization

Figure 3.3: A continuous-time and discrete-amplitude ECG signal

P

R

T

Amp (V)

Time (sec)T 2T 3T ...

0001

0000

0010

0100

0011

0101

0111

0110

1000

Code #

Frequency (Hz)

Power (V2)

0 1/T 2/T-1/T-2/T

Increased noise

floor due to

sampling

Figure 3.4: A discrete-time and discrete-amplitude ECG signal

• Gain error

• Offset error

• Missing codes

• Differential Non-Linearity (DNL)

• Integral Non-Linearity (INL)


• Harmonic distortion

• Intermodulation distortion

These performance metrics can be divided into static and dynamic metrics, wherethe static ones are analyzed in the time domain, and the dynamic metrics are ana-lyzed in the frequency domain [42].

The static measurements are usually measured with either a sinusoidal or a rampinput, where the input voltage spans the full scale voltage of the ADC. A selectionof the static metrics are:

Gain error is evaluated by measuring the derivative of a curve formed from theLSB transition voltage to the MSB transition voltage. This derivative should ide-ally be unity, but a real implementation may have a non-unity value. This erroris called the gain error, and an ADC with a large gain error is illustrated in Fig. 3.5.

Offset error is evaluated as the difference between the ideal first transition step(Q0,ideal), and the real first transition step (Q0,real). There are two types of ADCs,the mid-step converters and the full-step converters. The ideal first step (Q0) shouldbe Q/2 for a mid-step converter, and Q in the full step converter. The offset erroris shown in Fig. 3.5 for a mid-step converter.

Missing codes are missing transitions in the transfer curve. This means thatthere is no analog input voltage that corresponds to one specific digital represen-tation. A missing code is shown in Fig. 3.5 for the ADC with the large gain error,where there is no analog input voltage that is associated to the digital code 1012.

Differential Non Linearity (DNL) is the error of the real step lengths Qk,real,and is given by

DNLk =Qk,real − Q

Q, (3.2)

where Qk,real is the real step length for code k, and Q is the average step length ofthe ADC [42]. The DNL of the ADC without gain error is shown in Fig. 3.5. TheDNL should be measured after the transfer curve is corrected for offset and gainerrors.

Integral Non Linearity (INL) is the integrated step length error comparedto the ideal case, and is given by

INLk =

m∑

k=0

(Qk,real − Q) , (3.3)

where INLk is the INL for the k:th code, Qk are the real code lengths for the step k,and Q is the average step length. The INL for the ADC without gain error is shown


in Fig. 3.5, where it can be seen that the INL in this case is a larger value than theDNL. INL can show linearity issues in the ADC, that in some cases can not be seenin the DNL measurement. The INL should be measured when the transfer curvehas been corrected for offset and gain errors.

000

Code #

111

110

101

100

011

010

001

INmax

Short step

Long step

Bin #1 2 3 4 5 86 7

INL (LSB)

1

-1

Bin #1 2 3 4 5 86 7

DNL (LSB)

1

-1

Offset

Missing

code

Gain error

Ideal

curve

Figure 3.5: Static ADC errors

The dynamic metrics in an ADC are determined with a one- or two-tone test, wherethe frequency of the sinusoidal input signal/signals have to fulfill the condition ofcoherent sampling [42]. A selection the dynamic metrics are:

Harmonic Distortion is when harmonic tones of the input signals appear overthe noise floor in a Power Spectral Density (PSD) plot. The harmonic frequenciesare integer multiplications of the fundamental frequency, e.g. 2fin, 3fin, a.s.o.

Intermodulation Distortion is when two tones are applied to the ADC as atest signal, and intermodulation products appear in the PSD plot. The magni-tude of these intermodulation products can, when compared to the fundamentalamplitudes be used to determine the linearity of a system [88], and also an ADC.Proper care has to be taken when the tones for the two-tone test are selected, sothat the frequency of the intermodulation tones do not coincide with harmonic or


other ADC distortion.

Spurious Distortion is other distortion that is not of harmonic or intermodula-tion character. This is most common in time interleaved ADCs, algorithmic ADCs,Successive Approximation Register (SAR) ADCs, and in Sigma Delta ADCs.

There are a number of errors that can occur when an analog to digital conver-sion is made, as shown in the list in this section. As a way to quantize how goodan ADC is there are a number of Figure of Merits (FOMs) that express how goodthe results were from the performance metrics above.

3.1.4 Figures of Merit

As one starts to look at ADC specifications, for instance in a ADC data sheet,not only the elementary specifications such as number of bits in resolution, andsampling rate are given, but a number of other specifications are common thatquantize how large the errors are in the performance metrics presented above. Alot of effort is spend in the development and deployment of a standardized methodto fully characterize an ADC [42], and a few of the static specifications are:

DNL, and INL are performance metrics, but they are also presented as FOMs,and they are usually given as a part of LSB.

Offset can be given in some cases.

The dynamic metrics are more numerous, which also results in more FOMs. Thedynamic performance is in the context of ADCs for multistandard wireless receiversmore relevant:

SQNR is the result of the measure of the Signal to Quantization Noise Ratio, andit is the upper theoretical limit for the dynamic performance of an ADC. Given thatthe input to an ADC is a full scale sinusoidal signal, the power Ps of this signal is

Ps =

(

Q·2N

2√

2

)2

, (3.4)

where Q is the quantization interval in Volt, and N is the number of bits of theADC. With this expression Q·2N is the full scale input voltage of the ADC. Thequantization noise power PQ have been found to be [45]

PQ =Q2

12, (3.5)


where Q is the quantization interval in Volt. Then the SQNR can be determinedas

SQNR = 10·log(

Ps

PQ

)

, (3.6)

which further can be simplified to

SQNR = 10·log(

Q2·22N ·12

Q2·8

)

, (3.7)

where N is the number of bits in the ADC. This can further simplified to

SQNR = 6.02·N + 1.76, (3.8)

which may be familiar to the reader. The SQNR is usually not presented in ADCspecifications.

SNR is the Signal to Noise Ratio. There is no standardized method to produce theSNR measurement, but it is in spite of this a common way to express the spectralpurity of the ADC.

SNDR/SINAD is the Signal to Noise and Distortion Ratio, which quantifieshow strong the input signal is in a PSD plot compared to everything else. Thestandardized way to measure SNDR/SINAD is presented in [42].

SFDR is the Spurious Free Dynamic Range, which quantifies the spectral distancein power between the input signal and largest interferer or distortion visible in thePSD plot, from a single-tone test of the ADC. There is a standardized method howthis distance should be measured [42]. This is usually presented as a figure in dBor dBc (decibels below carrier).

THD is the power of all of the harmonic distortion in the spectrum compared tothe signal power. The method to measure the THD is specified in the standard [42].

ENOB is the Effective Number Of Bits, which is defined from the SINAD of theADC for a number of conditions that have to be given when this figure is presented,e.g. input signal amplitude and frequency. The ENOB of an ADC is

ENOB =SINAD − 1.76

6.02, (3.9)

where SINAD is given in dB.

In addition to these FOMs, there is a wide variety of other definitions on howto quantify an ADC. Many of these do not only regard the static and dynamicperformance, but also put this in relation to the power consumption of the ADC.

3.2. FLASH ADCS 35

One worth mentioning was proposed by the Technical Program Committee of theIEEE Solid-State Circuits Conference in 1996,

EQ =P

2ENOB (2·fB), (3.10)

where EQ is the FOM in Joule per conversion step, P is the power dissipation,ENOB is the effective number of bits, and fB is the lower of either the effectiveresolution bandwidth or the Nyquist frequency. This may sound like a unified ex-pression for how good an ADC is, but there are a lot of things that are unknown,e.g. how much of the ADC is included in the power consumption measurement? Isthe digital Finite Impulse Response (FIR) filter, needed to process the Sigma Deltaoutput into a high-resolution signal included or not? This is why these FOMsshould be treated with caution.

This was a selection of the methods to characterize an ADC, and the FOMs thatare presented to quantify these measurements. The remainder of this chapter willintroduce different ways to implement the analog to digital conversion.

3.2 Flash ADCs

Flash, or direct conversion ADCs have been a popular selection for ADCs that re-quires high conversion speed and low resolution. The flash ADC use one comparatorfor each interval that is to be detected by the ADC. To do this, each comparator hasa reference voltage associated to it, in order to set the correct transition point. Fora 3 bit ADC, the full scale voltage is divided into 8 (2N) regions, and 7 comparators(2N -1) are needed to do this. The block diagram of a 3-bit flash ADC is shown inFig. 3.6, where a resistive ladder is used to generate the comparator references.

As the number of bits of a flash ADC increases, the number of intervals, thus thenumber of comparators increases exponentially, which also increase power consump-tion, area, and input capacitance exponentially. This becomes very problematic forhigh-speed flash ADCs. Folding of flash ADCs has been proposed as a techniqueto avoid this exponential increase [45, 109].

3.2.1 The folding technique

Folding is one way to reduce the number of comparators that are needed at theinput of the flash ADC. The principle is simply that each comparator is given manyreferences to compare the input signal to. This is illustrated for a folding factor of 2in Fig. 3.7, where it can be seen how the same reference ladder is used for the foldingflash ADC, but two references are connected to each comparator. This techniquereduces the number of comparators by a factor of two. If even more references areadded to each comparator, then the input capacitance can be reduced even further.


+

-R/2

+

-R

+

-R

+

-R

+

-R

+

-R

+

-R

+

-R

R/2

Vref Vin

Comparators

Bu

bb

le/M

issi

ng

co

de

corr

ecti

on

Th

erm

om

eter

to

Bin

ary

Dec

od

er

Over range

bit 0bit 1bit 2

Figure 3.6: A 3 bit flash ADC implemented with comparators and a resistive ladderreference

The folding is done in the two-input comparators, where the output is highwhen the first input exceeds it threshold voltage, and is pulled back low as theinput exceeds the second reference signal. On the right hand side of Fig. 3.7, the

3.2. FLASH ADCS 37

output of the four comparators are shown for an input signal that varies from 0 tothe full scale voltage. It can be seen how all of the comparator outputs initiallyrises, as the first threshold is exceeded. It can also be seen how they all graduallyreturn to zero after the second input threshold have been exceeded. The problemwith the output of these comparators, is that it cannot be used directly to mapto a binary code, since the state 00002 represents both the highest and the lowestvalue. This is why an extra bit of information is needed from either the first or thelast comparator, in order to map this code to e.g. a binary code.

R/2

R

R

R

R

R

R

R

R/2

Vref Vin

Comparators

Bubble

/Mis

sing c

ode

and f

old

ing c

orr

ecti

on

Ther

mom

eter

to B

inar

y D

ecoder

Over range

bit 0bit 1bit 2

+

-+

+

-+

+

-+

+

-+

1

2

3

4

5

6

7

8

1,5

2,6

3,7

4,8

Vo3

Vo2

Vo1

Vo4Vin

t

Vo2

t

Vo3

t

Vo1

t

Vo4

t

Figure 3.7: A 3 bit folding flash ADC, with only 4 two-input comparators.

The disadvantage of folding is the increased complexity of the comparators, whenthe additional reference voltage is needed. Folding has been used extensively toincrease the resolution of flash ADCs, e.g. in [80, 109]. Folding is however not the


only way to reduce the number of comparators, there is another technique calledinterpolation.

3.2.2 The interpolation technique

Interpolation is a second way to decrease the number of comparators in a flash ADC.The interpolation flash ADCs implements analog interpolation to produce higheraccuracy from a lower number of comparators. A 4-bit ADC with an interpolationfactor of 4 is shown in Fig. 3.8, where it can be seen that a resistor ladder is usedto interpolate the comparator outputs V1 and V2. The interpolated voltages V2a,V2b, and V2c are fed directly to latches.

The response of the interpolating network is shown in Fig. 3.9, where the origi-nal output signals V1 and V2 are shown with thick lines. The interpolated voltagesV2a, V2b, and V2c are shown with normal lines. These interpolated voltages addsthree additional zero-crossings, which are the input to low-accuracy comparators,which quantize the analog signal, at the threshold given in Fig. 3.9.

The design challenge of the interpolating ADCs is that the threshold voltages ofthe comparators and of the latches needs to be well defined in order to achievegood linearity in the ADC. Compensation may have to be done to the values ofthe resistors in the interpolation network to avoid non-linearity in the interpolation.

3.2.3 Implementation

The implementation complexity of the flash ADCs is low for the ADCs that do notimplement either folding or interpolation. As more things are done to reduce thenumber of comparators, the complexity increases. The output of a flash ADC isusually a thermometer code, which has to be translated into the desired outputcode, where the most common is the binary code. This is usually straight forwardwhen a flash ADC is to be implemented. A few of the other challenges in the designof a flash ADC are:

Input capacitance increases exponentially with the number of bits that are re-quired from the ADC. This does not only come from the exponential increase inthe number of comparators, but also from the offset requirements of the compara-tors. The offset that a comparator has typically depends on the matching that canbe achieved between the input transistors, but also on the process variation. Toget smaller offsets, larger devices are needed. This further increases the capacitiveinput. The input capacitance can be reduced with folding and interpolation tech-niques, as previously mentioned.

Resistor ladder feedthrough is the effect of non-zero resistance in the refer-ence resistor ladder. As a comparison is made, there is a small current injected into

3.2. FLASH ADCS 39

R

R

R

R

R

latch

latch

latch

latch

latch

latch

latch

latch

latch

latch

latch

latch

latch

latch

latch

latch

+

+

R

R

R

R

R

R

R

R

R

R

R

+

2

6

7

8

9

10

11

12

13

14

15

16

Dig

ital

lo

gic

Overflow

V2a

V2c

V2b

b0

b1

b2

b3

Vin

3

+

R

R

R

R

Vref = 1 V

V4

V3

V2

V1

LatchComparators

Input

Amplifiers

0.25 V

0.5 V

0.75 V

5

1

4

-

-

-

-

Figure 3.8: A 4-bit interpolating ADC with a 1-to-4 interpolation scheme

the resistor ladder, which changes the input voltages to all of the other compara-tors. This causes non-linearity in the ADC, and there are two approaches to solvethis issue. The first method is to decrease the resistance in the ladder to such alevel that it is no longer affected by these small currents. The second method is touse a capacitor array instead of resistors to create the reference voltages.


VFS

0.50.25 0.75 1.0

0

V1

V2a V2b

V1, V2, V2a, V2b, V2c

Vin

V2c

V2

Latch thresold

0

V

Figure 3.9: An illustration of interpolation in a flash ADC. Three new responsesare created with the use of this 1 to 4 interpolation, as shown in Fig. 3.8

Memory effect is when a comparator did not completely reset after a previouslylarge input signal, and a new small signal is applied. The old residue exceeds thenew input, and an erroneous result is created. The way to get around this is tomake sure that all the charge is removed from the inputs for all operating condi-tions. This is done by e.g. allowing sufficient time for the reset phase. This limitsthe speed of the flash ADC.

Sampling clock jitter and delay is an issue for high-speed, high-accuracy flashADCs. If the sampling clock is not distributed in an sufficiently accurate way, thetime slack that is created between the ends of the comparator array can be suffi-cient for the fast input signal to travel though several LSBs. Sampling clock jitter isanother phenomenon that has attracted attention in the design of ADCs [37, 104].Sampling clock jitter is when the edge of the clock signal arrive at a different time,than expected in an ideal case. Large and fast input signals may travel throughseveral LSBs during this clock edge arrival time deviation. There are a few waysto reduce this effect: take proper care in the design of the clock generation circuits,have a sufficiently accurate clock generator, and to use decoupling to reduce thesupply rail noise in the ADC.

Thermometer code bubbles is an error that can occur in flash ADCs. A bub-ble is created if a comparator in a flash ADC that is higher in the thermometerscale changes before a lower comparator does. This usually happens close to thetransition voltage between two intervals. This can be caused by noise, comparatoroffsets, comparator meta-stability etc. [45]. It can efficiently be removed with someadditional logic, called a bubble correction circuit. The input to the bubble correc-

3.3. SIGMA DELTA ADCS 41

tion circuit is the comparator thermometer code, and the output is a “one-cold”code. This code is the opposite of the “one-hot” code, where only one bit is highat one instance of time [102].

Comparator kick-back is when the comparator strobe or output signals are fedback to the comparator inputs. This can cause resistor ladder feedthrough, and itcan also create noise on the input terminals. This effect is usually limited by theuse of multiple stages in the comparator.

Comparator offset is the origin of code bubbles or non-linearity of the flashADC. This can for poorly designed comparators lead to missing codes, and otherADC non-linearities. The comparator offsets can be reduced by either increasingthe size of the transistors in the comparator, to reduce the offsets, or the use ofpre-amplifiers to amplify the input signal.

These were some of the implementation issues in flash ADCs. What about de-velopment trends in flash ADCs?

3.2.4 Trends

Flash ADCs have been the choice when a high-speed low resolution ADC was tobe designed. They have previously been proven useful up to moderate accuracy,where a 12-bit folding and interpolating ADC has been demonstrated [112]. Theflash ADCs have also been pushed up in speed, where a 4 GHz sampling frequencyis reported as the fastest flash ADC [83].

Interpolation with the use of capacitors in a pipelined way was suggested in [54],and has been implemented recently for high-speed flash ADCs for UWB applica-tions [37, 89, 93]. These capacitive interpolation flash ADCs require interpolatingamplifier, which can be a challenge in the implementation. These amplifiers havethe most of the ADCs non-idealities associated to them.

Flash ADCs are appropriate for low-resolution high-speed ADCs. What aboutthe other extreme, low-speed high-resolution ADCs?

3.3 Sigma Delta ADCs

Sigma Delta (Σ∆) ADCs are popular for implementations in many areas, and withthe new Continuous Time (CT) topologies, they are also gaining ground from thepipelined ADCs for high-speed, medium-resolution applications. The Σ∆ ADCuses two methods to increase the SINAD over a band of interest: oversampling andnoise shaping.


3.3.1 Oversampling

The first signal processing technique that the Σ∆ ADCs implement is oversampling.The simple and fundamental concept is that the quantization noise is spread outover a larger frequency band, in order to reduce the in-band power of the quanti-zation noise, and thus to improve the SNR in the band of interest. The concept ofoversampling is shown in Fig. 3.10 for a low-pass case. Here it can be seen how thenoise spectral density power reduces from A1 to A2 when sampled at two differentsampling frequencies, fs1 and fs2.

A1

f (Hz)

A2=A1/OSR

fs/2 fs/2

Power (V2)

fbw

fbwf (Hz)

fbw

Power (V2)

fs1 = 2.fbw

fs2 = 2.OSR.fbw

Figure 3.10: The concept of oversampling

In order to quantify how much improvement that is made, some mathematics arerequired. Given that the input to the ADC is a full scale sinusoidal signal, thepower Ps of this signal is given by Equation (3.4). The quantization noise powerfor an oversampled signal PQ has been found to:

PQ =Q2

12·OSR, (3.11)

where Q is the quantization step in Volt, and OSR is the oversampling ratio [45].The SQNR can be determined to

SQNR = 10·log(

Ps

PQ

)

, (3.12)


which can be simplified to

SQNR = 10·log(

Q2·22N ·12

Q2·8

)

− 10·log (1/OSR) , (3.13)

where N is the number of bits in the ADC. This can further simplified to

SQNR = 6.02·N + 1.76 + 10·log (OSR) , (3.14)

which is the SQNR for the Nyquist ADC, shown in Equation (3.8), plus the loga-rithmic term.

This improvement in SQNR has limited influence. The effective increase in SQNRfor a doubled sampling ratio (OSR = 2) is only 3 dB. Since the signal now is sam-pled at a higher rate, decimation or down sampling have to be done to recreate thesignal afterwards. The second technique Σ∆ ADCs utilize to further improve theSINAD in the band of interest is noise shaping.

3.3.2 Noise shaping

Noise shaping allows Σ∆ ADCs to achieve high SQNR over a band of interest. Thequantizer is the contributor of the quantization noise, and the trick is to filter thisnoise out of the signal band, and at the same time let the signal pass through thefilter without attenuation. For the low-pass case, the quantization noise is high-passfiltered. This technique is implemented with the use of negative feedback. Given afirst order oversampling Σ∆ modulator, which is shown in Fig. 3.11 a). It can be

H1(z)+X(z) Y(z)

H1(z)+

E(z)

Y(z)

Quantizer

+X(z)

a)

b)

-

-

Figure 3.11: A first order Σ∆ modulator, shown with quantizer in a) and withquantizer as a noise representation in b)


seen from the figure that the quantization noise enters the system from a differentport than the signal. The Signal Transfer Function (STF) is given by

STF =Y (z)

X(z)=

H1(z)

1 + H1(z), (3.15)

where X(z) is the input signal, Y(z) is the output signal, and H1(z) is the loop filtertransfer function. For a delaying loop filter, with the transfer function H1(z) =z−1/(1 − z−1), will give a STF of

STF =z−1

1−z−1

1 + z−1

1−z−1

=z−1

1 − z−1 + z−1= z−1, (3.16)

which is only a delay.

The Noise Transfer Function (NTF) is on the other hand given for the same system,shown in Fig. 3.11 b) by

NTF =Y (z)

E(z)=

1

1 + H1(z)=

1

1 + z−1

1−z−1

= 1 − z−1, (3.17)

which is a first order high-pass filter. Thus the signal is delayed, and the quantiza-tion noise is high-pass filtered. The magnitude of the quantization noise dependson the quantization step.

Now the loop filter H1(z) do not need to be of the delaying kind, it can also benon-delaying. Then several of these filters may be cascaded, to create a higherorder filter. If the filter is of higher order, the NTF will also be of higher order.This is illustrated for only oversampling and noise shaping up to the fourth orderin Fig. 3.12, where it can be seen that the noise in the signal band, up to 100 Hz issignificantly attenuated for higher order noise shaping.

102

103

-120

-80

-40

0

40

Frequency (Hz)

Nois

e A

mpli

tude

(dB

V)

Only oversampling

First order shaping

Second order shaping

Forth order shaping

Third order shaping

Figure 3.12: The noise shaping in different order of Σ∆ modulators

One of the interesting properties of this noise is the in-band noise power, and the


in-band SQNR. This depends, as can be understood from Fig. 3.12 on the order ofthe noise shaping, but also from the amount of noise that is shaped. This impliesthat there is another degree of freedom, and that is the quantizer resolution. Thegeneral expression for the in-band SQNR is given by

SNQR ≈ 10·log(

3

2·(

2 · L + 1

π2·L

)

· M2·L+1 · 22N

)

, (3.18)

where L is the loop filter order, M is the oversampling ratio, and N is the quantizerresolution [103]. The equation can be simplified to

SNQR ≈ 6.02N + 1.76 + 10log (2L + 1) − 9.94L + 10 (2L + 1) log (M) . (3.19)

This helps to establish the fundamental limits for an oversampled Σ∆ ADC. TheSQNR for different modulators are shown in Fig. 3.13, where it can be seen how theSQNR relates to the loop order, and quantizer resolution from 1 to 4 bits. It canbe seen that there are a number of combinations of modulator order, oversamplingratio, and number of bits in the quantizer, that can be used to achieve one desiredSQNR.

10 20 30 40 50 60 700

20

40

60

80

100

120

140

OSR

SQ

NR

(dB

)

First order Loop filter

Second order Loop filter

Third order Loop filter

Fourth order Loop filter

N1=1

N1=4

N4=1N4=4

N3=1

N3=4

N2=1

N2=4

Figure 3.13: The SQNR for different quantizer resolutions and loop order versusOSR

Let us return back to the block level again, and look at different architectures ofthe high loop order Σ∆ modulators.

3.3.3 Architectures

The number of ways that a higher order Σ∆ ADC can be implemented at blocklevel is very large.


Feedback is the central method that is used to create the noise shaping. Feedbackcan also be implemented in a number of ways in high loop order Σ∆ modulators.The simple example is given in Fig. 3.11, with the first order loop filter, where azero was placed at origin for the NTF and one pole was placed for the STF atthe origin. For a second or higher order modulator, these poles and zeroes canbe placed at any location, naturally with the limitations of the implementation.The position of these poles and zeroes can be moved by the use of coefficients.To provide one example, these coefficients will be selected for a second order Σ∆modulator, where the zeroes of the NTF, and the poles of the STF are placed atthe origin. The modulator is shown in Fig. 3.14, where the loop filters H1(z) andH2(z) have multiplication coefficients b1 and b2, respectively.

H1(z)

ADC

DAC

X(z)b1 b2

1

H2(z)-

Y(z)

-

Figure 3.14: A second order feedback Σ∆ modulator block diagram

This Σ∆ modulator has the STF

STF =H1(z)H2(z)b1b2

H1(z)H2(z)b1b2 + H2(z)b2 + 1. (3.20)

If the transfer functions H1(z) and H2(z) are implemented as delaying integrators,with the transfer function

H1(z) = H2(z) =z−1

1 − z−1, (3.21)

then the coefficients b1 and b2 can be found to be 0.5 and 2 respectively, to achievea STF=z−2. The NTF for this Σ∆ modulator is given by

NTF =1

H1(z)H2(z)b1b2 + H2(z)b2 + 1=

(

1 − z−1)2

, (3.22)

which provides second order high-pass filtering. This concept of feedback can beapplied for even higher orders of modulators, and it is important to consider thatthe second order modulator is only conditionally stable. For the modulators of or-der 3 and above, special consideration have to be spent to investigate the stability,even for coefficient variations due to process mismatches.

Feedforward is a technique that can increase the linearity of Σ∆ modulators,and it was demonstrated in [100]. A block diagram of a second order feedforward


modulator is shown in Fig. 3.15. Here the coefficients a1, a2, b1, and b2 can beselected to achieve the desired pole and zero locations for the STF and NTF, re-spectively.

H1(z)

ADC

DAC

X(z)b1 b2

1

H2(z)-

Y(z)

a2

a1

Figure 3.15: A second order feedforward Σ∆ modulator block diagram

The advantage of the feedforward architecture is that the input signal amplitudeof the loop filters are significantly reduced, since only the quantization noise is pro-cessed, and not the signal. A histogram plot where the input signal of the firstloopfilter is compared between the feedforward architecture, and the second ordermodulator, is shown in Fig. 3.16, for a two-tone input test signal. It can be seenhow the input signal is only a fifth in the feedforward case, which significantly re-duces the requirements for the first loopfilter.

-1 -0.6 -0.2 0 0.2 0.6 10

40

80

120

b)

Amplitude (V)

Num

ber

of

occ

ura

nci

es

-0.2 -0.1 0 0.1 0.2

0

20

40

60

80

a)

Amplitude (V)

Num

ber

of

occ

ura

nci

es

Figure 3.16: Input signal histogram comparison for a feedforward modulator in a)and a feedback modulator in b)

The two examples presented in the feedback and feedforward section this far areboth second order modulators. For higher order modulators, the modulator stabil-ity is also a concern, as briefly mentioned above. But there are tricks to achievehigher order modulators without the concern of stability, and one of these tech-niques is called Multi StAge Noise Shaping (MASH).


MASH Σ∆ modulators were proposed to achieve higher order noise shaping, with-out the risk of instability [38, 68]. The MASH architecture is built by cascadingmultiple Σ∆ modulators, in order to achieve the correct transfer function. This isconceptually shown in Fig. 3.17 for a 2-1 MASH architecture.

H1(z)X(z)b1 b2

1

H2(z)-

Y1(z) = z-2X(z) + (1-z-1)2E1(z)

-

H3(z)+

Y2(z) = z-1E1(z) + (1-z-1)E2(z)

Quantizer

Quantizer

-

-

z-1

z-1 z-1

(1-z-1) (1-z-1)

X2(z)=E1(z)

Y4(z) = z-1(1-z-1)2E1(z) + (1-z-1)3E2(z)

Y3(z) = z-3X(z) + z-1(1-z-1)2E1(z)

-Y(z) = z-3X(z) - (1-z-1)3E2(z)

Figure 3.17: The 2-1 MASH architecture

The idea is that the quantization noise from the first modulator is passed to thesecond modulator, and the output of the two modulators are combined in such away that the quantization noise from the first modulator is cancelled. This is shownwith equations in Fig. 3.17, where the E1 components of Y3 and Y4 cancel eachother in the digital domain. The difficult challenge in this topology is to make thissubtraction of the quantization noise in an efficient way, since it requires a matchingof the delays in a digital output from the first modulator, to the delay of the analogsignal through the second modulator [97]. This is why the first modulator usuallyis chosen to be of second order, to reduce the effect of this non-ideal subtraction [97].

Bandpass Σ∆ modulators are not conceptually different from the low-pass ar-chitecture that has been implicit in the modulator types explained above. Thebandpass modulators have a non-origin placing of the zeros of the NTF, thus creat-ing a low-noise band at a non-zero frequency, but requires as bandpass filters twicethe filter order compared to the low-pass or high-pass filters. More informationabout bandpass Σ∆ ADC can be found in e.g. [45]

These were some of the fundamental Σ∆ modulator architectures, but how arethese modulators implemented?


3.3.4 Implementations

There are two types of implementations for Σ∆ modulators, discrete time, andcontinuous time. The first method, which has been implicit in the section on archi-tectures above, is the discrete time implementation. The notation H1(z) is used toindicate that this is a discrete time implementation. How are these filters imple-mented in more detail?

Discrete time filters are usually implemented with the SC technique. This hashistorically been the most common way to realize discrete time filters for Σ∆ mod-ulators. This is well described in the literature, in e.g. [45], and shown for asingle-ended delaying first order loop filter in Fig. 3.18, where the loop filter isshown for three different levels of abstraction. The input and the DAC voltage aresampled during phase p1, and connected to the integrator during phase p2.

There are a number of implementation issues of this loop filter, where the centrallimitations are associated to the amplifier non-idealities, such as the limited DCgain, the limited bandwidth, the offset, the output swing limitation, and linearityover the input signal range. All of these make the amplifier, the amplifier settling,and accuracy of this settling the bottleneck of discrete time Σ∆ ADCs. One wayto get around this is to remove all these settling phases in the filters, which can bedone with a Continuous Time (CT) loop filter implementation.

Continuous time filters is a second approach to design Σ∆ modulators. Most ofthe NTF and STF analysis remains the same, but is moved from the z-domain intothe s-domain. The sampling, which in the discrete time modulators is done at theinput to the first loop filter is now moved after the last loop filter. This concept isillustrated for a second order modulator in Fig. 3.19, where it can be seen that theloop filters now have a continuous time representation, and the input signal is alsoa continuous time signal.

Implementation issues that arise in the CT modulators are the passive componentsthat are needed to realize the filter functions. These do not have good accuracywhen implemented in a standard CMOS process and limit the accuracy of the fil-ters. A second important limitation is the timing jitter constraints on the clockthat is driving the sample and hold. In the SC modulators, the DAC responseneeds to arrive before the DAC output voltage should be used. In CT modulators,the arrival time of this DAC voltage is central, since the integrators continuouslyintegrates the signal. If the DAC response is delayed (called excess loop delay),the wrong signal will be integrated in the meanwhile, which can cause large errors.These errors are not suppressed by the feedback loop, and they are directly addedto the input signal. A more elaborated description of the impact of jitter in CTΣ∆ ADCs can be found in e.g. [78, 110].


H1(z)+X(z)

Quantizer

-Y(z)

Y(z)

X(z)

+

-

C

CC

z-1

H1(z)

+-

X(z)

Y(z)

Block diagram

Detailed block diagram

Switched Capacitor

implementation

p1

p2 p1

p2

p1

p2

Figure 3.18: The steps in a discrete time SC delaying integrator

H1(s)

ADC

DAC

X(s)b1 b2

1

H2(s)-

Y(z)

-S/H

CLK1

Figure 3.19: A block diagram of a second order continuous time feedback modulator

Filtering of the output signal is also an issue that in many cases is overlookedfor Σ∆ ADCs. The digital output that comes from the ADC is not near the largeSQNR signal that is sought for, and it may require very large digital filters, and


down sampling before the desired signal can be reconstructed. This is especiallycritical for the higher order modulators where the noise increases fast outside of thepassband.

DAC nonlinearity is a concern for most mulit-bit Σ∆ ADCs, since small pro-cess variations in the DAC implementation can result in a loss of the high SQNR,as these non-linearities are not filtered by the feedback loop.

These are some of the implementation approaches and issues for Σ∆ modulatorADCs. What are some of the recent trends for Σ∆ ADCs?

3.3.5 Trends

For many years Σ∆ ADCs were and still are the most simple and straight-forwardway to achieve a high SQNR in an ADC, without the need of external high-precisioncomponents or expensive on-chip trimming. This is why a lot of interest has beendirected into the development of this ADC architecture. A few modern Σ∆ ADCtrends are:

CT deployment attract a lot of research and scientific contributions, e.g. onhow to accommodate the limitations of sampling time jitter, which is one factorthat limits the deployment. An advantage that currently is exploited is that theloop filter in CT Σ∆ ADC also can be used as an anti-aliasing filter, or as a chan-nel select filter in the receiver chain [82]. This is not possible in discrete time Σ∆modulators, since the sampling is made before the filtering.

Bandpass is a recent trend that appeared, in the context of IF sampling of RFsignals. If a CT bandpass Σ∆ modulator is implemented, then the loop filters canbe used to provide channel selection and image rejection in a quadrature radio re-ceiver, which would remove the need for an extra complex filter [82].

Reconfigurability is not really a new concept for Σ∆ ADCs, since there is aninherent trade between SQNR and OSR. The trend is that additional electronicsare used to sense, within the frame of the application, how much SINAD is neededfor the ADC at a given time, and the performance of the ADC is adjusted, whichallows a more intelligent use of the power spent in the ADC [65].

Now the high-speed, low-resolution and low-speed, high-resolution ADCs have beencovered. What about medium-speed medium-resolution ADCs? There are threearchitectures that can fit this description, pipelined ADCs, algorithmic ADCs, andSAR ADCs.


3.4 Pipelined ADCs

The pipelined ADC (pipeline) was introduced to reduce the size of flash ADCs.The first step towards pipelined ADCs was the sub-ranging or two-step ADCs, thatquantized the bits in two steps, starting with the MSBs, and finishing with theLSBs [45]. The pipelined ADC is built on the same concept, but it expands this bythe use of several sub-ranging converters, or stages with a few bits of resolution. Ageneral block diagram of a pipelined ADC is shown in Fig. 3.20, where it can beseen that each stage has Ni bit resolution. These bits are fed to a digital block thatcombines the outputs of all the stages to a final result with the resolution N bits.

Stage 1 ...Stage 2

Digital correction / Digital calibration / Switch control

Stage MVin

N bits

N1 bits

Vres

N2 bits NM bits

Figure 3.20: A block diagram of a pipelined ADC

A sample is made by the first stage in every clock cycle, and subsequently passeddown the pipeline before the next clock cycle, in order to allow a new sample to bemade. In this way, a latency or a slack, is introduced into the conversion, but thethroughput is kept high. A few bits of memory are required, in order to create theoutput word in a correct way.

The stages of the pipelined ADC are shown in Fig. 3.21, where the residue ofthe i:th stage Vres,i is found as

Vres,i = Gi · (Vres,i−1 − VDAC,i) , (3.23)

where Gi is the gain of the i:th stage, Vres,i−1 is the input residue to the i:th stage,and VDAC,i is the DAC response to the Vres,i−1 input. To perform this operation,there are four operations that takes place:

1. Sample input signal (Vres,i−1 or Vin)

2. Hold input signal and determine the ADC and DAC results (VDAC,i)

3. Subtract DAC voltage from input signal and multiply residue with Gi

4. Hold amplified residue

3.4. PIPELINED ADCS 53

+

ADC DAC

Gi-

N bits

Vin S/HVout

Vref

Figure 3.21: A block diagram of a pipelined stage

The overall operation of the pipelined ADC is to find a set of reference voltagesthat match the input voltage, in such a way that the difference is zero. The pro-cessing gain in the stages makes this process easier, since it removes the need forvery small reference steps. This process is explained for a 1-bit 4-stage pipelinedADC in a graphical way in Fig. 3.22, where it can be seen how one input signal isgradually processed through the 4 stages.

Stage 4

comparator

threshold

Stage 3Stage 1

1

0

Stage 2

Input

data

11

10

101

100

1001

1000

Figure 3.22: The processing of an input signal in a 4-stage, 1 bit per stage pipelinedADC

In the first stage, the input data is above the comparator threshold, which resultsin a negative reference voltage from the DAC. The new residue is multiplied, andsampled by the next stage. Now the first residue is below the comparator threshold,which results in a positive reference voltage from the DAC. The second residue iscreated with the multiplication of the first residue plus the DAC reference. The sec-ond residue is now sampled by the third stage. The second residue is found againto be below the threshold of the third comparator, and a positive DAC voltageis created, and added and multiplied with the second residue, to create the thirdresidue. This third residue is sampled by the last stage, and it is found to be above


the comparator threshold voltage. In this last stage, no new residue is needed forfurther processing, and the output data is ready.

The result from Fig. 3.22 came out to be 1001. With a careful look at the in-put signal, with the magnified input scale shown in Fig. 3.23, it can see that thesame result 1001 can be observed when the quantization intervals get a digital valueassociated to them.

Input

data

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Figure 3.23: A magnified image of the input from the 4-stage, 1-bit pipelined ADC,with the associated digital values for the 4-bit conversion

The general function of the pipeline is now clear. What about the implementation,and the implementation issues of pipelined ADCs?


The pipeline stage or stages are the central parts of the pipelined ADC. A SwitchedCapacitor (SC) implementation of a pipelined stage is shown in Fig. 3.24, where itcan be seen that four clocks are used to drive the stage. These clocks are numberedaccording to the number of the phases of the operation:

1. Sample input signal

2. Determine the ADC and DAC results

3. Subtract DAC voltage from input signal and multiply residue with Gi

3.4. PIPELINED ADCS 55


The SC implementation in Fig. 3.24 shows how the ADC is implemented as asingle comparator that decides whether the input signal is above or below the com-parator reference value. The output from the ADC controls the DAC during thesecond phase, and a reference voltage is set, which is held during phases 2 and 3.If the Vres,i−1 is smaller than the reference Vcomp, a positive DAC voltage shouldbe applied to the multiplier, and vice versa.

VDAC,i

Vres,i-1

+

-

CGiCp1

p1

p1

p3

p3

+

-comp

Vref- Vref+

D

D=0 D=1

p1

Strobe @ p2

ADC DAC

-Vres,ip4

Vcomp

Figure 3.24: A SC implementation of a 1-bit pipeline stage

Other blocks that also need to be implemented are:

Clock generation circuit is needed to generate the four clocks necessary in theoperation of the pipeline stage. To make the design of these clocks efficient, only onenon-overlapping clock generation circuit is used, that creates two non-overlappingclocks, p1 and p3. The clock p2 is the inverse of p1, and p4 is the inverse of p3.To make the pipeline more efficient, the clocks p1 and p3 to the first stage (andsubsequent odd stages) are reused as clocks p3 and p1 respectively for the secondstage (and subsequent even stages). This allows only one master clock to be usedto generate all the needed clock phases for the pipeline.

Real ADCs/DACs are usually not implemented with only 1 bit. More com-mon implementations have a redundancy, to allow for errors to be corrected withthe use of digital processing [60], apart from the last stage. With this redundancy


added, the 1-bit ADC is called a 1.5 bit ADC and DAC, and it has one comparisonlevel less than the 2-bit ADC. This specific choice of number of levels in combina-tion with the selected gain in the SC amplifier assures that the signals do not gooutside of the range of the SC amplifier [13].

Digital correction can be done to the ADC outputs, if redundancy is addedin the processing. This allows comparator offsets to be corrected, and one methodto do this is presented in [60].

There are also a few techniques that are common in the design of pipelined ADCs:

Amplifier down-scaling is a technique that is implemented in pipeline ADCs.This is feasible due to the processing gain in the chain, which allows higher errorsto be tolerated. One source of these errors is the incomplete settling of the ampli-fiers during the hold phase. This technique was suggested in [60].

Sampling capacitor down scaling can also be applied, due to the processinggain. Since the input signal is amplified in the stages, the kT/C noise is allowedto increase, which allows smaller sampling capacitors to be used. This allows theamplifiers can be scaled down even further [13].

Resolution per stage selection needs to be done. The trade-offs that are in-volved when this is done is the area, the power consumption, the design effort, andwhether the stage and capacitance down scaling is used.

Calibration is needed for high-resolution pipelined ADCs, and there are severaltechniques to do this. The amplifier is the main block that needs calibration, alongwith the capacitors needed to implement the gain in the stage. The matching isusually sufficient for 11 to 12 bits of resolution [113]. When higher resolutions aredesired a calibration scheme is needed, which can be implemented as self-calibration,e.g. [56], or with trimming.

These are some of the implementation issues in pipelines. What is the focus ofthe present effort in pipelined ADCs?

3.4.2 Trends

There is still a lot of ongoing development in the design of pipelined ADCs. A fewof the areas where there is development are:

Self calibration of pipelines, where the calibration is used to achieve higher res-olution, e.g. 12 bits and above. These calibration algorithms are usually done inthe background, e.g. in [63], and in the digital domain.

3.5. ALGORITHMIC ADCS 57

High accuracy on-chip passives are also used in some cases, and calibrationcan be avoided completely, and accuracies up to 14 bits has been achieved [57, 118].

Nanometer technology is also creating new challenges for high accuracy inpipelines. One small pipelined ADC in a 90 nm CMOS technology has recentlybeen proposed for Flat Panel Displays [58].

Time interleaving is a hot topic in pipelined ADCs, in order to get higher per-formance. This will be covered and explained further in Section 3.7.

The second ADC architecture that fit the medium-speed, medium-resolution wasthe algorithmic ADC. The next section discuss this architecture in more detail.

3.5 Algorithmic ADCs

Algorithmic ADCs can be traced back to the 1960’s, when the first implementationscame [62]. The converters are also known as cyclic ADCs, but for the remainder ofthe thesis they will be called algorithmic ADCs. The integrated algorithmic ADChas also been around for a very long time, and one early integrated algorithmicADC was presented at the ISSCC in February 1977 [70]. There is speculation thatthe pipelined ADCs were based on algorithmic ADCs [113]. The two converterarchitectures use the same concept of making a sub-ranging conversion, where thematching between the input voltage to a reference voltage is the goal.

The algorithmic ADC consists of only one pipeline stage, with or without the S/Hcircuit, which depends on the implementation, as discussed in Section 3.5.1. This,in contrast with the number of stages needed in the pipelined ADC, allows thealgorithmic ADCs to be a physically smaller solution. A block diagram of an algo-rithmic ADC is shown in Fig. 3.25, where the resemblance of the pipelined stagein Fig. 3.21 is evident. The number of bits from the stage is fixed, at N bits perconversion, and the number of cycles made in the loop determines the total resolu-tion, Ntot of the ADC. The gain of the stage is set to G.

A second difference between the algorithmic ADC and the pipelined ADC apartfrom the size, is the throughput. The pipelined ADC produces new data everyclock cycle, where-as the algorithmic ADC needs several cycles in the loop beforethe output data is produced. The algorithmic ADC does not suffer from the la-tency or slack of pipelined ADCs, but the clock frequency has to be higher thanthe sampling frequency. The operation of the algorithmic is the same as in thepipelined case. The residue of the i:th cycle Vres,i is found as

Vres,i = G · (Vres,i−1 − VDAC,i) , (3.24)


+

ADC DAC

G

-

N bits

Vin

Error correction

Digital control

Ntot bits

Clock generation

S/H

Figure 3.25: An algorithmic ADC block diagram

where G is the gain of the stage, Vres,i−1 is the input residue in the i:th cycle, andVDAC,i is the DAC response to the Vres,i−1 input. To perform this operation, thereare four steps that takes place:

1. Sample input signal (Vres,i−1 or Vin)

2. Hold input signal and determine the ADC and DAC results (VDAC,i)

3. Subtract DAC voltage from input signal and multiply residue with G, andsample the signal with the S/H


This describes the high-level operation of algorithmic ADCs, but what are theimplementation issues associated to this architecture?


Many of the algorithmic ADCs have been implemented with the SC technique, andan illustration of a single ended implementation is shown in Fig. 3.26, where itcan be seen that it is similar to the pipelined stage. The differences are an extrasample and hold circuit, the fixed gain G, and the two switches controlled by theclock signals psamp, and pcycle, which are closed during the sampling phase and theremaining phases respectively.

There are a few techniques that are commonly implemented in the design of algo-rithmic ADCs:

The double capacitor technique only requires one amplifier, instead of the twoneeded in Fig. 3.26. This technique substitutes capacitors C1 and G·C1 with thecapacitors C2 and G·C2 every other cycle, as shown in Fig. 3.27. The clock phases


VDAC,i

Vres,i-1

+

-

C1G.C1p1

p1

p1

p3

p3

+

-comp

Vref- Vref+

D

D=0 D=1

p1

Strobe @ p2

ADC DAC

-Vres,ip4

Vcomp

psamp

Vin

pcycle

+

-

C2 C2p1

p3

p3

p1

p1

Figure 3.26: A SC implementation of an algorithmic 1-bit ADC

are now substituted from being only four, to eight. The clocking scheme that passedfrom p1 to p4, and then restarting with p1 again, has now changed to start from p11

to p14, and then p21 to p24, before re-starting with p11. This increase in clockingcomplexity is one disadvantage of this implementation, but the digital logic neededto implement this is usually lower in power, compared to the S/H circuit needed forthe simpler clocking scheme. A second disadvantage is the matching that is neededbetween the two sets of capacitors [75].

Time scaling is when the later cycles of the conversion are made in shorter timecompared to the initial phases. This is possible due to the processing gain duringthe bit cycling. This gain allows larger settling errors of the amplifier during thehold phase. In pipelines, the stages could be scaled down, but since the same stageis reused in the algorithmic ADC, the same effect is created if less time is allocatedfor the amplifier settling. This technique is shown in Fig. 3.28, and was previouslyimplemented to increase the sampling rate of algorithmic ADCs [75].

The double capacitor sampling technique adds two capacitors to the circuit,and extra switching complexity. The idea is to use the full sampling period tosimultaneously sample and process the sample, instead of dividing this sampling


VDAC,i

Vres,i-1

+

-

C1G.C1p11

p11

p11

p13

p13

-Vres,ip14

G.C2

p13

p13

C2

p13

p13

a)

VDAC,i+1

Vres,i

+

-

C2G.C2p21

p21

p21

p23

p23

-Vres,i+1p24

G.C1

p23

p23

C1

p23

p23

b)

Figure 3.27: A SC implementation of the double capacitor technique in algorithmicADCs

...

t1 t1 t1 t1t2 t3 t4 t5

p11 p13 p21 p23 p11 p13 p21 p23

Figure 3.28: Timing diagram of algorithmic ADC operating with time scaling

period into a sampling time and a processing time. A block diagram of this tech-nique is shown in Fig. 3.29, where the capacitor set C1 and G·C1 is used duringthe processing of the first sample, when the capacitors C3 and G·C3 are trackingthe input signal with the switches ps1 closed. When the first sample is processedthrough all cycles, and the new processing should start, capacitors C3 and G·C3

are switched directly to the amplifier with the new sample stored on them. Thecapacitors C1 and G·C1 are connected to track the input signal, with the switchesps2. The operation of the capacitor sets C1 and C3 are also shown in Fig. 3.30,where four cycles are used to process the complete sample.


VDAC,i

Vres,i-1

+

-

C1G.C1p11

p11

p11

p13

p13

-Vres,ip14

G.C2

p13

p13

C2

p13

p13

a)

VDAC,j+1

Vres,j

+

-

C2G.C2p21

p21

p21

p23

p23

-Vres,j+1p24

G.C3

p23

p23

C3

p23

p23

b)

G.C3

ps1

ps1

C3

ps1

ps1

Vin ...

G.C1

ps2

ps2

C1

ps2

ps2

Vin ...

Figure 3.29: A SC implementation of the double capacitor and double samplingtechnique in algorithmic ADCs

t1 t1 t1 t1t2 t3 t4 t5

Sample

Cap set 1

Cap set 3

Sample ...

...

t1 t1t2

...

...

p21 p23

p11 p13 p21

p21 p23p11 p13 p11 p13

Figure 3.30: A simplified timing diagram for the sampling time maximization andtime scaling scheme

Calibration of algorithmic ADCs is easier than for pipelined ADCs, since there isonly one or two amplifiers that needs to be calibrated. But again the matching ofthe capacitors is more difficult to achieve, since there may be many sets of capaci-tors that need to match each other.


What are the trends in algorithmic ADCs?

3.5.2 Trends

The development of algorithmic ADCs is not that strong any longer, where theinterest is not continuing on in the same way as in pipelines or Σ∆. The areas ofdevelopment in algorithmic ADCs are:

Self calibration of the stage, where the calibration is used to achieve higherresolution, e.g. 12 bits and above. These calibration algorithms are usually donein the background, e.g. in [71], and in the digital domain.

Low supply voltage is also creating new challenges to achieve high accuracyin algorithmic ADCs. One implementation working on only 0.9 V in a 0.18 µmprocess have recently been presented [61].

The last and final ADC architecture that support medium speed, medium resolu-tion is the Successive Approximation Register ADCs. The following section discussthese in more detail.

3.6 Successive Approximation Register ADCs

Successive Approximation Register (SAR) ADCs have been attracting recent in-terest with their moderate conversion times and moderate complexity. The SARADCs implement a binary search algorithm to find a set of reference voltages thatin the most accurate way represent the analog input.

3.6.1 DAC based SAR

There are two popular ways to implement the SAR ADC, where one is a DACbased approach, where Vin is compared to Vref , which is binary searched. Theblock diagram of the DAC based SAR is show in Fig. 3.31, where the Sample andHold (S/H) circuit, the comparator, the SAR logic, and the DAC can be seen.

Vin

Vref

b1

b2

b3

b4 b

n

S/HSucessive Approximation Register

(SAR) and control logic

D/A Converter

+

-comp

Figure 3.31: A block diagram of a DAC based SAR ADC.

3.6. SUCCESSIVE APPROXIMATION REGISTER ADCS 63

The operation is simple, and it starts with the input signal Vin being sampled tothe S/H block. As this is done, the SAR logic set the MSB b1 high, creating areference voltage of Vref /2. In the second phase the input voltage is compared tothe DAC output voltage. If the result is larger than 0, then the next bit b2 is alsoset. If the result is smaller than 0, then the b1 is set to 0, and b2 is set. Next anew comparison is made, and the process is repeated until all the bits have beencompared to the input voltage.

3.6.2 Charge Redistribution SAR

The second popular approach is the Charge Redistribution SAR, where Vin ismodified instead of Vref in the binary search algorithm. This is done by addingand removing voltages, and comparing whether the added voltage is too large ortoo small. A block diagram of the charge redistribution SAR is shown in Fig. 3.32,where one comparator, a digital block and a capacitor array can be seen. Thedigital SAR block controls the switches b1 to bn, called bk. The operation of the

+

-

S2

Vin Vref

16C

b1 b

2b

n

8C C C

Capacitor

arrayS3

Suce

ssiv

e A

ppro

xim

atio

n R

egis

ter

(SA

R)

and c

ontr

ol

logic

b1

b2

bn

Vx

comp

Vb

Figure 3.32: A block diagram of a charge redistribution based SAR ADC.

charge redistribution SAR is mainly done in three phases:

1. Sample the input signal

2. Hold the input signal

3. Iterate the result with the binary search

In the first sample phase, the switches S1, and bk are connecting the input signalto the bottom plate of the capacitor array, and the switch S2 is closed. This makesthe comparator input Vx = 0. In the second phase, switch S1 connects the node Vb

to Vref instead of Vin, and all of the switches bk are connecting the bottom plates


of the capacitor array to the analog ground, and the switch S2 is opened to holdthe comparator value. This makes the comparator input Vx = -Vin. In the thirdphase, which is a repetition of operations, the switches bn are now gradually movedto the reference voltage, starting with b1. The input voltage to the comparatorVx = -Vin-Vref /2. If this is smaller than zero, which means that the input signalis larger than Vref /2, then the switch b1 is left in the closed position. If, on theother hand, the voltage Vx is larger than zero, then the switch b1 is again opened.This process is repeated for all of the remaining switches of bk, until the desiredresolution is achieved.

These sections described two possible architectures of SAR ADCs, and some ofthe implementation issues with these architectures are discussed below.


The central components of the SAR ADCs are the DACs and the comparators.The Sample and Hold block is also important for the DAC based SAR ADC. Theseblocks need to have sufficiently good performance in order to not compromise theresolution of the SAR ADC.

The comparator is the most central block, since its offset directly affects theresolution of the ADC. The smallest signals that efficiently can be processed are allabove the offset voltage of the comparator. This is why pre-amplification is used,some times in many stages to reduce the comparator offset [33]. The specificationsfor these pre-amplifiers can in some cases be strict, and these amplifiers can con-sume a significant part of the ADC total power, due to the bandwidth and slewrate requirements of the block.

The DAC needs to have sufficient linearity and sufficient matching in order tonot compromise the accuracy of the ADC. This can be a difficult challenge in acharge redistribution SAR, since the capacitors can vary significantly in size in ahigher resolution SAR.

The S/H or the sampling path in the charge redistribution SAR is also of greatimportance. As the operating frequency of SARs are pushed up in frequency, thesampling times have to be made shorter, to allow longer processing for the actualbit-cycling. But as this time gets shorter, the sampling accuracy is compromised,due to the bandwidth of the S/H and the sampling path respectively.

What are the recent trends in SAR ADCs?

3.7. TIME INTERLEAVING OF ADCS 65

3.6.4 Trends

There is a lot of ongoing work with this architecture, especially in time interleavingof simple SAR ADCs. This topic will be covered in Section 3.7. Other trends thathave helped the development of SARs are:

Self-timing of comparators removes the need for a high-frequency clock thatcontrols the comparator and the SAR logic. This implies that the comparator havea simple added functionality, which indicates to the SAR logic when the comparisonfinishes, and the SAR logic can move to the next bit in the bit-cycling phase [84].The concept is simple, and is based on the fact that the outputs of a differentialcomparator is not the same when it has resolved the input.

Now a wide range of ADCs have been covered, from high-speed, low-resolutionall the way down to low-speed, high-resolution. One trend that was mentionedpreviously in this chapter was time interleaving of ADCs. The next section willdiscuss this in detail.

3.7 Time interleaving of ADCs

There are a number of factors that limit the possible speed of ADCs, where thespeed of the IC processes is one dominating limitation. One technique that hasbeen proposed is to use parallel ADCs, and to clock them with a slight time dif-ference, in order to create a parallel ADC processing [9]. A block diagram of thetime interleaving concept is shown in Fig. 3.33, where it can be seen how the inputsignal x(t) is sampled at full speed at the frequency fs. The parallel ADCs aresampled at a part of the full sampling frequency, namely fs/n plus a phase delay,where n also is equal to the number of stages. The final block in Fig. 3.33 is thedigital combiner, that runs at the full clock frequency fs, and arranges the outputsof the n slices in the right order.

The specifications of the n ADCs, or slices can now be relaxed, due to the reducedsampling frequency. This has also been proven to be an efficient technique, andvery high sampling rates have been achieved for medium resolution ADCs with theuse of time interleaving of pipelined ADCs [105]. It has also been proven with theuse of time interleaving of SAR ADCs, to achieve very low power consumptions forhigh-speed wireless or Hard Disk Drive (HDD) applications [21, 33].

What about the implementation issues of time interleaved ADCs?


The implementation of time interleaved ADC architecture poses several circuit de-sign challenges, and the central ones are:


S/H

ADC

x(t)

fs

ADC

fs/n+p1

fs/n

ADC

fs/n+pn

...

...

N

N

N

Dig

ital

com

bin

erN

fs

Figure 3.33: A block diagram of time interleaved ADCs.

Sample and Hold design is something that is not straight-forward. This blockhas to track the signal at full speed, with full resolution. One example of such adesign is where the amplifier alone, needed in the track and hold circuit required28 mA (!) [50].

Clock generation is also a challenge. The clocks that are driving the slices needto be very accurate, and have a precise phase shift, to avoid tones to appear inthe output spectrum. For a time interleaved ADC with 4 slices, one example ofa clocking scheme is when the first slice is clocked with 90 degrees delay of theoriginal clock, the second with 180 degrees, the third with 270 degrees, and finallythe last with one clock cycle delay. All of the clocks, including the clock to the S/Hcircuit need to fulfill the ADC requirements for the highest tolerable jitter, also thephase shifted clocks to the slices. The phase shifted clocks can be generated withe.g. a Delay Locked Loop (DLL) [16].

Slice matching is the last of the central considerations in the time interleavedADC design. The slices do not only have to be clocked properly, the response ofthe slices have to be very similar, in order not to lose performance. Formulas for

3.8. MULTISTANDARD ADCS 67

how mismatches of the slices affect the overall ADC performance has been derivedpreviously [53].

Now the fundamentals of an analog to digital conversion, as well as the funda-mentals and implementation challenges of many ADC architectures have been pre-sented, and it is time to connect back to the applications of these ADCs.

3.8 Multistandard ADCs

The overall target for this thesis was the design of reconfigurable ADCs for wirelessapplications. The title implies that a certain design approach is preferred for mul-tistandard ADCs. Before stepping too deeply into the details of the reconfigurableADCs, a more general overview can be done to present the ways a multistandardADC can be designed in order to meet the required specifications, set by severalwireless communication standards, and to motivate why this certain design ap-proach is preferred.

3.8.1 Overpower ADC design

The first and initial approach that one can consider is the overpower ADC, thathas the highest dynamic range over the highest sampling rate set by the multiplestandards. The specifications for this type of ADC, to cover all the standardsshown in Fig. 2.9 would required 100 dBs, or 14 bits over a bandwidth of 264 MHz.To reach this performance, time interleaving of three slices of the pipelined ADCpresented in [3] in a 0.35 µm BiCMOS process could be one option. The powerconsumption of one of the slices is 1.85 W, and the die area is 70 mm2. It is difficultto estimate what the total power consumption and area would be of such a solution,but if only the slices were added in parallel, a power consumption of 5.55 W, overan area of 210 mm2 would be the result. The envisioned slice does drop in SNDR atthe higher sampling rates, but that would not be a problem for the time interleavedoverpower ADC, since only fractions of that resolution is needed anyways. Evenif there is a spot of sunlight to this solution, both the power and the chip arearequired does not make this a feasible solution for a wireless handsets.

3.8.2 Parallel ADC design

The parallel ADCs is the second option to implement multistandard ADCs. Inthis approach, one specific and optimized ADC is added for each standard that isdesired. To make a comparison, let us look into the area of parallel ADCs thatwould cover GSM, WCDMA, WLAN/WiMAX and UWB. There are many ADCsthat are presented for each of the standards, where the results of the ADC canbe very different depending on the receiver chain implementation. The purposeof this exercise is not to find the largest nor smallest implementation for eachof the standards, but more to make a first assessment of the feasibility of such


an implementation for a low-cost wireless handset. The overview of the ADCs ispresented in Table 3.1.

Table 3.1: ADC specification

Standard Area Technology ReferenceGSM 1.0 mm2 0.5 µm [77]

WCDMA 1.0 mm2 0.35 µm [49]WLAN 1.6 mm2 0.18 µm [96]UWB 0.12 mm2 0.13 µm [93]Total 3.72 mm2 - N/A

The first thing worth noticing is that the processes are not the same, and the effectsof the total area is difficult to estimate. Given this figure as it is, an area of 3.72mm2 should be compared to the area of at least 210 mm2 from the overpowersolution. From this comparison, the parallel ADCs seems much more feasible. Thecost of this ADC would be large, due to the area that is required to implementthis solution. The power consumption of the ADCs would be nearly optimal foreach standard. This solution after all seems feasible, and this is the approach theindustry is using at the moment to design multistandard receivers [69]. What isthe potential gain of moving into a reconfigurable ADC compared to this solution?

3.8.3 Reconfigurable ADC design

A reconfigurable ADC is an ADC that is designed to reuse blocks in order tominimize the area, and at the same time reach the desired performance. Thereconfigurability can be implemented by changing the way the ADC is built, by re-arranging the blocks, called architectural reconfiguration, or by changing the blocksthemselves, called circuit reconfiguration. It can also be done with a combinationof architectural- and circuit -level reconfiguration.

The founder of the concept to reconfigure an ADC for many applications is dif-ficult to establish clearly, but early reports on reconfigurable ADCs, that also werepresented specifically as reconfigurable ADCs have been found from 1995 [15], wherea two-step ADC is reconfigured between a 2- and a 4-bit mode. This ADC was usedas an interface between an analog- and a digital- programmable field array. Thereconfigurable ADCs for wireless applications started to arrive a number of yearslater [19, 73, 79, 92]. These reconfigurable ADCs covered two standards. Thiswas soon extended to incorporate more standards, but there has not yet, to theknowledge of the author at the time of writing been any measurement results ona reconfigurable ADC that covers the GSM, WCDMA, WLAN and UWB, evenif the method to reconfigure between these standards have been presented [90].

3.8. MULTISTANDARD ADCS 69

There has been reports on reconfigurable ADCs between some of these standards[31, 91], but there are no chip implementations for this particular combination,which makes the area estimation difficult. There is one report on a triple-standardADC that is reconfigured between GSM, WCDMA and Bluetooth [74], but withoutmeasurement results. The layout is shown, which allows the area to be estimatedto around 1.2 mm2 for the triple band ADC [74]. If a flexible flash ADC could beadded to this architecture, as proposed in [91], then the total area for the combi-nation of GSM, WCDMA, Bluetooth and UWB could be estimated to about 1.5mm2 (1.2+0.12+overhead). It is worth to mention that this estimation is not reallycomparable since the additional area of the Bluetooth implementation may differfrom the additional area required for a WLAN implementation. This is about halfof the estimation for the parallel receivers. This would cut the manufacturing costof the ADCs in the reconfigurable receivers by almost a factor of 2. This motivatesthe work in the design of reconfigurable ADCs.

The next chapter will discuss the reconfigurable ADCs in more detail, and giveexamples on both architectural- and circuit-reconfiguration.

Chapter 4

Analog to Digital Converters: Reconfigura-

bility

4.1 Reconfigurability in ADCs

There were three methods of implementing multistandard ADCs for wireless com-munication mentioned in Section 3.8, namely the overpower design, the parallelADC design, and the reconfigurable ADC design. The overpower design was shownto not be feasible for handsets, due to the high power consumption. It was alsoshown in principle that the reconfigurable ADCs could be an attractive option fora multistandard handset, since it could have smaller area compared to the parallelADC approach.

The initial industrial approach to the design of multistandard receivers was withparallel receiver chains [69], and with this design choice the ADCs also become par-allel. The parallel receiver chains consume unnecessary area [32], and this was thereason to aim for the SDR receiver. The SDR receiver is built as a chain of reconfig-urable blocks, as described in Section 2.2.2. One of the blocks in the SDR receiverchain is the multistandard reconfigurable ADC. With this modern approach, andthe basic knowledge of ADCs, a more detailed picture can now be shown for howthe reconfigurable multistandard ADCs can be built.

If an ADC is reconfigured in the way the blocks in the ADC are used and or-dered, it is an architectural change of the ADC, or architectural reconfigurability.These blocks can also be changed, for instance how the amplifiers are biased, orhow many bits of resolution that a quantizer has in a Σ∆ ADC. These are examplesof how circuit level reconfigurability is applied to an ADC.

The previous chapter introduced several ADC architectures, e.g. flash, Σ∆, pipeline,etc. suitable for wireless applications without addressing their features for recon-

71

72 CHAPTER 4. ANALOG TO DIGITAL CONVERTERS: RECONFIGURABILITY

figuration. How much reconfigurability is inherent in these ADC architectures?

Flash ADCs can mainly be reconfigured at circuit level, where the number oflevels of interpolation can change, and the number of folds could also be adjustedin a dynamic manner. There are also some possibilities of architectural reconfigu-ration between normal, folding, and interpolating flash ADCs.

Σ∆ ADCs provide a high degree of reconfigurability on both circuit level andarchitectural level. At architectural level the loop order and oversampling ratio canbe changed, the number of included blocks, and way these blocks are arranged ine.g. a MASH architecture. At circuit level many things could change, such as biascurrents, amplifier performance, quantizer resolution etc.

Pipelined ADCs can provide reconfigurability at both the architectural level andcircuit level. The way the blocks are connected to each other, if there is feedbackof the signal between the blocks, etc. are examples of architectural reconfigurabil-ity. Combinations with other ADC architectures have also been reported, e.g. Σ∆ADCs [35]. At the circuit level the number of bits per stage could be reconfigured,as well as bias currents and amplifier performance.

Algorithmic ADCs provide easy circuit level reconfigurability by selecting thenumber of iterations during which the data is processed. Secondly it also providescircuit level reconfigurability by selecting the duration of the respective phases,along with the bias currents and amplifier performance.

Successive approximation Register ADCs also provides easy circuit level re-configuration, with the binary search algorithm. The binary search can simply bestopped at an earlier stage to get lower resolution, and the bias currents to theamplifiers can be changed as well.

Time interleaved ADCs provides the reconfigurability of the slices, but in addi-tion to this also the freedom to select the number of slices, and the order they areused.

These ADC architectures provide a high degree of reconfigurability, and they arepotential candidates for the implementation of a multistandard ADC for wirelesscommunication.

The target of this research was to investigate reconfigurability at both circuit andarchitectural levels, and a case study was done at each level. Before looking intothese case studies let us show some examples of the architectural and circuit levelreconfigurability.

4.2. ARCHITECTURAL RECONFIGURABILITY 73

4.2 Architectural reconfigurability

The first case study in this research effort is on architectural level reconfiguration,where the architecture of the ADC is changed in order to meet the specifications fortwo different wireless communication standards. This is not a new concept, and inorder to further illustrate the concept of architectural reconfiguration, two previousreconfigurable ADCs are explained, where different reconfigurability schemes areused.

The first example is a Σ∆ ADC that was reported in [74]. This ADC is recon-figured between different loop orders, quantizer resolution and OSR to achievecoverage over three wireless communication standards, namely GSM, Bluetooth,and UMTS (WCDMA).

The second ADC is a flexible pipelined ADC, presented in [5]. This ADC consistof a number of stages that can be connected in series, or connected with feedback,in order to achieve the desired reconfigurability. In this way a combination of thepipelined ADC and the algorithmic ADC is achieved.

4.2.1 A reconfigurable Σ∆ ADC [74]

The switched capacitor Σ∆ modulator is reconfigured both at architectural leveland circuit level, in order to optimize the power consumption for all three modesof operation. The specifications for the ADC are given in Table 4.1.

Table 4.1: Modulator specification

GSM Bluetooth UMTSResolution (bits) 13 11 9

(SINAD) 80 dB 68 dB 56 dBBandwidth 200 kHz 1 MHz 4 MHz

Some of these specifications are in contrast with the standard overview in Table 2.1,but no information is provided about the intended receiver architecture, and thusthese ADC specifications can be well adjusted to the intended receiver architecture.

A block diagram of the ADC is shown in Fig. 4.1, where it can be seen that theADC has a number of reconfiguration possibilities. The ADC is configured in thefollowing way for the three standards:

• GSM: L = 3, N = 1, and OSR = 100

• Bluetooth: L = 4, N = 1, and OSR = 20


H1(z)

ADC1

DAC1

X(z)b1 b2

1

H2(z)- Y(z)-

H3(z)

ADC2

DAC2

Y1(z)b3-

H4(z)

ADC3

DAC3

Y2(z)b4-

1 or 2 bit

1 or 2 bit

Dig

ital

pro

cess

ing

Bluetooth /

UMTS

Settings

Settings

Settings Settings

Figure 4.1: Block diagram of the MASH ADC [74]

• UMTS: L = 4, N = 2, and OSR = 10,

where L is the Loop order of the modulator, N is the number of bits in ADC3, andOSR is the oversampling ratio. The theoretical SQNR of 126 dB in GSM mode, of94 dB in Bluetooth mode, and 73 dB in UMTS mode.

Systematic behavioral modeling was used to find circuit block parameters for theimplementation of the loop filters, and the comparators in the ADCs. This wasdone with care taken to the process, temperature and supply voltage variations.The results met the specifications, and are presented in Table 4.2.

4.2.2 A reconfigurable pipelined ADC [5]

This second example of reconfigurable ADCs for wireless communication standards,which only applies architectural level reconfiguration. The targeted wireless appli-cations were: GSM, UMTS, and WLAN. The ranges of operation were given inbandwidths of the baseband signal, from 200 kHz (GSM), up to 20 or 40 MHz(WLAN). The dynamic ranges were given to be somewhere beteen 6 to 12 bits. Itis said that these specifications depend on the receiver architecture, and the trade-off between ADC performance and the anti-aliasing filter. In [5], it was concluded itis difficult to implement the reconfigurable Σ∆ ADCs for high-speed applications,

4.2. ARCHITECTURAL RECONFIGURABILITY 75

Table 4.2: Simulation results

Name GSM Bluetooth UMTSBehav. CircuitSim. Sim.

(worst) (typ)

Behav. CircuitSim. Sim.

(worst) (typ)

Behav. CircuitSim. Sim.

(worst) (typ)Resolution

(bits)(SINAD)

12.9 13.079.3 dB 80.0 dB

10.9 11.367.2 dB 68.0 dB

9.1 9.056.3 dB 56.0 dB

Bandwidth 200 kHz 1 MHz 4 MHz

and thus a new reconfigurable pipeline approach is desirable. Pipelines have provento cope with the speed requirements for e.g. WLAN ADCs. The block diagram ofthe proposed architecture is shown in Fig. 4.2.

Stage 1 ...Stage 2

Digital correction / Digital synchronization / Switch control

Stage 9Vin

10 bits

1.5 bits 1.5 bits 1.5 bits

Stage 3 Stage 4

1.5 bits 1.5 bits

3

Feedback

State controlDigital Control Unit

Figure 4.2: Block diagram of the reconfigurable pipeline [5]

Two signals control the operation of the pipelined stages. Stages 1 and 3 are slightlydifferent than the other stages, in order to support the algorithmic ADC behaviorthat are used to increase the dynamic range of the ADC. One of these control sig-nals control the feedback to stages 1 and 3, and the other control signal assures thenormal operation of the ADC.

The ADC has been fabricated in a 0.18 µm CMOS process, and the measurementresults of the ADC are presented in Table 4.3. An input signal of an amplitude of1 dBV below the full-scale voltage is used, at an unspecified frequency.


Table 4.3: ADC reconfigurability

10-bit 8-bit 6-bit10 MHz

SNDR 56.2 dB 46.9 dB 35.4Power 93.7 mW 73.0 mW 51.8 mW

5 MHzSNDR 55.9 dB 47.0 dB 36.1 dBPower 52.6 mW 52.4 mW 30.4 mW

2.5 MHzSNDR 56.0 - -Power 30.3 mW - -

In this table it can be seen how the SNDR is consistent with the reconfigurationthat is made between the modes of operation, and that the power dissipation scaleswith the sampling frequency.

4.2.3 The architectural reconfigurability case study

In the case study presented in Chapter 5, an ADC was designed to be reconfiguredbetween Σ∆ and flash architectures, to cover the bandwidth-accuracy space ofBluetooth and UWB standards. To take maximum advantage of the architecturalreconfiguraion, circuit level reconfiguration is implemented in the flash ADC.

4.3 Circuit reconfigurability

These three examples, including the case study on architectural reconfigurabilitypresented in the next chapter provides a solid explainiation on architectural recon-figurability. The second case study in this research is on circuit level reconfigura-tion, where circuit parameters are changed in order for the ADC to meet the desiredspecifications for different wireless standards. These circuit level parameters canbe, e.g. bias currents, capacitor sizes, and amplifier gain. Two examples of circuitlevel reconfiguration are presented:

The first example is presented in [74], where architectural level reconfigurationwas used in combination with circuit level reconfiguration to optimize the designe.g. for power consumption in the loop filter in all the modes of operation.

The second example is the reconfiguration of a resistor ladder based flash ADCthat was presented in [99]. This ADC has two modes of operation, one fast low-resolution mode, and one slow, high resolution mode, where the bias conditions of

4.3. CIRCUIT RECONFIGURABILITY 77

the comparator preamplifiers are changed to optimize the power consumption forboth modes of operation. The ADC changes from only a straight flash ADC in thelow resolution mode, to implement interpolation in the high resolution mode. Thisreconfiguration is at the architectural level for the flash ADC, but if e.g. the flashADC is used in a Σ∆ ADC, this same reconfiguration is at circuit level of the Σ∆ADC.

4.3.1 Circuit level reconfiguration in a Σ∆ ADC [74]

The Σ∆ ADC presented in [74] covered three wireless communication standardsby changing the oversampling ratio, the quantizer resolution, and the loop order ofa switched capacitor Σ∆ modulator. This was not the only reconfigurability thatwas implemented in that work. The amplifiers in the loop filters were also madereconfigurable, due to the change in oversampling ratio, and sampling rate, andthus the amplifier operating conditions. The critical conditions for the amplifiersis the settling time requirements that the fast clocking of these switched capaci-tor circuits are posing. The clocking speeds of the different modes of operations are:

• GSM: 200 kHz · 2 · 100 = 40 MHz

• Bluetooth: 1 MHz · 2 · 20 = 40 MHz

• UMTS: 4 MHz · 2 · 10 = 80 MHz

In addition to the clocking speeds of the circuits, the accuracy of the settling alsomakes a difference in the design. This requirement is higher in the high-accuracyGSM mode, compared to the other two.

There were 4 loop filters implemented in the Σ∆ modulator, and the amplifiersin these loop filters were designed as folded cascode amplifiers. The transistor sizesin these 4 amplifiers were the same, a part from the input differential pair of theamplifiers of loop filters 2 and 3 in Fig. 4.1, which had larger input differential pairsto obtain a quicker response. The bias currents of these amplifiers were also ad-justed to get different performance of these amplifiers. The bias current generationto these amplifiers is shown in Fig. 4.3. Here it can be seen that all of the switchesare closed for the maximum current in UMTS mode. Only two of the switchesare active in GSM mode, and finally only one branch is providing the current inBluetooth (BT) mode.

The amplifier performance is briefly summarized in Table 4.4. The full informationabout the amplifiers can be found in [74]. It can be seen that the amplifiers havelarge variations in both gain-bandwidth product (GBW), and in DC gain, for thedifferent standards.


bias2

AVDD

Mn1 Mn2

UMTS

MBT

Iref

Mref

GSM /

UMTS

IBTI1

I2

IB

Figure 4.3: Bias current generation for different modes of operation to amplifiersin [74]

Table 4.4: Reconfigurable OPAMP specifications

Name GSM Bluetooth UMTSGBW/DC gain GBW/DC gain GBW/DC gain

(MHz / dB) (MHz / dB) (MHz / dB)Amplifier1 244 / 61.6 183 / 62.7 326 / 58.5Amplifier2 143 / 64.2 130 / 64.6 251 / 57.3Amplifier3 143 / 64.2 130 / 64.6 232 / 59.5Amplifier4 N/A 105 / 62.7 102 / 58.5

4.3.2 Circuit reconfiguration of a flash ADC [99]

This ADC is not primarly intended for wireless applications, but it is a genericsolution, and it has a good tutorial value for circuit reconfiguration of flash ADCs.The application is Partial Response Maximum Likelihood (PRML) read channelwith a digital servo [99]. The reconfiguration of the ADC can be done between350 Mega Samples Per Second (MSPS) with a resolution of 5.75 bits, to 150 MSPSwith a resolution of 6.75 bits. A block diagram of the reconfigurability scheme atarchitectural level is shown in Fig. 4.4, where an extra set of grey marked compara-tors can be seen. These comparators are used to implement interpolation, to createthe extra bit of resolution. Many of the details in the original block diagram in[99] have been left out for simplicity, e.g. the autozero switches, and how the inputsignals to the preamplifiers are connected. The extra grey clocking block is usedto clock the extra comparators. In addition, the bandwidth of the preamplifiers isalso scaled down by changing the bias current. The preamplifier used in the ADCis shown in Fig. 4.5, where the bias current IB is changed between the two modesof operation, to optimize the power consumption.

4.3. CIRCUIT RECONFIGURABILITY 79

+

-

+

-R

+

-

+

-

+

-

+

-

Vrp1

Enco

der

and o

utp

ut

lath

ces

bit 0bit 1bit 2

+

-+-+

-+-

+

-+-+

-+-

+

-+-+

-+-

Vr0

Vrn1

R

Q1

Q11

Q20

Q01

Qn1

Qn11

bit 3bit 4bit 5

... ...

...

...

... ...

Clock

Bias Auto Zero, gain control and ADC clocking

bit 6

Figure 4.4: Block diagram of reconfigurable flash ADC [99]

The ADC was manufacured in a 0.35 µm BiCMOS process, and the measured re-sults from the chip are summorized in Table 4.5. The supply voltage was 5 V ± 10 %.The power dissipation was 225 mW at 400 MHz clock frequency with a supply volt-age of 3.3 V. It is worth while to notice that the power consumption that is presentedis from a low clocking speed, with a lower supply voltage. It is likely to believethat the power consumption of the ADC is significantly higher when operating at350 MSPS, and the full 5.5 V supply.

4.3.3 The circuit reconfigurability case study

In the case study presented in Chapter 6, an ADC was designed to cover thebandwidth-dynamic range space of CDMA2000-1X and Bluetooth communicationstandards, by the use of circuit level reconfiguration. To limit the work to circuitreconfigurability only, an algorithmic ADC was implemented, where measures weretaken to achieve the highest possible reconfigurability in sampling rate, with pre-


AVSS

inninp

AVDD

outpoutn

M2 M3

M5 M4 M7M6

IB

Figure 4.5: Preamplifier schematic in reconfigurable flash ADC [99]

Table 4.5: Settys ADC reconfigurability

Name Fast mode Slow modeSpeed 350 MSPS 150 MSPS

Resolution 5.75 bits 6.75 bitsENOB (Fin=Fs/4) 5.44 bits 6.15 bits

SNDR 31 dB 35.3 dB

served dynamic range. The use of this ADC is not only limited to these wirelesscommunication standards, but it is also appropriate for sensor applications. Thiswill be discussed more in detail in Chapter 6.

Chapter 5

Architectural Reconfigurability: A Case

Study

5.1 Motivation

The purpose of this case study on architectural reconfigurability was to investigatethe feasibility for reconfigurable ADCs for deployed Wireless Personal Area Net-works (WPANs). The selected standards were Bluetooth (BT) and the WiMediadefinition of OFDM Ultra WideBand (UWB).

Many handsets today have a BT transceiver, and it would be a great benefit ifthis transceiver could be reconfigured to UWB to deliver higher data rates. Thiswould allow e.g. live video and audio transfer from the handset to the home-entertainment center, or to download music and or video from a laptop computer.This is illustrated in Fig. 5.1.

Unfortunately the BT and UWB communication standards are not similar stan-dards in any other way than the intended applications, as illustrated in Fig. 2.10.What are the specifications for a multistandard BT/UWB receiver, and what spec-ifications this impose on the ADC.

5.2 The reconfigurable BT/UWB receiver

The envisioned receiver is a SDR receiver, which is shown in Fig. 2.8 in Chapter 2.There are recent publications showing implementations of full-scale transceiverscovering the whole UWB standard [114], which advocates that a reconfigurable re-ceiver for BT and UWB is feasible today.

Significant effort was spent in the standardization process of the WiMedia Alliance,where one white paper can be regarded as central contribution [8]. Big parts of the

81

82 CHAPTER 5. ARCHITECTURAL RECONFIGURABILITY: A CASE STUDY

UWB or BT

UWB

Figure 5.1: Handset applications for a BT/UWB transceiver

physical layer in the UWB standard issued by ECMA in 2006 [22] was based on thework presented in this white paper. This white paper presents, e.g. a link budgetanalysis for the first band group between 3.1 up to 4.7 GHz, and analysis of theinterferers for this band group [8]. Based on this work, a 4-bit ADC resolution wasproposed sufficient [34]. The same link budget analysis was also interpreted laterthe same year, in the way that a 5-bit ADC [87] or 6-bit ADC [93] was needed. The4-bit ADC specified in [34] did not consider the DCM modulation that is applied inorder to receive the higher data rates in the UWB standard. With this confusion, aclarification is needed. Based on the link budget from [8], a simple hand calculationwas made. The dynamic range of the ADC mainly needs to consider a few things:

The highest ADC input power in any operating condition is not limited byin-band interferers, which put no special constraints to the dynamic range of theADC [8].

The gain step size in the receiver chain has been reported to 12 dBs ofan LNA [87].

The SNRmin required to demodulate the signal can be found to be 8 dBs[101].

5.2. THE RECONFIGURABLE BT/UWB RECEIVER 83

Margin for the quantization noise has been presented to be from 5 to 10dBs [11], and a pessimistic 10 dB was assumed.

Total required dynamic range from this calculation is 30 dBs, which is equiv-alent of 6 bits.

Now only the bandwidth or the sampling rate for the UWB ADC needs to beestablished. This also depends on the receiver performance, but for a I/Q receiver,528 MSPS would be sufficient. This established the specification for UWB modeto 30 dB DR over 264 MHz bandwidth.

Similar analysis for the link budget can be made for the BT standard:

The highest ADC input power in any operating condition is in the BTcase limited by the in-band blockers, which can be 30 dBs higher than the desiredinput signal [17].

The gain step size in the receiver chain depends on design choices in thereceiver chain, but the short preambles in the BT standard complicates the designof the Received Signal Strength Indicator (RSSI) loop. A gain step of 12 dBs hasbeen reported [17].

The SNRmin required to demodulate the signal can be found to be 6 dBsfor a BER of 0.1 % for the GMSK modulation [101].

Margin for the quantization noise is the same here as in the UWB handcalculation above. 10 dBs was selected to be on the pessimistic side [11].

Total required dynamic range from this calculation is 58 dBs, which is equiv-alent of 10 bits.

These 10 bits, or 60 dBs in DR, over a bandwidth of 500 kHz, have also beenreported as the targeted specifications for many ADCs for BT applications [24, 28,51, 115].

To fulfill the requirements of these link budgets, an ADC that covers 6 bits over abandwidth of 264 MHz in UWB mode, and 10 bits over 500 kHz in BT mode, isneeded. How can such an ADC be designed?


5.3 Reconfigurable ADC design for BT/UWB

If a dedicated ADC was to be designed for BT, the choice would have been a Σ∆ADC, since it requires high Dynamic Range (DR), and low bandwidth. Σ∆ ADCstake advantage of noise shaping and oversampling to improve the accuracy overnarrow frequency bands, of low-performance analog blocks. For the UWB stan-dard, a dedicated ADC would have been of flash-type, due to the high bandwidthand low DR requirements. In this case study one ADC is to be reconfigured to bothof these requirements. It is a difficult challenge to fully reconfigure a Σ∆ ADC toa flash ADC, or the other way around. Fortunately the Σ∆ ADC requires a flashADC as its quantizer.

This opens a possibility to build a Σ∆ ADC for BT applications, with a recon-figurable flash ADC that can be used as quantizer of the BT Σ∆ mode, and asa stand alone ADC in the UWB mode [37]. The proposed solution is shown inFig. 5.2. Σ∆ ADCs with reconfigurable flash ADCs have previously been presentedin e.g. [31, 91], where the focus of the reconfigurability of the flash ADC has beento change the quantizer resolution. In this work the flash ADC is reconfigured tobe used as a stand-alone converter for a different wireless standard.

+ +H1(z)

ADC

DAC

4 / 6In

b1 b2

k1

1

Bluetooth Mode

BT / UWB

H2(z)

Figure 5.2: Block diagram of Reconfigurable BT/UWB ADC

5.3.1 Sigma Delta ADC

The dominant part of Fig. 5.2 is the feed-forward Σ∆ ADC. This is only one partof the reconfigurable receiver, and it is active in the BT mode. The loop orderand number of bits in the quantizer is a design choice that have to be done at anearly stage in the design process, and there are many possible solutions to achievea desired dynamic range, as shown in Fig. 3.12. The possible theoretical SQNR fora general Σ∆ ADC is given by Equation (3.19) in Section 3.3.2.

The target of this design was to achieve a low-power solution. This approachto achieve this target was to primarily select as low loop order as possible to limit

5.3. RECONFIGURABLE ADC DESIGN FOR BT/UWB 85

the number of active components that needs biasing, and secondly to choose a lowoversampling ratio. The feedforward architecture was selected as a preferred archi-tecture, since it has previously been proven to be highly linear [100], and to havelow requirements of the included circuit blocks, as shown in Section 3.3.3.

Looking back at Fig. 3.12, it can be seen that it would require an oversamplingratio of 64 or more to achieve 60 dBs of dynamic range for a first order modulator,even with a 4-bit quantizer. For a second order modulator an oversampling ratioof 16 would be sufficient to meet the same performance for a 4-bit quantizer. Thisneeded validation, and a behavioral model was built in Matlab/Simulink, basedon the blocks presented in [64], and after careful consideration and weighting ofparameters, an oversampling ratio of 16 was selected with a 4-bit feedback for asecond order modulation. The multi-bit feedback in Σ∆ ADCs can in some casesrequire linearization techniques in order not to degrade the performance of the mod-ulator. It was found by the use of exhaustive behavioral modeling of componentmismatches in the feedback network that standard matching would be sufficient forthis application.

Thus the architecture shown in Fig. 5.2 was set for the BT implementation. Moreissues about the implementation, with the simulation results from the behaviorallevel as well as the circuit level follows in the sections below. With this high-levelspecification for the BT mode, the reconfigurable flash ADC that can support 4-bitquantization needed to be designed.

5.3.2 Reconfigurable flash ADC

One of the key components in this design is the reconfigurable flash ADC that isthe quantizer in the Σ∆ ADC. The Capacitive Interpolation (CI) scheme originallyproposed by [54], and recently implemented for UWB applications [93] was selectedfor this implementation for two reasons. The first reason was the inherent option ofreconfigurability, since the interpolation was done in many stages. This interpola-tion could theoretically be stopped at any level above the input level, and be usedas output. This concept is shown in Fig. 5.3, where it can be seen that a resolutionof 3 up to 6 bits is possible with the use of the one-to-two interpolation structure.

The second reason for selecting the CI flash ADC architecture was that the powerconsumption was proven to be very competitive in a 0.13 µm CMOS process [93],as shown in Fig. 5.4. A summary over the energy per quantization step, given inEquation (3.10) is shown in Fig. 5.4, where this FOM is presented for differenttypes high-speed flash ADCs [14, 20, 30, 39, 55, 72, 76, 81, 89, 93, 94, 95, 106, 107,108, 116, 117, 119].

86 CHAPTER 5. ARCHITECTURAL RECONFIGURABILITY: A CASE STUDYS

tage

1, 3 b

its

Sta

ge

2, 4 b

its

Sta

ge

3, 5 b

its

Sta

ge

4, 6 b

its

Vin

EN EN EN

Out1

Out2

Out1

Out2

Out1

Out2 Out

1/21/21/2

9

9

17

17

33

33 65

65 Comparators

Thermometer to binary conversion

65

STROBE

...

UR ORb0 b5...

Figure 5.3: Block diagram of possible reconfigurability in a CI flash ADC

The one-to-two interpolation scheme is shown at block level in Fig. 5.5 was imple-mented. It can be seen how the capacitors are used to interpolate the new referencelevels. The interpolated voltages are held with the use of interpolating amplifiers.

At this point in the design, the upper level of resolution could be determined fromthe requirements of the UWB standard, and the lower requirement could be deter-mined from the Σ∆ design choices above. This implied that a 4/6-bit CI flash ADCwas needed. Let us step back again to the BT mode, and look more into details ofthe implementation.

5.4 Implementation of the ADC for Bluetooth mode

The established requirements for the ADC in BT mode is 60 dB DR over a 500kHz bandwidth. The ideal SQNR for the selected second order Σ∆ modulator with4-bit feedback is given by

SQNR = 6.02N + 1.76 + 50log (OSR) − 12.9, (5.1)

5.4. IMPLEMENTATION OF THE ADC FOR BLUETOOTH MODE 87

100

101

102

108

109

1010

Sam

ple

rat

e (H

z)

EQ (pJ/conv)

R-ladder

CI

Time Int

Current mode

Figure 5.4: Energy per quantization step for flash ADCs

where N is the number of bits of quantizer resolution, and OSR is the OversamplingRatio. To reach the 60 dB DR needed for the BT standard, a 4-bit quantizer wasselected, with an oversampling ratio of 16. This gives an ideal DR of 73.1 dB. Thisleaves 13.1 dB margin for implementation losses.

The Matlab toolbox developed by Schreier [67], was used to establish a transferfunction and the coefficients needed for this second order feed-forward Σ∆ ADC.The coefficients k1, b1, and b2, as shown in Fig. 5.2 were found to be k1 = 1.75, b1

= 1, and b2 = 0.8.

A behavioral model was built in Matlab/Simulink in line with the design proceduredescribed in Chapter 1, where the following non-idealities were considered:

• DAC non-linearity

• Quantizer offsets

• Amplifier DC gain

• Amplifier bandwidth

• Amplifier slew rate


1

1

1/2

1/2

rst

rst

rst

rst

rst

rstrst

rst

rst

rst

samp

samp

to adjacent stages

to adjacent stages

Vref+

Vref-

Vin

Figure 5.5: Block diagram of the 1-to-2 capacitive interpolation scheme

• Amplifier offset

• kT/C noise in amplifiers

• Thermal noise in amplifiers

• Capacitor matching (Coefficient accuracy)

The behavioral models are based on the same concept as shown in [64], and theywill not be presented here. The results of the behavioral level simulations were aset of specifications for the mentioned non-idealities, which are shown in Table 5.1.

From this table, a few practical interpretations can be made:

5.4. IMPLEMENTATION OF THE ADC FOR BLUETOOTH MODE 89

Table 5.1: Bluetooth ADC specifications from behavioral modeling

Specification ValueDAC component matching < 2 %

Amplifier DC gain 30 dBVAmplifier bandwidth 7 MHzAmplifier slew rate 10 MV/sSmallest capacitor 1 pF

Thermal RMS noise in amplifiers 10 mVOffset of amplifiers 10 mV

Capacitor matching (Coefficient accuracy) < 1 %Quantizer resolution 4 bitsOversampling ratio 16

DAC design does not need any linearization techniques, since 2 % matching canbe achieved in modern CMOS processes.

Amplifier design is straight-forward. The specifications for DC gain is very low,and can be met with a simple differential pair with current mirror load, using aCommon Mode FeedBack (CMFB) to establish the output DC voltage. A transis-tor level schematic of the implemented amplifier is shown in Fig. 5.6. This amplifieris a central block since many of the non-idealities in the list are associated to it.The bias currents and the component sizes have to be kept at a sufficiently largelevel in order for the specifications for offset, and thermal noise to be met.

AVSS

bias2

inninp

AVDD

outpoutn

M2 M3

M1

M4 M5CMFBCMFBbias1 bias1

M7M6

Figure 5.6: Implemented amplifier for the BT Σ∆ ADC

Smallest capacitor of 1 pF was found by inserting different levels of kT/C noiseinto the amplifiers. This puts some constraints to the DC current needed in the


amplifiers, to make them meet the specifications of Table 5.1.

Capacitor matching is an important aspect of the design of SC circuits. Thematching of the capacitors, or the precision in the gain coefficients is a concern,since it can affect the stability of higher order Σ∆ modulators. Even if this isnot a central concern for second order modulators, the pole locations for processvariations of the coefficient implementation was investigated with the use of RootLocus analysis. The root locus for 1 % coefficient variation is shown in Fig. 5.7,where it can be seen that the poles reside comfortably inside the unit circle for thisvariation.

-1 -0.5 0 0.5 1

-1

-0.5

-0.25

0

0.25

0.5

1

Root Locus

Real Axis

Imag

inar

y A

xis

Figure 5.7: Root locus plot for coefficients k1=1.75, b1=1, and b2=0.8

Quantizer implementation was important, since most of the circuit level recon-figurability needed to be implemented in this block. The CI flash ADC was usedas the quantizer in BT mode, and as a stand-alone ADC in UWB mode. The finalblock diagram of the implemented CI flash ADC is shown in Fig. 5.8, where it canbe seen that the interpolation is done in 2 stages for 4-bit resolution needed forBT. In BT mode, the last two stages of the interpolation are not needed, and thusturned off to save static power consumption. The first two stages are configured ina low-speed, low-power mode, so that they can meet the requirements of the BTΣ∆ ADC. In order to reduce the current in the first two stages, the bias currentsthat are driving the interpolation amplifiers, which can be seen in Fig. 5.5, couldbe significantly reduced. Let us look more in detail how this ADC was designed.

5.5. IMPLEMENTATION OF ADC FOR UWB MODE 91S

tag

e 1

, 3 b

its

slo

w /

fa

st

Sta

ge

2, 4

bit

s s

low

/ f

ast

Sta

ge

3, 5

bit

s

Sta

ge

4, 6

bit

s

Vin

UWB UWB

Ou

t1

Out2 Out

UWB/BTUWB/BT

9 17

17

33

65

65 Comparators

Thermometer to binary conversion

65

STROBE

...

UR ORb0 b5...

BT UWB

Figure 5.8: Block diagram of Reconfigurable CI flash ADC

5.5 Implementation of ADC for UWB mode

The requirements for the ADC in UWB mode was found from the hand calculationsto be 30 dB DR over a 264 MHz bandwidth. In order to support this, a 6-bit designwas targeted, to have some margin for implementation losses. This full theoreticalSQNR for a Nyquist rate ADC without oversampling is given by

SQNR = 6.02 · N + 1.76, (5.2)

where N is the number of bits. In this case, the ideal SQNR would be 37.88 dB,which leaves a margin of almost 8 dB.

To implement this high-speed ADC reconfigurable, behavioral modeling was donein Matlab/Simulink to establish circuit block specifications, as described in Chap-ter 1. This effort has been presented in two papers, first the initial UWB-onlyhigh-speed CI flash ADC in [89], and secondly the reconfigurable UWB and BTreconfigurable flash ADC in [36].

These models were used to establish circuit block specifications, and they includedthe following ADC non-idealities:

• Amplifier DC gain

• Amplifier slew rate

• Amplifier bandwidth


• Amplifier offset

• Amplifier thermal noise

• kT/C noise

• Reference noise

• Sampling clock jitter

• Interpolation capacitor matching

The behavioral models are implemented in the same way as described in [64], apartfrom the amplifier and the clock jitter model, that has been improved.

The amplifier behavioral model has been improved, since this should oper-ate at very high-speed, and the amplifier also has the largest number of ADCnon-idealities associated to it, where all of these non-idealities should be consideredat the behavioral level to achieve an accurate circuit specification for the amplifier.The new model is shown in Fig. 5.9, where it can be seen that there are two parallelforward paths. The upper path is activated in sample mode, and the lower pathis active in reset mode. This way to model the amplifier is more realistic, since adifferent feedback path is implemented in the reset mode compared to the samplemode. This modeling supports the use of an asymmetry in the sampling clock, insuch a way that more time is spent of the clock period in sampling than in the resetphase, and the impact of this asymmetry can be simulated.

1Out

Out1

kT/C Noise

1

clk_constant

0

analog_ground

1den(s)

Reset BW

1den(s)

Sample BW

Reset SR

Sample SR

Product3

Product2

Product1

Product

Gaussian

Gaussian NoiseGenerator

x1

Gain

x2

Amplifier offset

Add4

Add3

Add2Add1

Add2clk

1Inp

Sampling Path

Reset Path

Figure 5.9: Behavioral model of interpolating amplifier from Matlab/Simulink

Clock jitter model is only implemented as a first order approximation in [64, 89],and the effects of higher order terms needed to be investigated. A comparison of

5.5. IMPLEMENTATION OF ADC FOR UWB MODE 93

the first-order linear jitter model with a phase modulated jitter model is shown inFig. 5.10, where it can be seen that the error of the first-order model is large forlarger values of clock jitter, compared to the phase modulated model. To generate

V0

-V0

Input signal (V)

Sampling pulseTA

EA

TSAMPLE

THOLD

Time uncertainty

Amplitude

uncertainty

t

Linear model Phase modulated model

Figure 5.10: Input signal amplitude error caused by sampling clock jitter

the phase modulated jitter, the input signal is generated with a phase modulator,where the deviation in phase is set with a Gaussian noise generator. The two jittermodels are shown in Fig. 5.11. The maximum amplitude error EA of the linearmodel of jitter can be expressed as

EA = V0 · 2πf · ∆TE , (5.3)

where V0 is the input signal amplitude, f is the input signal frequency, and ∆TE isthe time jitter error [64, 89]. In the phase modulated jitter model, the input signalVin is given by

Vin = V0sin (2πf + φE (t)) , (5.4)

where V0 is the input signal amplitude, f is the input signal frequency, and φE(t)is the jitter phase error. This jitter phase error is given by

φE (t) = 2πfSTE (t) , (5.5)

where TE(t) is the jitter time error, and fs is the sampling frequency. This modeltranslates the time error into a phase shift of the input signal, which contributesto a more accurate jitter model, since no linearization takes place.

Behavioral level simulations have been made to find the circuit block specifica-tions of the non-idealities mentioned above. These simulation results are shown forboth UWB and BT modes of operation in Table 5.2. These specifications serve ascircuit block design specifications in the circuit design phase of the ADC.

Amplifier design is one of the main challenges in this design. There are a largenumber of amplifiers needed, and the demands on these amplifiers are very high


1

Out

S ine Wa ve

P roduct

Gaussian


-K-

Ga in

du/dt

De riva tive

x

Consta nt

Gaussian


a)

1Out

P M

P MModula torP a ssba nd

Gaussian


1

Ga in

x

Consta nt

Gaussian


b)

Figure 5.11: Behavioral model of signal generator including jitter a) as suggestedby [64], and b) as suggested by [36]

in UWB mode. The combined UWB and BT specifications only applies for theinterpolating amplifiers in the first two stages, since they are the only ones activein both modes of operation. The interpolating amplifiers in the last two stages are

5.5. IMPLEMENTATION OF ADC FOR UWB MODE 95

Table 5.2: CI flash ADC specification from behavioral modeling

Specification UWB BTSampling rate 528 MSPS 16 MSPS

ADC resolution 6 bits 4 bitsAmplifier DC gain 15 dBV 17 dBVAmplifier slew rate 500 MV/s 10 MV/s

Amplifier bandwidth 400 MHz 70 MHzAmplifier offset 10 mV 10 mV

Amplifier thermal noise 1 µV, RMS 1 µV, RMSSmallest capacitor 100 fF 100 fFOffset of amplifiers 10 mV 10 mVCapacitor matching < 1 % < 1 %Sampling clock jitter 20 psec 100 psec

only active when the ADC is configured in UWB mode. The specifications for theinterpolating amplifiers is very different in bandwidth between the two modes ofoperation, but very similar when it comes to DC gain. A reconfigurable amplifier asshown in Fig. 5.12 was designed, where it can be seen that the bias current and theamplifier loads are reconfigurable. The high bandwidth requirement of 400 MHz

AVSS

bias2

inninp

AVDD

Reset

outpoutn

M1

M2 M3

M4

M6RR

M5

BT BT

UWBUWB

AVSS

M8 M9-39

M7

UWB

Figure 5.12: Implemented amplifier for the BT Σ∆ ADC

3-dB bandwidth in UWB mode required a bias current of 0.85 mA to be used. Thiscurrent could be scaled down to 30 µA in BT mode. This is done by changing thecurrent trough the transistor M7. The loads in UWB mode are resistors, to reducethe parasitic capacitance at the output of the amplifier. In BT mode, a diode loadis used. Neither of these loads requires a CMFB circuit, which simplifies the design


and reduces the capacitive load at the output nodes. The transistors M2, M3, andM4 are not changed between the two modes of operation. Amplifier offset is con-sidered by keeping the input differential pair large, and by proper layout. Amplifierthermal noise is reduced by using a large aspect ratio of the input differential pair.

Smallest capacitor put constraints on the amplifier bias currents. The require-ment of only 100 fF still made the amplifier design very challenging in order tomeet the bandwidth and slew rate.

Capacitor matching of 1 % could be reached with the accuracy in standardCMOS processes, if special considerations were taken in the layout of the design.

Sampling clock jitter needs special attention in the UWB mode. This clock jitteroriginates in part from the phase noise of the external clock generator [7, 104], andin part from the non-overlapping clock generation circuits [103]. These two jittercontributions can be added, since they can be regarded as uncorrelated [52]. Thesampling clock jitter have previously been studied [103], where it was shown thatfor a 5 % supply voltage variation to the clock generation circuit, a jitter of 1 % ofthe clock period could be created alone. In the UWB mode, this 1 % is the full 20psec. of jitter that is specified in Table 5.2, and special consideration have to betaken in order to reduce the supply voltage variation to the clock generation circuits.

Power saving strategy In the UWB mode, all the blocks of the BT Σ∆ ADCare powered down, except for the CI flash ADC, which is configured to high-speed,high-resolution mode. In this mode, all of the interpolating stages are activated,and configured for the high-speed operation, as shown in Figure 5.8. The operationin BT mode was explained in Section 5.4.

The layout of the flexible CI flash ADC was performed in a 0.18 µm CMOS process,and the layout is shown in Fig. 5.13. The layout measures 1.3 mm times 1.6 mm,including pads. The active area is approximately 1 mm2.

Both modes of operation were simulated both at behavioral level in Matlab/Simulinkas well as at circuit level, and the simulation results are presented in the next sec-tion.

5.6 Simulation results

The systematic design approach that was used facilitated simulation results fromboth the behavioral modeling, and from the circuit implementation. The behavioralmodeling in Matlab/Simulink was thus used to establish block specifications to fa-cilitate the circuit level implementation. Furthermore behavioral level simulationswere done in VerilogA/AHDL in the cadence environment to re-validate the ADC

5.6. SIMULATION RESULTS 97

Figure 5.13: Layout of CI flash ADC

performance to the system level. In this section, two levels of simulation results areshown, one from the behavioral level modeling in Matlab/Simulink, and secondlyfrom the transistor level implementation in cadence.

5.6.1 Bluetooth mode

Since both BT and UWB are frequency hopping mobile communication standards,there will be in-band interferes that the chain has to process. This puts strictconstraints on the linearity of all the blocks in the receiver chain, including theADC. In order to ensure that there is no degradation to the signal processing in the


receiver chain a two-tone test was performed of the ADC at both the behaviorallevel, and at the circuit level.

Behavioral level simulation results in BT mode shows that the linearity of theADC is meeting the specifications, since there are no visible intermodulation prod-ucts in the PSD plot which is shown in Fig. 5.14. The estimated in-band SpuriousFree Dynamic Range (SFDR) is 65 dB. The input signal frequencies were 200 kHzand 210 kHz respectively, and the input signal amplitudes of the two tones were 11dBV below the full scale input voltage.

103

104

105

106

107

-100

-80

-60

-40

-20

0

PSD of output signal from SD ADC, with Hanning window, N=4096

Norm

aliz

ed p

ow

er (

dB

V)

Frequency (Hz)

fin=200kHz, 210 kHz @ 1MSPS

Figure 5.14: Normalized PSD plot from a two-tone test at behavioral level of ADCin BT mode

Circuit level simulation results verifies the performance from the behavioral levelmodeling, and a two-tone test is shown in Fig. 5.15. It can be seen that there is nodegradation to the in-band SFDR, which can be estimated to 67 dBs. The SFDRis higher in the simulation results of the circuit level, since there are no mismatchesapplied to the DAC.

5.6.2 UWB mode

A two-tone test was performed at both behavioral level and circuit level in UWBmode, since the importance of the ADC linearity is similar as in BT mode.

Behavioral level simulation results in UWB mode of a two-tone test is shownin Fig. 5.16, where a SFDR of 38 dBs can be seen. The input signals frequencieswere 50 and 63 MHz, and the input signal amplitudes where 5 dBs below the full-


103

104

105

106

107

-120

-80

-40

0

PSD of output signal from SD ADC, with Hanning window, N=4096

Norm

aliz

ed p

ow

er (

dB

V)

Frequency (Hz)

fin=200kHz, 210 kHz @ 1MSPS

Figure 5.15: Normalized PSD plot from a two-tone test at circuit level of ADC inBT mode

scale ADC input voltage.

105

106

107

108

-80

-60

-40

-20

0

PSD of output signal from Flash ADC, with Hanning window, N=8192

Norm

aliz

ed p

ow

er (

dB

V)

Frequency (Hz)

fin= 50MHz, 63MHz @ 528 MSPS

Figure 5.16: Normalized PSD plot from a two-tone test at behavioral level of ADCin UWB mode

Circuit level simulations verify the performance from the behavioral level model-ing, and the PSD plot of a two-tone test at circuit level can be seen in Fig. 5.17.Input signal frequencies of 60 and 80 MHz were used, with amplitudes of 5 dBVbelow the full-scale ADC voltage. The SFDR increased at circuit level to 41 dBs,since neither the offset voltages to the stages nor the comparators are simulated at


circuit level.

105

106

107

108

109

-70

-50

-30

-10

0

Norm

aliz

ed p

ow

er (

dB

V)

Frequency (Hz)

fin= 60 MHz, 80 MHz @ 528 MSPS

PSD of output signal from Flash ADC, with Hanning window, N=512

Figure 5.17: Normalized PSD plot from a two-tone test at circuit level of ADC inUWB mode

5.6.3 Simulation results from both UWB and BT modes

One of the central measures in the performance of an ADC for wireless communi-cation standards is the Dynamic Range (DR). This performance metric validateswhether the ADC can work of not for the intended application. The DR was mea-sured at both behavioral level and at circuit level.

Behavioral level simulations were performed in both modes of operation usinga single tone test, which input amplitude was swept down from slightly above thefull-scale voltage, until the SINAD of the ADC became negative. The results ofthese simulations are shown in Fig. 5.18, where it can be seen that the DR for theADC is about 30 dBs in UWB mode, and 65 dBs in BT mode. These dynamicranges meets the specifications set in the link budget analysis established earlier.The input signal frequencies were 200 kHz in BT mode, and 53 MHz in UWB mode.The peak SINAD was 63 dBs in BT mode, and 30 dBs in UWB mode, for the sameinput frequencies.

Circuit level simulations were also performed in order to measure the performanceat circuit level. The results are shown in Fig. 5.19, where the DR for BT and UWBmodes are 65 dBs, and 34 dBs (estimated) respectively, where the input frequencywas 102 kHz in BT mode, and 53 MHz in UWB mode. The peak SINAD was31 dBs in UWB mode, and 63 in BT mode, which implies that there still is somemargin for further implementation losses, that may arise in the layout of the ADC.


-80 -70 -60 -50 -40 -30 -20 -10 0

0

20

40

60

SIN

AD

(d

B)

Input signal part of full-scale voltage (dBV)

BT mode, 200 kHz @ 1 MSPS

UWB mode, 53 MHz @ 528 MSPS

Figure 5.18: SINAD versus input signal voltage for both modes of operation frombehavioral modeling

The results for both the DR and the SINAD is higher at circuit level, and thisdepends on the lack of implementation of the DAC nonlinearity at BT circuit level,and amplifier and comparator offsets at UWB level.

-70 -60 -50 -40 -30 -20 -10 0

0

20

40

60

SIN

AD

(d

B)

Input signal part of Full-scale voltage (dBV)

Bluetooth mode, fin = 102kHz@1MSPS

UWB mode, fin = 53 MHz@528MSPS

Figure 5.19: SINAD versus input signal voltage for both modes of operation fromcircuit level simulations

A summary of the ADC performance from circuit level simulations are shown inTable 5.3.

It can be seen from the table that the specifications are met for the reconfigurable


Table 5.3: Simulation results from reconfigurable ADC

Specification UWB BTSampling rate 528 MSPS 1 MSPS

Flash ADC resolution 6 bits 4 bitsSINAD 31 dB @ 53 MHz 60 dB @ 200 kHzSFDR 37 dB 67 dB

Capacitor matching < 1 % < 1 %Sampling clock jitter 20 psec 100 psecPower consumption 180 mW 5 mW

Supply voltage 1.8 VEstimated active area 1.5mm2

Technology 0.18 µm CMOS

ADC that was the target for this case study. This innovative architectural recon-figuration is what facilitated the reconfiguration to include the UWB standard intoreconfigurable ADCs, and to the knowledge of the authors, this is the only reportof such an ADC.

Chapter 6

Circuit Reconfigurability: A Case Study

6.1 Motivation

This case study was performed to investigate circuit reconfigurability in a algorith-mic ADC architecture. Significant previous effort has been spent on investigatingreconfigurability in Σ∆ ADCs for wireless applications e.g. [19, 28, 31, 32, 73,74, 79, 91, 92, 110]. Also reconfigurable combinations of pipelined ADCs and al-gorithmic ADCs have been investigated for wireless applications e.g. [5]. To theknowledge of the author at the time of writing, not much work has investigated thefeasibility of circuit reconfiguration in algorithmic ADCs to cover wireless commu-nication standards, which motivates a study in this area.

The small area of algorithmic ADCs make them appropriate for e.g. wireless sensornodes, which is a powerful unit that can build many types of systems. The wirelesscommunication of these nodes can be used to form Ad-Hoc Bluetooth networks [23],or to transmit data traffic over a UMTS/CDMA2000-1X link [1]. One applicationof the envisioned natural disaster early warning system is shown in Fig. 6.1, wherethe sensor network is monitoring the risk of a landslide. If the network detectsthat the risk of a landslide increases above a certain level, a message is sent tothe telecommunications network over the UMTS link, and a public warning can beissued.

These sensor nodes, or motes are typically small, flexible, and low in power con-sumption. This implies that integrated circuits for motes also should have thesame set of abilities. The small size and the low power consumption of the motesalso drastically reduce the cost of maintenance and the cost of installation. Ablock diagram of a mote is shown in Fig. 6.2, where it can be seen that the moteconsists of: a microprocessor, memory, the power supply, and the multistandard(Bluetooth/CDMA2000-1X) transceiver, with the reconfigurable ADC.

103

104 CHAPTER 6. CIRCUIT RECONFIGURABILITY: A CASE STUDY

M10

M1M3

M2

M4

M5

M8

M7

M6

M9

CDMA2000-1X

Bluetooth link

Mk Mote

Figure 6.1: Sensor nodes in landslide early warning system

The transmitter shown in the figure is a reconfigurable transmitter that can trans-mit either Bluetooth or CDMA2000-1X. Low power transmitters that can be used

6.1. MOTIVATION 105

LNA ADC

Multi-

Band

Generator

Data

processing

Micro-

processor

Ultrasound Temperature

Co

Data out

Bluetooth/CDMA2000

tranceiver

Power

management

RAM and

flash

Power

supply

On-board sensor examples

FEM

PA DAC

I / O

Figure 6.2: Mote block diagram with transceiver

for this purpose have recently been presented [120], which supports the frequenciesfor both Bluetooth and the CDMA2000-1X communication. The power used in thetransmitter should be adjusted to accommodate the needs of the network, in ordernot to waste power anywhere in the network. Software settings controls the com-munication within the network, e.g. what nodes that should communicate, withwhich intervals, which node that should connect with the CDMA2000-1X link, etc.

The receiver shown in Fig. 6.2 is a SDR receiver, that can receive both Bluetoothand CDMA2000-1X, but not at the same time. The operation of the receiver willalso be controlled by the network in such a way that none of the motes are requiredto receive both of the standards at the same time. The ADC in the receiver chainis not only used to receive these two standards, but also as a front-end for theon-board sensors. This make the ADC a central component on the mote. Small,reconfigurable, and low-power ADCs for this application have previously been pre-sented e.g. [98], where the bandwidth and dynamic range are not sufficient to coverwireless communication standards.

If a reconfigurable, small and low-power ADC is to be designed for motes withthis reuse, the specifications for this component needs to be established. Assumingthat the mote should be able to communicate in an Ad-Hoc Bluetooth network e.g.as shown in Fig. 6.1, or with CDMA2000-1X/UMTS over a 3-G data network, the


ADC needs to be designed to fulfill the requirements of these standards. It alsoneeds to fulfill the requirements of the on-board sensors that are connected to themote.

6.2 The reconfigurable ADC specifications for Bluetoothand CDMA2000-1X

The Bluetooth standard operates in the 2.4 GHz ISM band, with a frequency hop-ping scheme. The channel bandwidth is 1 MHz, and for an I/Q receiver the ADCsampling rate can be decreased to 1 MSPS. The dynamic range requirements for anADC for a Bluetooth Zero-IF receiver was established earlier in Section 5.2, whereit was found that 60 dBs of dynamic range would be sufficient. This has also beenvalidated by other reports of ADCs for Bluetooth receivers [28, 51, 115].

For the CDMA2000-1X mode, the ADC specifications have to be established aswell. CDMA2000-1X operates at several frequencies, e.g. in band at 800 MHz in theUS. The CDMA2000-1X communication is using 1.25 MHz channel spacing, with aCode Division Multiple Access (CDMA) modulation deviate called DS-CDMA [2].The specifications of the ADC in the back of the receiver chain needs to take thefollowing parameters into account:

• The highest ADC input power in any operating condition

• The gain step size in the receiver chain

• The SNRmin required to demodulate the signal

• Margin for the quantization noise

There are two issues with the CDMA2000-1X radio: firstly it is a frequency du-plexed system, which means that the transmitter is active at the same time as thereceiver; and secondly there is a strong 1-G mobile system blocker only 900 kHzaway from the receive band [120]. Assuming that the deployment of the sensor sys-tem can be made in an environment where the 1-G mobile system is not as strong,then the link budget for the receiver can be relaxed, which relaxes the power con-sumption of the receiver.

The highest ADC input power in any operating condition is decided bythis strong 1-G phone system blocker. With the close distance to the receive band,all of the signal power can pass un-filtered through the chain, and it has been re-ported to be up to 71 dBs higher than the smallest CDMA2000-1X signal afterthe signal chain [120]. If the mote that is communicating over the CDMA2000-1Xlink can be placed in such a way that this blocker is only 40 dBs over the smallestCDMA2000-1X signal, then a low-power solution could be possible. This is notan unlikely scenario, since much of this 1-G system has been replaced with the

6.2. THE RECONFIGURABLE ADC SPECIFICATIONS FOR BLUETOOTH ANDCDMA2000-1X 107

CDMA2000-1X coverage, which can be seen with a coverage locator for one of themain cellular providers in the US [111].

The gain step size in the receiver chain has been reported to be typically10 dBs is a normal implementation in a receiver chain.

The SNRmin required to demodulate the signal for the CDMA modula-tion is low, since the signal itself is recovered by the digital processing from thespectrum. This implies that the ADC should not degrade the noise floor in thereceived band. An extra 5 dBs of margin is added to accommodate this.

Margin for the quantization noise of 5 dBs have been assumed for other appli-cations, due to the larger amplitudes in the quantization noise compared to thermalnoise [11].

Total required dynamic range for this CDMA2000-1X ADC sums up to beat least 60 dBs.

Dynamic ranges for ADCs for CDMA2000-1X receivers have been reported to befrom 55 dB up to 85 dB [12, 110, 120]. The bandwidth of the CDMA2000-1X systemis 1.25 MHz, which can be covered in an I/Q receiver by an ADC with a 1.25 MSPS.

This ends up with a ADC specification of 60 dB dynamic range for both stan-dards, over 500 kHz bandwidth in Bluetooth mode, and 625 kHz bandwidth inCDMA2000-1X mode. The same ADC, over similar or lower bandwidths can alsobe used for sensors, e.g. sub 100 kHz ultrasound crack detection in medium-densitymaterials, or accurate temperature or vibration sensors.

In order to determine the architecture of the required ADC a number of factorshad to be considered. The suitable ADC architectures that usually can providedynamic range of 60 dBs over a bandwidth up to a few MHz are pipelined, algo-rithmic, Σ∆, and SAR ADCs [4, 5, 36, 75]. The performance of the ADCs from[4, 5, 36, 75] has been summarized, and is shown in Fig. 6.3.

The FOM given by Equation (3.10) is calculated for these ADCs, and it is shownin Fig. 6.4 how effective these ADCs are. All of the ADCs in the figure have 60dBs of dynamic range or more, and the sampling rates are of 1 MSPS or higher.In order to compare all the ADCs shown in Fig. 6.4, they can be moved down tothe 1 MSPS line, in the direction indicated in the figure, assuming that no scalingis used for the resolution of the ADCs. Looking back to Equation (3.10), one canunderstand that if the sampling rate decreases by a factor of 10, then the figureof merit increases with a factor of 10, since they are inversely proportional. Fromthe figure it can be interpreted that the SAR have the best FOM, secondly thealgorithmic and the one Σ∆ ADC shown, and the pipelines are most inefficient for


fsample (Hz)

DR (dB)

20

60

100

103 105 107 109

SA

R

Alg

ori

thm

ic

Pip

elin

e

Sigma-Delta

140

Algorithmic ADCs [Anderson2005, Gustafsson2008, Muthers2004]

Figure 6.3: Overview of the performance of Pipelined, Algorithmic, Σ∆ and SARADCs

this application.

10-1

100

101

10210

5

106

107

108

109

Sam

ple

ra

te (

Hz

)

EQ (pJ/conv)

Sigma Delta

SAR

Pipeline

Algorithmic

EQ

versus sampling rate for different topologies

Muthers2004

Gustafsson2008

Anderson2005

Improvement

Figure 6.4: Overview of the performance of Pipelined, Algorithmic, Σ∆, and SARADCs

For the area of the ADC, which also is an important aspect, the algorithmic ADCsare the smallest for this resolution. Second is the Σ∆ and the pipelined ADCs.

6.3. ALGORITHMIC ADC 109

The SAR ADCs are the largest, since the DAC grows exponentially with the ADCresolution.

In order to choose one of these ADCs for this wireless sensor node, not only thefeatures of power consumption and area are important, but also the reconfigurabil-ity inherent in the ADC architectures.

The selection in the end was the algorithmic ADC, mainly since the architecturefacilitates a smaller area compared to SAR, and a lower power consumption andmore flexibility than pipelines. What is the flexibility of an algorithmic ADC?

6.3 Algorithmic ADC

The general block diagram for an algorithmic ADC is shown in Fig. 3.25, and itwas explained in detail in Section 3.5. A more detailed block diagram of this algo-rithmic ADC is shown in Fig. 6.5, where it can be seen that the double capacitortechnique, and the double capacitor sampling techniques are used, to remove theextra Sample and Hold circuit shown in Fig. 3.26.

The references for the flash ADC shown in Fig. 6.5 are generated with a resistorladder. In the figure there are two ladders shown, but only one ladder is imple-mented in the real implementation, to save power. This is possible with tuning ofthe threshold voltages of the comparators in the ADC. The implemented design isfully differential, but in Fig. 6.5 it is shown single ended for simplicity. Many ofthe switches are left out, to keep the block diagram simple.

6.3.1 Flexibility in algorithmic ADCs

To implement flexibility in this algorithmic architecture, capacitor scaling and timescaling was implemented, as explained in Section 3.5.1, but they were implementedas variable capacitor scaling, and variable time scaling, in order to create circuitlevel reconfigurability in the ADC. The possible resolution of the time and ca-pacitance scaling is a limiting factor, where the time and capacitance only canbe changed in unit steps. The unit time step is a trade-off between accuracy onone hand, and power consumption and complexity of the digital part required todrive the ADC, on the other. The unit capacitance is also a trade-off between reso-lution on one hand, and complexity, capacitor array size and matching on the other.

An increase in bandwidth of 25 % was needed for a given sampling rate, with thepreserved dynamic range in order to reconfigure the ADC from Bluetooth mode toCDMA2000-1X mode. In order to investigate if this was feasible for an algorithmicADC, a behavioral model was developed in Matlab/Simulink.


Statemachine with

variable clock generation

VDAC,i

Vres,i-1

+

-

C1G.C1p1

p1

p1

p3

p3

2.5

bit

s

p1

Strobe @ p2

ADC

DAC

-Vres,ip4

psamp

Vin

pcycle

G.C2

p23

p23

C2

p23

p23

R

R

R

R

R+

-

+

-

+

-

+

-

+

-

...

...

...

...

Ther

mom

eter

to b

inar

y c

onver

sion

R

R

R

R

R

R

...

...

...

...

VDAC select

Error correction

Digital controlNtot bits

G.C3

ps1

ps1

C3

ps1

ps1

Vin

Second capacitor set

for double sampling

Figure 6.5: Detailed block diagram of algorithmic ADC

6.4 Behavioral modeling of algorithmic ADC

The method of implementing accurate high-level Matlab/Simulink behavioral mod-els based on circuit parameters has been used for Σ∆ ADCs [64], and have alsobeen proven for other ADC architectures [37]. The same approach has been usedfor the algorithmic ADC to establish circuit parameters, which reduces the circuitdesign time, and the time-to-market.

There are a number of non-idealities that have to be regarded when an accuratebehavioral model is built for an algorithmic ADC. The most important ones are:

6.4. BEHAVIORAL MODELING OF ALGORITHMIC ADC 111

limited amplifier DC gain, limited amplifier bandwidth, limited amplifier slew-rate,amplifier thermal noise, the minimal sampling capacitor used, capacitor set mis-match, and comparator offset.

Most of these non-idealities are associated to the amplifier, and to accurately modelthe effects of time- and capacitance-scaling a new behavioral model is needed. Thismodel should model different settling times and bandwidths during different cyclesof operation.

The step response of a multiple pole amplifier depends on the phase margin, thegain-bandwidth product and the slew rate. The error at the end of a settling phasealso depends on these parameters, and three cases can be identified, which areshown in Fig. 6.6, for a low- and high- phase margin case.

amp (V)

t (sec)

Slew rate limitedSlew rate and bandwidth limitedBandwidth limited

E1E2E3

Figure 6.6: Amplifier step response depending on non-idealities

The error in the amplifier step response for a high-phase margin case can be: E1

if limited by bandwidth, E2 if limited by both bandwidth and slew rate, and E3 iflimited by slew rate only.

The error E1 is given by

E1 = Vin − Vine−tN /τN , (6.1)

where Vin is the input voltage, tN is the time allowed for settling in this phase,and τN is the time constant given by the gain-bandwidth of the amplifier for theN:th cycle, considering the bandwidth determined by the applied capacitance. Theerror E2 is given by

E2 = Vin −(

tsSRN + (Vin − tsSRN ) e−(tN−ts)/τN

)

, (6.2)

where Vin is the input voltage, tN is the time allowed for settling in this phase, ts isthe time the amplifier is in slew rate limitation, SRN is the amplifier slew rate, andτN is the time constant of the amplifier gain-bandwidth in the N:th cycle. Finallythe error E3 is given by

E3 = Vin − tNSRN , (6.3)


where Vin is the input voltage, tN is the time allowed for settling in this phase,and SRN is the amplifier slew rate for the N:th cycle.

Short amplifier settling times is the key parameter that can allow a high-speedalgorithmic ADC to be designed, since the amplifier settles a number of times dur-ing the conversion. Three amplifier settling conditions are shown in Fig. 6.6, whereit can be seen that the gain-bandwidth limited response can provide the fastestsettling times. Naturally the power consumption of a gain-bandwidth limited sys-tem will be higher, compared to a slew-rate limited system, for the same capacitiveload. It can further be seen in Fig. 6.6 that if errors can be tolerated from theamplifier settling, a lower phase margin can be beneficial for the settling times. Adeliberate selection of a lower phase margin can be beneficial from two perspectives:the power consumption of the amplifier, and the time required for the amplifier toreside within the desired tolerances. In Fig. 6.7, the settling times are shown for anamplifier with different phase margins, comparable to the one needed in this design,to reside within 2 mV from the desired value of 1 V. In this figure it can be seenthat the time difference, between the safe choice and the over- and under-dampedresponses of the amplifier is large. The optimal solution would be the criticallydamped solution, that would have more overshoot than the safe choice shown inthe figure.

5 10 15 20 25 30

992

996

1000

1004

1008

Time (nsec)

Outp

ut

volt

age

(mV

)

Under damped

Stable/safe choice

Over damped

T1T3T2

Figure 6.7: 2-pole amplifier response with different phase margins

By comparing the times needed for the three solution in Fig. 6.7 to settle withinthe tolerances, it can be seen that significant time can be saved if proper care istaken to the phase margin in the design. It is important to remember that this isonly a model of the amplifier, where the effect of all the non-dominant poles andzeroes are replaced with an equivalent pole. The final verifications have to be madeat circuit level.

From the behavioral simulations of the ADC model in Matlab/Simulink, it wasdecided that the capacitance should be varied in two levels. The full capacitancefor the first cycles, and an option of lower capacitance for the later cycles. Onlytwo levels were selected to decrease the complexity of the layout. The smaller ca-

6.5. CIRCUIT IMPLEMENTATION OF ALGORITHMIC ADC 113

pacitance could be used in iterations 3, 4 and 5 in the model. It was also foundthat the settling times of cycles 2, 3, 4, and 5 could be variable, and only two set-tling time lengths were implemented for cycles 2 and 3, and four different lengthswere implemented for cycles 4 and 5. It was uncertain how well this would fit withthe circuit level implementation, but this could establish that 35 % sampling rateincrease could be achieved, compared to the un-scaled version. This range wascovered without any degradation to the ADC SINAD. Furthermore, specificationswere found through these simulations to the central non-idealities, and they arelisted in Table 6.1.

Table 6.1: Design specifications

Design object SpecificationAmplifier DC gain 62 dBVAmplifier 3-dB bandwidth 800 kHzAmplifier slew rate 100 V/msecAmplifier Thermal noise 500 nV, RMSMinimal sampling capacitance 1 pFComparator offsets 10 mV

These specifications were used to implement VerilogA/AHDL models in the Ca-dence environment in order to re-validate the system level specifications achievedfrom the Matlab/Simulink behavioral models. This created a platform in the Ca-dence environment that facilitated a rapid transistor level implementation.

6.5 Circuit implementation of algorithmic ADC

As shown in Fig. 6.5, the central blocks of the algorithmic ADC are: the amplifier,comparators with programmable thresholds, capacitor arrays and switches resistorladder with ADC and DAC reference voltages, the variable state machine, the ther-mometer to binary decoder, the DAC switch selector a.s.o.

In addition to these ADC core blocks, support electronics were needed such asthe voltage and current references. The variable state machine needed 35 statesto control the operation of all the settings of the variable capacitance, the variablesettling times, the double capacitor technique, and the double sampling capacitortechnique, described in Section 3.5.1.


6.5.1 Amplifier design

The most important block in this algorithmic ADC is the amplifier, that neededto support different capacitive loads, with optimum phase margin without compro-mising the settling accuracy. The implemented amplifier is a telescopic amplifier,due to the low bias currents needed compared to the folded cascode topology. Theamplifier is shown in Fig. 6.8, where it can be seen that a single Gain-Boosting(GB) amplifier is used to increase the DC gain. A switched-capacitor CommonMode FeedBack (CMFB) is implemented to establish the output DC point. The

AVSS

bias2

inninp

AVDD

outpoutn

M2 M3

M1

M10 M11CMFBCMFBbias1 bias1

M9M8

M4 M5

M6 M7bias2bias2

+

+

-

-

GB

amp

Figure 6.8: Telescopic amplifier with gain boosting

GB amplifier was implemented as a folded cascode amplifier also with a switched-capacitor CMFB. The implemented DC gain is 62 dB, with a 3-dB bandwidth of800 kHz, in the worst process corner, which meet the specifications listed for theamplifier in Table 6.1. The current in the amplifier was set to 1 mA, and 330 µAin the GB amplifier. The drawback of the telescopic topology is that the inputDC voltage is different from the output DC voltage, which makes the reset of theamplifier more difficult. Low-impedance references are needed to efficiently removeall the residual charge between the input terminals, to reduce the amplifier offset.

6.6 Simulation results

The reconfigurable algorithmic ADC can cover the requirements for both the Blue-tooth and CDMA2000-1X standards. These requirements are close to the edges of


the 30 % ADC flexibility for one clocking frequency, that was reached at circuitlevel. A loss of 5 % in ADC flexibility was due to the extra phase margin needed atcircuit level, since the higher order poles reduce the phase margin more than in theimplemented equivalent pole model [45]. The dynamic range of the ADC has beendetermined at behavioral level, for both Bluetooth and CDMA2000-1X modes, andthe simulation results are shown in Fig. 6.9. It can be seen that the maximumSINAD is 58 dB for both modes, for an input frequency of 110 kHz. The dynamicrange is 71 dBs for Bluetooth mode, and 73 dBs in CDMA2000-1X mode.

-80 -70 -60 -50 -40 -30 -20 -10 0

0

20

40

60

Input signal (dBV)

SINAD

(dBV)

BluetoothCDMA2000-1X

Figure 6.9: Dynamic range simulation results from behavioral model for Bluetoothand CDMA2000-1X modes

A Power Spectral Density (PSD) plot from the behavioral level model, in Bluetoothmode is shown in Fig. 6.10, where the SINAD is approximately 58 dB, for a fullscale input signal at 301 kHz, sampled at 1.25 MSPS. A strong DC component canbe seen in the spectrum which can be filtered out.

103

104

105

106

fin = Vfullscale @ 301 kHz

-100

-80

-60

-40

-20

0

Norm

aliz

ed p

ow

er (

dB

)

Frequency (Hz)

Figure 6.10: Power spectral density plot of a full scale input in CDMA2000-1Xmode from behavioral simulation

One 256-point spectrum takes about 1 second to simulate at behavioral level, and


approximately 300 hours at circuit level, on the same computer platform. In spiteof the long simulation times, one PSD plot was successfully created, and it is shownin Fig. 6.11. Here the SINAD is 58 dB, for a full scale input signal at 301 kHz,sampled at 1.25 MSPS.

104

105

106

-100

-80

-60

-40

-20

0

Norm

aliz

ed p

ow

er (

dB

V)

Frequency (Hz)

fin= Vfullscale @ 301 kHz

Figure 6.11: Power spectral density plot of a full scale input in CDMA2000-1Xmode from schematics

The simulation times makes further validation at circuit level as well as at lay-out level difficult, and the results of only a few points are used to validate theperformance.

6.7 Silicon implementation

The ADC was implemented in a 0.35 µm double poly, 4 metal, CMOS processwith both Metal-insulator-Metal (MiM) and poly-poly capacitors, and high-resistivepoly.

The chip micrograph is shown in Fig. 6.12, and it measures 3.2 mm2, of whichthe active area is about 1 mm2, including the voltage and current references. Thesubstrate is divided into two sections, the analog part and the digital part. Theanalog domain has one power supply that is connected to the separated pad-ringin the lower right corner. The digital-pad ring has two power supplies, one thatsupplies the pad-ring digital buffers, and the second supplies the digital part andthe comparators on the chip. All of the supplies are decoupled with three differentexternal capacitors, to reduce the power supply noise. ESD protection is appliedto all of the pads, and special consideration is taken to the analog input pads.

The chip was packaged in a tape-top JLCC 44 housing, to allow on-chip prob-

6.8. MEASUREMENTS 117

1.6 mm

1.6

mm

Figure 6.12: Die micrograph

ing of testpads. These testpads were placed at the voltage references, the currentreference, and at comparator outputs.

6.8 Measurements

6.8.1 Measurement setup

The measurement results of this design depend on how noise coupled into the de-sign, internally on the chip, to the chip from the supplies and the printed circuitboard (PCB), and also from the measurement equipment to the PCB and chip.

The used measurement equipment was a single-ended signal generator with 65 dBSpurious Free Dynamic Range (SFDR), with a maximum output signal frequencyof 200 kHz. The single-ended to differential conversion was performed with a lowfrequency center fed transformer, that also allowed the DC points of the inputs tobe set with a voltage source. All of the in and outputs to this transformer weredecoupled with large capacitors to decrease the noise.


The ADC clock was driven by a square waveform generator that could generatea clock signal up to 100 MHz, which was also the speed limitation of the on-chipdigital logic, i.e. the state machine, the DAC, and correction logic.

The PCB was designed for three power supply domains, with decoupling capac-itors placed as close to the chip as possible. Individual voltage sources were usedfor the three supplies. A photograph of the PCB is shown in Fig. 6.13.

Figure 6.13: Photo of the test Printed Circuit Board for the characterization of thealgorithmic ADC

All the cables going to the PCB were either twisted or coaxial, in order to reducethe coupled noise to the PCB. The grounds of the sources were connected togetherto reduce the ground noise.

A Logic Analyzer with a 65 kByte memory depth was used to store the digitaloutputs from the ADC, which allows 65536 point spectral analysis of the measure-ment data. The data was imported into Matlab, where the FFT was created withthe use of a Hanning window of 65536 element length.

6.8.2 Measurement results

The dynamic performance of the ADC was characterized, since the operation inBluetooth mode and CDMA2000-1X mode, as well as ultrasound and vibrationsmeasurements put constraints to the behavior in frequency domain.


The first measurement target was to verify that the sought 30 % speed recon-figuration could be reached with preserved SINAD. A 200 kHz input sinusoidalsignal was applied to the ADC, with a 65 dB SFDR. The ADC clock was generatedwith a 50 MHz square wave. The result is shown in Fig. 6.14, where it can beseen that the full 30 % range can be achieved. The lowest sampling rate that canbe reached with this clock frequency is when all the cycles are set to their longestlength. With this configuration the sampling rate was 1.12 MSPS. When all thecycles were programmed to have their shortest duration, a maximum SINAD of 60dB was reached at 1.4 MSPS. This results verify that all the settings of the timescaling worked in the ADC. Furthermore the capacitance scaling did not degradethe performance if it was applied during cycles 4 and 5.

1.1 1.2 1.3 1.40

20

40

60

Sampling rate (MSPS)

Max

SIN

AD

(dB

V)

Figure 6.14: SINAD of ADC over range of reconfiguration

Secondly the dynamic range needed to be verified for both Bluetooth and CDMA2000-1X modes. A 200 kHz input signal was applied to the ADC with input amplitudesfrom -62 dBV below the full scale 2 V differential input to 1 dBV above. TheSINAD was measured in a number of points across this range for a 65536 pointFFT spectrum, processed with a Hanning window, and the results are shown inFig. 6.15. The ADC clock frequency was 50 MHz. A maximum SINAD in Blue-tooth mode was measured to 59 dBs, with a full scale input voltage. The maximumSINAD for CDMA2000-1X mode was measured to 60 dBs. The dynamic range wasfound to be 58 dBs in both modes of operation.

Finally the SFDR was measured, by visual inspection of a PSD plot from a 200 kHzinput signal at the full scale 2 V differential Voltage, sampled at 1.25 MSPS witha 50 MHz ADC clock frequency. The 65536 point spectrum is shown in Fig. 6.16,


-70 -60 -50 -40 -30 -20 -10 0 10

0

20

40

60

Part of Vin (dBV)

SIN

AD

(d

B)

SINAD@1MSPS

[email protected]

Figure 6.15: Dynamic range measurement with 200 kHz input signal

where a SFDR of 68 dBs can be seen.

101

102

103

104

105

106

-150

-100

-50

0

Norm

aliz

ed p

ow

er (

dB

V)

Frequency (Hz)

fin= Vfullscale @ 200 kHz

Figure 6.16: PSD plot of a 200 kHz input signal in CDMA2000-1X mode

The performance summary from the measurements of the ADC are shown in Ta-ble 6.2. Here it can be seen that the performance requirements for both the Blue-tooth and the CDMA2000-1X wireless communication standards are met. Further-more, it can be seen that this is achieved at the low power consumption of 10 mW.


Table 6.2: Performance summary from measurements of reconfigurable algorithmicADC

Specification ResultClock speed < 100 MHz

Sampling rate 1.0 - 1.3 MSPS@ 50 MHz clock

SINAD 60 dB @ 200 kHzSFDR 65 dB @ 200 kHz

Power consumption 10 mWSupply voltage 3.3 V

Active area 1.0 mm2

Technology 0.35 µm CMOS

Chapter 7

Conclusions

The implementation of the wireless pocket telephone continues to expand into newfields of applications, and the limitations of this development are the cost and powerconsumption of the electronics. The launch of the integrated Software Defined Ra-dio, that covers all the available wireless communication standards is still a bitdistant in the future, even if there are products today that claim that they havereached the goal. Challenges arise with the new high frequency allocated bands,which complicates the receiver design. One of these standards is the UWB stan-dard, which will provide very high data communication rates. These data rates willfacilitate a completely new use of the wireless link, and development to integratethis standard into products is a desired goal for many multinational companies to-day. This standard will, as a first step, be integrated into multistandard commercialproducts with the addition of another complete transceiver, which is adding costand power consumption.

This thesis makes a contribution in showing that this does not have to be thecase. With the use of smart design techniques, such as with a multistandard Soft-ware Defined Radio receiver, implemented with reconfigurable receiver chains, thearea and power consumption can be reduced.

The first part of the thesis contains four chapters that provide an introductionto the area, where the first chapter of the thesis gave a short historical overviewof the development of the communications industry. It concluded that there is astrong need for further development of reconfigurable electronics to reduce the priceand power consumption of modern multistandard wireless applications.

The second chapter provides the necessary introduction into the applications, wherewireless receivers are covered from the past to the present, with future trends. Thechapter is concluded by introducing the Analog to Digital Converters used in recon-figurable receivers, and the Analog to Digital Converter specifications for Zero-IF

123

124 CHAPTER 7. CONCLUSIONS

multistandard receivers.

The third chapter provides a solid background in both Analog to Digital Conver-sion, and Analog to Digital Converter architectures with a high degree of inherentreconfigurability. Design approaches to implement multistandard Analog to DigitalConverters are discussed, and it is concluded that reconfigurable Analog to DigitalConverters is the best approach.

The forth chapter provides analysis of reconfigurability in Analog to Digital Con-verters, and two levels of reconfiguration are identified, as architectural level andcircuit level reconfiguration. Two examples from the literature are given at eachlevel of reconfigurability, and the two case studies are briefly introduced.

The second part of the thesis presents two case studies on reconfigurable Ana-log to Digital Converters, that use novel techniques to maximize the flexibility ofthe Analog to Digital Converters.

The first case study shows how architectural reconfigurability can be used to designan Analog to Digital Converter that can cover the Bluetooth and the UWB com-munication standards for Wireless Personal Area Network applications. The spec-ifications for the two modes of operation, for both case studies are found throughanalysis of the wireless communication standard documents and reported receiverchains from the literature. An Analog to Digital Converter implementation thatcombines the Sigma Delta and flash architectures is proposed, which meets therequirements of a Zero-IF Bluetooth/UWB Software Defined Radio receiver. Thisreconfigurable Analog to Digital Converter is to the knowledge of the author thefirst Analog to Digital Converter that can be reconfigured to cover the UWB stan-dard, and another low-data rate wireless communication standard.

The second case study is focused on sensor node applications, where an Analogto Digital Converter, which can be used for many purposes is proposed. The mainpurpose of this Analog to Digital Converter is to cover the needs of a Bluetooth /CDMA2000-1X transceiver, and secondly to cover the need of the on-board sensorinterfaces. The methods to increase the performance of algorithmic Analog to Digi-tal Converters are implemented in a way to also achieve a very high reconfigurabilitywith simple software settings. It is shown that the implemented reconfigurability issufficient to meet the requirements of two wireless communication standards. ThisAnalog to Digital Converter has been manufactured, and the measurement resultsshow that the requirements of both the Bluetooth and CDMA2000-1X standardscan be met.

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