15740 - Computer Architectures Francisco Pereira João Pedro Sousa

Reconfigurable computing

Papers:

[Goldstein et al] PipeRench: A Coprocessor for Streaming Multimedia Acceleration

[Razdan & Smith] PRISC: A High-Performance Microarchitecture with PFUs

[Cardoso & Vestias] Architectures and Compilers to Support Reconfigurable Computing

15740 - Computer Architectures Francisco Pereira João Pedro Sousa

Terminology

FPGA Field Programmable Gate Array

PFU Programmable Functional Unit

ISA Instruction Set Architecture

PE Processing Element

PRISC PRogrammable Instruction Set Computer

RPU Reconfigurable Processing Unit

15740 - Computer Architectures Francisco Pereira João Pedro Sousa

Challenge 1

Workloads submitted to processorsinclude more and more simple calculationson very large quantities of data.

Multimedia applications, video streaming…

15740 - Computer Architectures Francisco Pereira João Pedro Sousa

Challenge 1

Assumptions of general purpose processing:

The processor reads more instructions than data elements

processors are optimized for high instructions bandwidth

(pre-fetching, branch prediction)

Data comes in fixed sized, wide words

32 or 64 bits are not uncommon

15740 - Computer Architectures Francisco Pereira João Pedro Sousa

Challenge 1

Characteristics of data stream processing :

Data comes in large quantities of variable, small width elements

12 bits, 7 bits…

A single transformation is to be applied to all the data elements

That transformation is domain specific and is likely torequire several instructions on a general-purpose processor

15740 - Computer Architectures Francisco Pereira João Pedro Sousa

Challenge 2

Performance critical applicationsoften rely on a reduced number of functions being executed frequently

Can we support those in hardware?

15740 - Computer Architectures Francisco Pereira João Pedro Sousa

Reconfigurable computing

Papers:

[Goldstein et al] PipeRench Challenge 1

[Razdan & Smith] PRISC Challenge 2

[Cardoso & Vestias] Challenge 2

15740 - Computer Architectures Francisco Pereira João Pedro Sousa

Idea

Design hardware that can be configuredat run time to support:

Complex transformations of datain a single clock cycle

Variable data widths (challenge 1)

15740 - Computer Architectures Francisco Pereira João Pedro Sousa

Approaching the SolutionG

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15740 - Computer Architectures Francisco Pereira João Pedro Sousa

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15740 - Computer Architectures Francisco Pereira João Pedro Sousa

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15740 - Computer Architectures Francisco Pereira João Pedro Sousa

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15740 - Computer Architectures Francisco Pereira João Pedro Sousa

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15740 - Computer Architectures Francisco Pereira João Pedro Sousa

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15740 - Computer Architectures Francisco Pereira João Pedro Sousa

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15740 - Computer Architectures Francisco Pereira João Pedro Sousa

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15740 - Computer Architectures Francisco Pereira João Pedro Sousa

So, why don’t I have one yet?

Shortcomings of FPGAs [Goldstein et al]:

Configuration time – 100s of microsecs to 100s of millisecs

Forward compatibility – must be redesigned every generation

Compilation time – synthesis, placement and routing

Logic granularity – designed to replace random logic

Hard constraints – the hardware image must fit

15740 - Computer Architectures Francisco Pereira João Pedro Sousa

Comparison in a typical application

15740 - Computer Architectures Francisco Pereira João Pedro Sousa

PRISC performance

Applicability and application speedup

15740 - Computer Architectures Francisco Pereira João Pedro Sousa

PipeRench performance

Performance on benchmark kernels:

15740 - Computer Architectures Francisco Pereira João Pedro Sousa

PipeRench performance

Performance on applications:

15740 - Computer Architectures Francisco Pereira João Pedro Sousa

Conclusion

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PipeRench PRISC