Int. J. Electron. Commun. (AEÜ) 98 (2019) 174–180

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International Journal of Electronics andCommunications (AEÜ)

journal homepage: www.elsevier .com/locate /aeue

Regular paper

Reconfigurable chaotic pseudo random number generator based on FPGA

https://doi.org/10.1016/j.aeue.2018.10.0241434-8411/� 2018 Elsevier GmbH. All rights reserved.

⇑ Corresponding author.

Ahmed A. Rezk a, Ahmed H. Madian d,a,⇑, Ahmed G. Radwan c,a, Ahmed M. Soliman b

aNISC Research Center, Nile University, Cairo, Egyptb Electronics and Comm. Eng. Dept., Cairo University, EgyptcDept. of Engineering Mathematics and Physics, Cairo University, EgyptdRadiation Engineering Dept., NCRRT, Egyptian Atomic Energy Authority, Egypt

a r t i c l e i n f o

Article history:Received 25 July 2018Accepted 17 October 2018

Keywords:PRNGFPGAChaosReconfigurableEncryptionCascaded cipher

a b s t r a c t

This paper presents an FPGA Pseudo Random Number Generator (PRNG) that is based on the Lorenz andLü chaotic systems. These two systems are used to generate four different 3D chaotic attractors. Oneattractor is generated from Lorenz while the other three attractors are generated from Lü. The outputattractor of the proposed PRNG can be reconfigured during real time operation using an efficient hard-wired shifting and multiplexing scheme. Furthermore, in order to exploit the proposed reconfigurationfeature, the proposed PRNG has been embedded in an FPGA cascaded encryption processor that ciphersthe input data from one up to four times successively. In each ciphering operation the PRNG is set to anew configuration and is initialized according to a part of the encryption key. The size of the encryptionkey can be varied according to the number of required ciphering operations. The proposed PRNG has beenrealized using VHDL, synthesized on Xilinx using the FPGA device XC5VLX50T, and analyzed usingMATLAB and the NIST statistical suite. The proposed PRNG has utilized only 1.4% from the FPGA’s slices,achieved an operating frequency up to 78 MHz, and successfully passed all the NIST statistical tests.

� 2018 Elsevier GmbH. All rights reserved.

1. Introduction

Chaos theory has been widely used in the field of digital com-munication [1,2], motor control [3,4], Pseudo Random NumberGenerators (PRNGs) [5,6], and data encryption [7–10].

The Lorenz [11] and Lü [12] chaotic systems have been utilizedin a lot of applications [1,21]. Each system is modeled by threeOrdinary Differential Equations (ODEs) that represent the rate ofchange of the system’s variables. These ODEs can be solved usingnumerical methods; such as Euler, mid-point, or 4th order RungeKutta [17]. Furthermore, each system has certain parameters thatlead to the desired chaotic behavior [12]. One way to view thischaotic behavior is to draw a 3D plot that shows how the solutionsof the system’s variables evolve. This 3D plot is called the attractor.The Lorenz system can lead to only one 3D chaotic attractor whilethe Lü system can lead to three different 3D chaotic attractors [12].

A lot of analog [13–16] and digital [17,18] circuits have beenused to realize different chaotic systems. The main advantage ofthe digital chaotic circuits is that the generated chaotic numbersare insensitive to the environmental condition or the processvariation.

Chaotic systems are employed in cryptographic applicationsdue to two main reasons. The first reason is that the output of

any chaotic system is very sensitive to the system’s initial condi-tion. The second reason is that the chaotic output can be used toprovide pseudo random numbers. Hence, in chaos based encryp-tion applications, the system’s initial condition is set according tothe encryption key, and then the generated pseudo random num-bers are used to cipher the input data [8].

Two techniques are used in the encryption process, the blockciphering; such as the Advanced Encryption Standard (AES), andthe stream ciphering; such as the RC4 and A5/1 [8]. The blockciphering provides high security performance at the expense ofincreasing the hardware complexity and reducing the system’sthroughput. On the other hand, the stream ciphering technique,which simply XOR’s the input data with a stream of pseudo ran-dom numbers, provides high throughput and low implementationarea at the expense of lowering the security performance. TheEncryption process can be performed using Hardware (HW) orSoftware (SW) solutions. The HW solution; such as the FPGAs,are mainly used to improve the system’s throughput [9,22].

This paper presents an FPGA PRNG that is based on the Lorenzand Lü chaotic systems. The similarities between the ODEs ofLorenz and Lü have been exploited in order to build a genericstructure that fits both systems. Moreover, the parameters of thisgeneric structure can be reconfigured during real time operationin order to switch between the Lorenz attractor and three differentLü attractors. This reconfiguration feature is realized using an

Table 1The numerical solution of Lorenz and Lü.

Euler’s method ODE Lorenz Lü

xiþ1 ¼ xi þ h: _x _x aðyi � xiÞ aðyi � xiÞyiþ1 ¼ yi þ h: _y _y cxi � yi � xizi cyi � xiziziþ1 ¼ zi þ h: _z _z xiyi � bzi xiyi � bzi

Table 2The configuration scheme of the proposed chaos generator.

Config. System Euler’s step size

00 Lorenz (a, b, c) = (8, 2, 32) 2�8

01 Lü (a, b, c) = (32, 4, 16) 2�8

10 Lü (a, b, c) = (32, 4, 12) 2�8

11 Lü (a, b, c) = (32, 4, 20) 2�8

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efficient hardwired shifting and multiplexing scheme. Further-more, an FPGA cascaded encryption processor, which is based onthe proposed reconfigurable PRNG, has been implemented in thispaper. The proposed encryption processor can encrypt the inputdata up to four times successively, each time using a differentPRNG configuration. The encryption operation is achieved by XOR-ing the data with PRNG’s output. The initial seed of each PRNG con-figuration is set according to a part of the encryption key. Thus, thesize of the encryption key can be varied according to the number ofciphering operations. The paper is organized as follows. Section 1presents the introduction. Section 2 presents the digital implemen-tation of the proposed PRNG. Section 3 presents the PRNG’s synthe-sis results, NIST statistical tests, and comparison with previouswork. Section 4 presents the proposed FPGA encryption system.Section 5 presents the conclusion.

2. The proposed reconfigurable PRNG

The proposed reconfigurable PRNG is based on the Lorenz andLü chaotic systems. The ODEs, _x, _y, and _z, of these chaotic systemsare summarized in Table 1 where a, b, and c are the system param-eters, and xi, yi, and zi are the system variables [11,12]. Further-more, Table 1 shows how these ODEs are solved using Euler’smethod where the subscript i is the iteration index and h is the step

Fig. 1. The HW realization of: (a) Euler’

size. The index i equals to zero corresponds to the initial point(x0, y0, z0).

One chaotic attractor can be generated from the Lorenz systemby setting the parameters (a, b, c) to (10, 8/3, 28) [12]. On the otherhand, three different chaotic attractors can be generated from theLü system by setting the parameters (a, b, c) to (36, 3, 13), (36, 3,20), or (36, 3, 28) [12].

In the proposed PRNG these original parameters’ values aremodified as shown in Table 2 where the step size is fixed at 2�8.The reason for this modification is to build a generic system thatcan switch between the four 3D chaotic attractors using only hard-wired shifters and multiplexers. The hardwired shifters are used toperform the multiplications by the constants a, b, and c and thestep size h. On the other hand the multiplexers are used to selectthe desired configuration using the two bits Config signal.

2.1. The HW implementation

The size of the generator’s data bus is set to 32 bits. The 2’s com-plement fixed point scheme is used to represent the data. The inte-ger part is represented using 8-bits while the fraction part isrepresented using 24-bits. Euler’s method is implemented asshown in Fig. 1(a). The 32 bits register is used to output xi. This reg-ister is updated every clock cycle. In case the Init. signal is set high,the multiplexer will load the initial value x0 into the register.Otherwise, the solution xi+1 will be loaded into the register. Thevalue of xi+1 is computed by adding h: _x to xi. The block inFig. 1(a) is implemented for each system variable: xi, yi, and zi.

The computations of h: _x, h: _z, and h: _y are realized as shown inFig. 1 (b), (c), and (d) respectively. The multiplexers in Fig. 1 (b)and Fig. 1 (c) are used to adjust the system parameters a and brespectively as discussed previously in Tables 1 and 2. Themultiplexers in Fig. 1 (d) are used to change the structure ofthe _y equation as illustrated in table 1 in addition to adjustingthe value of the c parameter as shown in table 2. The operator(�n) is an n bit hardwired shifting operation that corresponds tothe multiplication by 2�n. The truncation rounding scheme isapplied after any multiplication in order to preserve the 32 bitsbus size.

Finally, the pseudo random numbers are taken from the 8 LeastSignificant Bits (LSBs) of each chaotic signal (x, y, and z). Therefore,the proposed PRNG can generate 24 random bits per one clockcycle.

s method, (b) h _x, (c) h _z, and (d) h _y.

Table 3The NIST statistical p values results for the four different chaotic configurations.

NIST test2,000,000 bits

Config.00

Config.01

Config.10

Config.11

Frequency 0.7838 0.4612 0.7418 0.4682Block frequency (m = 128) 0.1604 0.9966 0.9988 0.1900Cusum-forward 0.8983 0.5885 0.7626 0.5244Cusum-reverse 0.8994 0.5698 0.9481 0.5286Runs 0.0118 0.6394 0.4193 0.6119Long runs of one 0.5826 0.2116 0.7711 0.6300Rank 0.0558 0.4707 0.1595 0.3443Spectral DFT 0.3272 0.5462 0.4957 0.2814Non-overlapping templates 0.5567 0.8451 0.7315 0.6462Overlapping templates (m = 9) 0.6093 0.6635 0.9712 0.6427Universal 0.6992 0.2365 0.5354 0.8026Approximate entropy (m = 10) 0.6081 0.9419 0.2760 0.7709Random excursions 0.8317 0.8366 0.9435 0.5788Random excursions variant 0.9461 0.9757 0.9493 0.9691Linear complexity (M = 500) 0.7640 0.2534 0.6339 0.1167Serial (m = 16) 0.9931 0.9900 0.4632 0.4319

919293949

-18 18

z

x

-30

-10

10

30

-20 0 20

y

x (a)

51525354555

-27 23

z

y

2

12

22

32

-20 0 20

z

x

-20-10

01020

-20 22

y

x (b)

2

12

22

32

-20 22

z

y

05

10152025

-16 16

z

x

-18

-8

2

12

-16 16

y

x (c)

05

101520

-18 18

z

y

010203040

-25 -5 15

z

x

-30

-10

10

-26 22

y

x (d)

010203040

-30 20

z

y

Fig. 2. The chaotic attractors of the proposed reconfigurable generator: (a) Lorenz (a, b, c, h) = (8, 2, 32, 2�8), (b) Lü (a, b, c, h) = (32, 4, 16, 2�8), (c) Lü (a, b, c, h) = (32, 4, 12,2�8), and (d) Lü (a, b, c, h) = (32, 4, 20, 2�8).

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Table 4Summary for previously implemented chaotic PRNGs.

Criteria This paper [18] [17] [20] [21]

System (Lorenz + Lü) Lorenz Lorenz Rössler LorenzThe number of 3D chaotic attractors 4 1 1 1 1Bus size 32 bits 32 bits 32 bits 32 bits 32 bitsFPGA Virtex V (XC5VLX50T) Virtex II (XC2V1000) Virtex IV (XC4VSX35) Zynq-7000 Zynq-7020Occupied slices/total 100/7200 1926/5120 145/15,360 � 338Slice registers/total 96/28,800 791/10,240 96/30,720 96/106,400 96Slice LUTs/total 276/28,800 2718/10,240 287/30,720 433/53,200 868DSP blocks/total 8/48 � 8/192 12/220 8MULT18X18/total � 40/40 � � �Frequency 78.149 MHz 15.598 MHz 53.53 MHz 70.9 MHz 36.31 MHzNIST Pass � � � �

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3. The proposed reconfigurable PRNG

The proposed PRNG has been realized using VHDL, and synthe-sized on Xilinx using the FPGA (XC5VLX50T). The number of LUTs,registers, and DSP blocks that are utilized by the generator are 96,276, and 8 respectively. Furthermore, the maximum clock fre-quency that can be handled by the generator is 78.149 MHz.

The proposed generator has been simulated using Xilinx ISE.Accordingly, a VHDL test bench has been implemented in orderto configure the generator, set the initial point (x0, y0, z0) to a ran-dom number, and finally write the outputs (xi, yi, zi) in a text file.This text file has been used to interface the Xilinx simulator withthe Matlab and the NIST statistical suite [19]. The Matlab has beenused to plot the chaotic attractors while the NIST suite has beenused to assess the randomness of the generator. The proposed gen-erator has passed all the NIST tests as shown in Table 3, where thepassing criteria is 1% (p value > 0.01). All the NIST tests have beenperformed using a stream of two million random bits. Further-more, the proposed generator has successfully produced four dif-ferent 3D chaotic attractors as shown in Fig. 2. Moreover, theproposed reconfigurable generator has been compared with othernon reconfigurable chaotic generators, [17,18,20,21], as shown inTable 4.

The proposed generator has the advantage of producing fourdifferent 3D chaotic attractors with a small implementation areaand high speed compared to the other generators that produceonly one 3D chaotic attractor. The proposed generator has utilized8 DSP units in order to implement the nonlinear multiplicationsthat are shown previously in Table 1; (xi�zi) and (xi�yi). The numberof slice registers that are utilized by the proposed generator is

RAM

Init.

IS0

Clk

HDMI

PRNG

InOut

Address

R/W

ClkResetStartE/D

Pixe

l

Proc

esse

dPi

xel

Config

NCiphers

00011011

Key1Key2Key3Key4

Control unit

Fig. 3. The block diagram of the proposed cascaded cipher processor.

equal to the size of the data bus (32-bits) multiplied by the numberof variables.

4. Cascaded encryption processor

Fig. 3 presents the block diagram of the proposed system. Thesystem consists of three main blocks; RAM, PRNG, and Control unit.All the Input/output and control signals are summarized in Table 5.The function of the proposed system is to read a 256 � 256 imagefrom a memory unit, encrypt or decrypt the image, write the pro-cessed image back in the memory, and finally display the image ona screen. The system’s encryption key is divided into four parts:‘key1’ to ‘key4’. Each part is used to initialize a specific configura-tion of the PRNG. The ‘NCiphers’ is a 2-bit input that is used toselect the required number of ciphering operations. In case ‘NCi-phers’ is set to ‘‘00”, the system will perform only one encryptionoperation using ‘key1’. In case the ‘Nciphers’ is set to ‘‘01”, the sys-tem will perform two consecutive encryption operations using‘key1’ and ‘key2’. The system can perform up to four consecutiveencryptions and use all the four keys. Hence, the size of the encryp-tion key is set according to the ‘Ncipers’ input. The FPGA’s internalRAM is used to store the input image. Each memory location isused to store one colored pixel (24 bits). The output of the pro-posed PRNG is combined with the image’s pixels in an XOR fashion.The Control units is used to provide the (HDMI) control signals, ini-tialize and configure the PRNG, and generate the RAM’s ‘Address’and Read/Write ‘R/W’ signal.

The block diagram of the control unit is presented in Fig. 4. TheControl unit consists of a counter, an HDMI controller, Multiplex-ers, a Flip Flop, and a Moore Finite State Machine (FSM). The coun-ter is used to generate the RAM’s ‘Processing address’ that is usedduring the encryption or decryption process. This counter is initial-ized when the ‘reset’ signal or the ‘Mode’ signal is set high, and is

Table 5Summary for the system’s IO and control signals.

Signal: Functionality:

NCiphers The number of required ciphers. (From 1 up to 4)Clk Clock signalReset Reset signalStart Start signalE/D Encryption: E/D = ‘1’. Decryption: E/D = ‘0’IS0 The image initial state: Encrypted: IS0 = ‘1’. Decrypted: IS0 = ‘0’Key The encryption keyHDMI The standard HDMI connector’s signalsR/W Write: R/W = ‘1’. Read: R/W = ‘0’Address The RAM’s addressInit. Initializes the PRNGConfig. Configures the PRNGMode Display: Mode = ‘1’. Process: Mode = ‘0’IS Image state: Encrypted: IS = ‘1’. Decrypted: IS = ‘0’Adjust Inverts the image state

Fig. 4. The block diagram of the control unit.

Table 6Implementation results of the proposed cascaded cipher processor.

System PRNG, Control unit, and XOR gates Full system

Occupied slices (7200) 119 286Slice registers (28,800) 118 299Slice LUTs (28,800) 494 1033DSP blocks (48) 8 8Clk frequency 78 MHz 78 MHz

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incremented after each write cycle. The counter’s two MSBs areused to configure the PRNG and select between ‘key1’ to ‘key4’.On the other hand the counter’s 16 LSBs are used to provide the‘processing address’ of the RAM. The HDMI controller is used to gen-erate the ‘HDMI’ control signals and the RAM’s ‘Display address’ thatare used during the image display process. A Multiplexer is used toselect between the ‘Display address’ and the ‘Processing address’ andthen send the appropriate ‘Address’ to the RAM. This Multiplexer iscontrolled by the ‘Mode’ signal. The state of the image ‘IS’ is storedin a Flip Flop and is initialized with ‘IS0’. The core part of the controlunit is the Moore Finite State Machine (FSM). The ‘‘IDLE” is thestarting state of the FSM. The FSM remains in the ‘‘IDLE” state untilthe ‘start’ signal is enabled. In case the ‘E/D’ input is the same as theimage state ‘IS’, the FSM will move directly to the ‘‘Display” state inorder to display the image. Otherwise, the FSM will process thestored image by looping through the ‘‘Read” and ‘‘Write” states.

Fig. 5. FPGA prototyping. (a) The FPGA kit, (b) the decr

After processing the image, the FSM will jump to the ‘‘Adjust IS”state in order to flip the image state. Finally, the FSM stays in the‘‘Display state” until the ‘E/D’ input is changed.

The proposed cascaded encryption processor has been realizedusing VHDL, and synthesized on Xilinx using the FPGA(XC5VLX50T). The IP core generator of Xilinx has been used to cre-ate the HDL model of the internal RAM and initialize it with Lena256 � 256 colored image. The synthesis results are summarizedin Table 6. Fig. 5 shows the experimental setup of the proposedcascaded ciphering system. The switches of the FPGA kit have beenused to provide the inputs of the system. Furthermore, a VHDL testbench has been implemented to simulate the encryption processorand write the output image after each encryption and decryptionoperation in a text file. This text file can be processed on Matlabin order to plot the output images. Fig. 6, shows the simulationresults for the case of four consecutive encryption operations.

5. Conclusion

A reconfigurable chaotic PRNG has been presented in this paper.The proposed PRNG has adopted the Lorenz and Lü equations inorder to support four different 3D chaotic attractors. The similari-ties between the Lorenz and Lü have led to an efficient HW imple-mentation area. Only Multiplexers and hardwired shifters havebeen utilized in order to switch between four different chaoticattractors during real time operation. The proposed system has

yption operation, and (c) the encryption operation.

Fig. 6. Simulation results for the case of four consecutive encryption operations: (a) the original image, (b),(c),(d),(e) the output of the four encryption operations, and (f),(g),(h),(i) the output of the four decryption operations.

A.A. Rezk et al. / Int. J. Electron. Commun. (AEÜ) 98 (2019) 174–180 179

been implemented on the FPGA (XC5VLX50T). The proposed PRNGhas utilized 1.4% and 16.7% from the available slices and DSP blocksrespectively. The DSP blocks have been used to implement the sys-tem’s nonlinear multiplications. Furthermore, the timing analysishas showed that the PRNG can operate at 78 MHz. Moreover, theproposed PRNG has successfully passed all the NIST randomnesstests. Finally, the proposed PRNG has been embedded in an FPGAcascaded encryption processor that can encrypt the input imageup to four times using a variable size encryption key.

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