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DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

ECE291- Digital Logic and Design Laboratory (Laboratory with Projects)

Academic Year (2017-2018) ODD Semester

for

DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING

Student’s Name :…………………………………………………

Register Number :…………………………………………………

Year / Semester :…………………………………………………

Section :…………………………………………………

LABORATORY MANUAL

ECE291 – Digital Logic and Design Laboratory

ECE / KALASALINGAM UNIVERSITY Page 1 of 101



TABLE OF CONTENTS

S. No Contents Page No.

1. Instructions 4

2. Do‟s and Don‟ts 5

3. Course Plan 6

4. Realization of logic gates 11

5. Implementation of combinational logic circuits 21

6. Multiplexer and De-multiplexer 30

7. Decoders and Encoders 37

8. Iterative circuits 44

9. Parity Checkers and Generators 49

10. Shift Registers 55

11. Ripple Counters and Synchronous counters 64

12. Seven Segment Decoder 71

13. Memory Devices 77

14. Analog to digital converters 83

15. Synchronous Finite State Machine 88

APPENDICES

A. Rubric for Pre Lab Work 95

B. Rubric for Model Lab 96

C. Rubric For Mini Project 97

D. Pin Diagrams for Gates and Flip-Flops 98



MARK SUMMARY

Exp.

No. Experiment Name Date Marks

Course

Teacher’s

Signature

1. Realization of logic gates

2. Implementation of combinational

logic circuits

3. Multiplexer and De-multiplexer

4. Decoders and Encoders

5. Iterative circuits

6. Parity Checkers and Generators

7. Shift Registers

8. Ripple Counters and Synchronous

counters

9. Seven Segment Decoder

10. Memory Devices

11. Analog to digital converters

12. Synchronous Finite State

Machine

LABORATORY REPORT (15%)

MODEL EXAMINATION (20%)

MINI PROJECT DEMONSTRATION (15%)

TOTAL INTERNAL MARKS (50%)



Instructions

Attendance

Students are expected to attend laboratory classes regularly, and to be on time

for every laboratory class period. Students can be dropped from a class due to excessive

absences. Excessive tardiness may be considered absences. Students are responsible for

assignments, and experiments covered during their absences.

Academic Honesty

Scholastic dishonesty is treated with the utmost seriousness by the instructor

and the department. Academic dishonesty includes, but it is not limited to the wilful

attempt to misrepresent one‟s work, cheat, plagiarize, or impede other students‟

scholastic progress.

Dress Code

Dress code must be appropriate for the laboratory. Students must dress in a way

that clothing and accessories do not compromise their safety, and the safety of others.

Proper foot wear is required in all laboratories. Absolutely no sandals or other footwear

that exposes the feet will be allowed.

Laboratory Conduct

Proper behaviour is expected in all laboratories. Foul language and horseplay

are not allowed.

Books, Tools and Supplies

Students are required to bring to class the required textbooks, tools (including

calculators), notebooks, supplies, and writing instruments as required by the instructor.



DO’S DON’T’S

Be regular to the lab. Do not exceed the voltage Rating

Follow proper Dress Code. Do not interchange the IC‟s while

doing the experiment

Maintain Silence. Avoid l o o s e co n n ec t i o n s and

short circuits

Know the theory behind the experiment before

coming to the lab

Do not throw the connecting wires

to floor

Identify the different leads or terminals or pins of

the IC before making connection. Do not come late to the lab

Know the biasing voltage required for different

families of IC‟s and connect power supply

voltage and ground terminals to the respective

pins of the IC‟s.

Do not operate the IC trainer kits

unnecessarily

Know the Current and Voltage rating of the IC‟s before using them in the experiment.

Do not panic if you don‟t get the

output.

Avoid unnecessary talking while doing the

experiment.

Handle the IC Trainer Kit properly

Mount the IC Properly on the IC Zif Socket.

Handle the other equipment‟s properly.

While doing t h e I n t e r f a c i n g , c o n n e c t

proper voltages to the interfacing kit.

Keep the table clean

Take a s i g n a t u r e o f t h e i n c h a r g e before taking the kit/components

After the completion of the experiments switch off t h e power supply and return the apparatus

Arrange the chairs/stools and equipment properly before leaving the lab.



KALASALINGAMUNIVERSITY

(Kalasalingam Academy of Research and Education)

ANANDNAGAR, KRISHNANKOIL – 626126

DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING

ODD SEMESTER 2017-2018

COURSE PLAN

Subject with Code DIGITAL LOGIC AND DESIGN LAB / ECE291

Course B.Tech

Branch / Semester / Section CSE / III / A, B, C, D

Course Credit 2

Course Coordinator Mr. M. SAKTHIMOHAN

Module Coordinator Mr. C. BALA SUBRAMANIAN

Programme Coordinator Dr. R. RAMALAKSHMI

Pre – Requisite

Basic Electrical and Electronics Engineering (EEE101),

Digital Electronics (ECE202)

Course Description

This course will impart the concepts of digital electronics practically and train students

with all the equipment „s which will help in improving the basic knowledge. It will also

help to analyze and design combinational logic and sequential logic circuits

Career Opportunities

1. JTO-BSNL

2. Network Engineer-CISCO, MTNEL

3. System Engineer

COURSE OUTCOMES(COS):

CO1: An ability to operate laboratory equipment.

CO2: An ability to construct, analyzes, and troubleshoots simple combinational and

sequential circuits.

CO3: An ability to design and troubleshoot a simple state machine.

CO4: An ability to measure and record the experimental data, analyze the results, and

prepare a formal laboratory report.



PROGRAM EDUCATIONAL OBJECTIVES (PEOS)

PEO1: The Graduates will be technically competent to excel in IT industry and to

pursue higher studies.

PEO2: The Graduates will possess the skills to design and develop economically and

technically feasible computing systems using modern tools and techniques.

PEO3: The Graduates will have effective communication skills, team spirit, ethical

principles and the desire for lifelong learning to succeed in their professional career.

PROGRAMME OUTCOMES (POS)

PO1: Ability to apply knowledge of mathematics, science and computer engineering to

solve computational problems.

PO2: Ability to identify, formulate, analyze and derive to solve complex computing

problems.

PO3: Capability to design and develop computing systems to meet the requirement of

industry and society with due consideration for public health, safety and environment.

PO4: Ability to apply knowledge of design of experiment and data analysis to derive

solutions in complex computing problems.

PO5: Ability to develop and apply modeling, simulation and prediction tools and

techniques to engineering problems.

PO6: Ability to assess and understand the professional, legal, security and societal

responsibilities relevant to computer engineering practice.

PO7: Ability to understand the impact of computing solutions in economic,

environmental and societal context for sustainable development.

PO8: Applying ethical principles and commitment to ethics of IT and software

profession.

PO9: Ability to work effectively as an individual as well as in teams.

PO10: Ability to effectively communicating with technical community and with

society.

PO11: Demonstrating and applying the knowledge of computer engineering and

management principles in software project development and in multidisciplinary areas.

PO12: Understanding the need for technological changes and engage in life-long

learning



PROGRAMME SPECIFIC OUTCOMES:

PSO1: Problem-Solving Skills: The ability to apply mathematics, science and computer

engineering knowledge to analyze, design and develop cost effective computing

solutions for complex problems with environmental considerations.

PSO2: Professional Skills: The ability to apply modern tools and strategies in software

project development using modern programming environments to deliver a

quality product for business accomplishment.

PSO3: Communication and Team Skill: The ability to exhibit proficiency in oral and

written communication as individual or as part of a team to work effectively with

professional behaviors and ethics.

PSO4: Successful Career and Entrepreneurship: The ability to create a inventive

career path by applying innovative project management techniques to become a

successful software professional, an entrepreneur or zest for higher studies.

PO and PEO Mapping:

PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12

PEO1 S S S S S L L S S

PEO2 L S S S S S S

PEO3 S S S S S S L S

CO, PO and PSO Mapping:

PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2 PSO3 PSO4

CO1 S S

CO2 S S M M S M M

CO3 S S M M M S M M

CO4 M S M

CO5 M M S M M

S-Strong Correlation M-Medium Correlation L–Low Correlation

Web Resources:

Website

1. http://www.electronics-tutorials.ws/combination/comb_1.html

2. http://www.ni.com/white-paper/5676/en/

3. http://www.ee.surrey.ac.uk/Projects/CAL/digital-

logic/multiplexer/index.html

4. http://www.tutorialspoint.com/computer_logical_organization/com

binational_circuits.htm

5. http://www.electronics-tutorials.ws/sequential/seq_3.html

6. http://www.allaboutcircuits.com/vol_4/chpt_11/5.html

7. http://www.slideshare.net/RajatMore/types-of-memories-and-

storage-device-and-computer

http://www.electronics-tutorials.ws/combination/comb_1.html

http://www.ni.com/white-paper/5676/en/

http://www.ee.surrey.ac.uk/Projects/CAL/digital-logic/multiplexer/index.html

http://www.ee.surrey.ac.uk/Projects/CAL/digital-logic/multiplexer/index.html

http://www.tutorialspoint.com/computer_logical_organization/combinational_circuits.htm

http://www.tutorialspoint.com/computer_logical_organization/combinational_circuits.htm

http://www.electronics-tutorials.ws/sequential/seq_3.html

http://www.allaboutcircuits.com/vol_4/chpt_11/5.html

http://www.slideshare.net/RajatMore/types-of-memories-and-storage-device-and-computer

http://www.slideshare.net/RajatMore/types-of-memories-and-storage-device-and-computer



Lesson Plan:

S.No Topic Name Refer

ences

No. of

periods

Cum. no.

of periods

Cycle I

1. Introduction 3 3

2. Realization of logic gates 3 6

3. Implementation of combinational logic circuits 3 9

4. Multiplexer and De-multiplexer 3 12

5. Decoders and Encoders 3 15

6. Iterative circuits 3 18

7. Parity Checkers and Generators 3 21

Cycle II

8. Shift Registers 3 24

9. Ripple Counters and Synchronous counters 3 27

10. Seven Segment Decoder 3 30

11. Memory Devices 3 33

12. Analog to digital converters 3 36

13. Synchronous Finite State Machine 3 39

14. Model Lab 3 42

15. Assessment of CO1, CO2, CO3, CO4 -- 1 43

16. Entry -Exit Survey, Review / Revision -- 2 44

Experiments for Fast Learners:

1. Realization of Duality theorem using Logic Gates.

2. Realization of De-Morgan's theorem using Logic Gates.

3. Realization of Distributive, Associative and Cumulative Laws in Boolean

algebra using Logic Gates.

4. Realization of 8:1 MUX and 1:8 DEMUX.

5. Realization of Binary to Gray code converter.

6. Realization of Gray to Binary code converter.

7. Realization of BCD to Excess-3 code converter.

8. Realization of Excess-3 to BCD code converter.

9. Realization of BCD Adder.

10. Realization of 4 bit ODD and EVEN Parity checker.

Mapping of CO to Model Lab:

A/T/COs Model Lab

CO1 Y

CO2 Y

CO3 Y

CO4 Y



Assessment Plan for the Course:

S.No Course Outcomes Measurement Tools Time of Measurement 1. CO1

Think Pair Share, Peer Review 20 minutes 2. CO2 3. CO3 Think Pair Share, Peer Review 30 minutes 4. CO4 Think Pair Share 30 minutes

Sample Measurement Tools:

Think Pair Share and Peer Review

Related projects (if any):

Digital counter

Content Delivery Methodologies:

1. Flipped Lab Course

2. Laboratory Sessions

Assessment Methodologies:

Direct Indirect

Examinations

Think Pair Share

Model Lab

Course Entry Survey

Course Exit Survey

Test Portions:

S.No Test Number Topic Number

1. Model lab 1-13

2. End Semester Examination 1-13



Date:

EX.NO:2 REALIZATIONS OF LOGIC GATES

Aim:

To Realize the Logic gates (AND, OR, NOT, NAND, NOR and EX-OR gate

using 74XX IC‟s.

Apparatus Required:

Sl.No Component Type Quantity

1 Trainer Kit - 1

2 AND Gate IC 7408 1

3 OR Gate IC 7432 1

4 NOT Gate IC 7404 1

5 NAND Gate IC 7400 1

6 NOR Gate IC 7402 1

7 EX-OR IC7486 1

8 Connecting wires - Required

Theory:

Logic Gates:

The logic gate is the basic building block in digital systems. Logic gates operate

with binary numbers. Gates are therefore referred to as binary logic gates. All voltages

used with logic gates will be either HIGH or LOW. A HIGH voltage will mean a binary

1. A LOW voltage will mean a binary 0. Remember that logic gates are electronic

circuits. These circuits will respond only to HIGH voltages (called 1s) or LOW

(ground) voltages (called Os).

AND Gate:

A basic AND gate consists of two inputs and an output. If the inputs are A,

B…X, the output (often called Y) is “on” only if all the inputs A, B…X are also “on.”

Y= A AND B AND C… AND X

Where A, B, … N are the input variables and Y is the output variable. The

variables are binary, i.e. each variable can assume only one of the possible values, 0 or

1. For example, for an AND operation the gate opens (Y = 1) only, when all the inputs

are present.

OR Gate:

A basic OR gate consists of two inputs and an output. If the inputs are A, B…X,

the output (often called Y) is “on”, if one the inputs A, B…X is “on.”

Y= A OR B OR C… OR X = A+B+C… +N



Where A, B, … N are the input variables and Y is the output variable. The

variables are binary, i.e. each variable can assume only one of the possible values, 0 or

1. For example, for an OR operation the gate opens (Y = 1), when one of the input is

present.

NOT Gate:

A NOT gate is also called an inverter. A NOT gate, or inverter, is an unusual

gate. The NOT gate has only one input and one output.

Y = NOT A. = A

The process of inverting is simple. The input is always changed to its opposite. If

the input is 0, the NOT gate will give its complement, or opposite, which is 1. If the

input to the NOT gate is a 1, the circuit will complement it to give a 0.

NAND Gate:

NAND Gate is a circuit which performs, the logic or Boolean operation derived

from the basic logic operations NOT and AND, namely the NAND operation.

________

Y = A B … N

Digital signals are applied at the input terminals A, B, C…N. The output is

obtained at the output terminal marked Y. The NAND operation is defined as: the

output of an NAND gate is 0 if and only if all the inputs are 1. It is the inverse of the

AND operation. The NAND gate is known to be one of the Universal gates.

NOR Gate:

NOR Gate is a circuit which performs, the logic or Boolean operation derived

from the basic logic operations NOT and OR, namely the NOR operation.

___________

Y = A +B+ … +N

Digital signals are applied at the input terminals A, B, C…N. The output is

obtained at the output terminal marked Y. The NOR operation is defined as: the output

of an NOR gate is 1 if and only if all the inputs are 0. It is the inverse of the OR

operation. The NOR gate is known to be one of the Universal gates.

EX-OR Gate:

The exclusive-OR gate is referred to as the “any but not all” gate or "one or

the other but not both". The exclusive-OR term is often shortened to read as XOR.

The XOR gate is enabled only when an odd number of 1s appear at the inputs. The

XOR gate could be referred to as an “odd-bits check circuit”.

Y = A EX-NOR B …

= A B… X



Design:

AND Gate:

Truth Table:

Logic Diagram: Pin Diagram:

OR Gate:

Truth Table:


INPUT OUTPUT

A B Y

0

0

1

1

0

1

0

1

0

0

0

1

INPUT OUTPUT

A B Y

0

0

1

1

0

1

0

1

0

1

1

1



NOT Gate:

Truth Table:


NAND Gate:

Truth Table:


INPUT OUTPUT

X Y

0

1

1

0

INPUT OUTPUT

A B Y

0

0

1

1

0

1

0

1

1

1

1

0



NOR Gate:

Truth Table:

Logic diagram: Pin Diagram:

EX-OR Gate:

Truth Table:

INPUT OUTPUT

A B Y

0

0

1

1

0

1

0

1

1

0

0

0

INPUT OUTPUT

A B Y

0

0

1

1

0

1

0

1

1

0

0

1






On Laboratory Work for Logic Gates:

OR Gae:

Inputs Output Output

Verified

A B Y (Y/N)

0 0

0 1

1 0

1 1

AND Gae:


Verified

A B Y (Y/N)

0 0

0 1

1 0

1 1

NOT Gae:


Verified

A B Y (Y/N)

0 0

0 1

1 0

1 1

NAND Gae:


Verified

A B Y (Y/N)

0 0

0 1

1 0

1 1



NOR Gae:


Verified

A B Y (Y/N)

0 0

0 1

1 0

1 1

EXOR Gae:


Verified

A B Y (Y/N)

0 0

0 1

1 0

1 1



Procedure: 1. Connections are made as per the circuit given.

2. The Low level input is grounded.

3. The HIGH level input is connected to the +5V supply.

4. Observe the output various combination of inputs.

5. Thus the truth table is verified.

Basic Workout Questions Related to Experiment:

1. Draw the XOR logic using only NAND gates.

2. Implement the following Boolean function with NOR – NOR logic.

F = Π(0,2, 4,5,6)

3. Define minterm & Maxterm. Give examples.



4. Realize F = A’B+AB’ using minimum universal gates.

5. What are universal gates implement AND gate using any one universal gate?

Rubrics for Laboratory Work:

Criteria Obtained Marks Allotted marks

Knowledge 20

Design 30

Analysis 20

Ethics 10

Communication 10

Team Work 10

Total 100

Signature

Result:



Date :

EX.NO:3 IMPLEMENTATION OF COMBINATIONAL CIRCUITS

Aim:

To realize the adder and Subtractor using logic gates and to verify the truth

table.

Apparatus Required:

Theory:

Half Adder:

A combinational circuit that performs the addition of two bits is called a half-

adder. This circuit needs two binary inputs and produces two binary outputs. One of the

input variables designates the augend and other designates the addend. The output

variables produce the sum and the carry.


1 Trainer Kit - 1


3 OR Gate IC 7432 1

4 EX-OR IC7486 2

5 NOT IC 7404 1




Pre Laboratory work for Half Adder

(Truth table, K-map Simplification, Logical Expression, Logical Diagram)



Full Adder:

A combinational circuit that performs the addition of three bits is called a half-

adder. This circuit needs three binary inputs and produces two binary outputs. One of

the input variables designates the augend and other designates the addend. Mostly, the

third input represents the carry from the previous lower significant position. The output

variables produce the sum and the carry.

Pre Laboratory work for Full Adder




Half subtractor:

A half subtractor is a combinational circuit that subtracts two binary inputs and

produces their difference. It also has an output to specify if a 1 has been borrowed. The

circuit has two inputs, one representing the Minuend bit and the other Subtrahend bit.

The circuits produces two outputs, then difference and borrow. The Boolean functions

for the tow outputs can be written as

Pre Laboratory work for Half Subtractor




FULL SUBTRACTOR

A full subtractor is a combinational circuit that subtraction between two binary

inputs, taking into account that a 1 may have been borrowed by a lower significant

sage. The circuit has three inputs, representing the minuend bit, the Subtrahend bit and

the previous borrow bit respectively. The two outputs, d and b represent the difference

& output borrows. The Boolean functions for the tow outputs can be written as

Pre Laboratory work for Full Subtractor




On Laboratory Work: Half Adder: Input Output Output Verified

A B Sum Carry (Y/N)

0 0

0 1

1 0

1 1

Full Adder: Input Output Output Verified

A B C Sum Carry (Y/N)

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

Half Subtractor:

Input Output Output Verified

A B Sum Carry (Y/N)

0 0

0 1

1 0

1 1



Full Subtractor:

Input Output Output Verified

A B C Sum Carry (Y/N)

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1



Procedure:

1. The adder and subtractor circuits are designed using the Boolean function which

is found out from the truth tables.

2. Connections are made as per the circuit given.

3. The Low level input is Grounded and the HIGH level input is connected to the

+5V supply.

4. Observe the output various combination of inputs.



1. What is combinational circuit? Give examples.

2. Design Half – adder using only NAND gates.

3. Draw the block diagram of n-bit parallel adder.



4. Implement Full adder with 2 Half adders.

5. What you mean by carry propagation delay?



Knowledge 20

Design 30

Analysis 20

Ethics 10

Communication 10

Team Work 10

Total 100

Signature

Result:



Date:

EX.NO:4 MULTIPLEXER AND DEMULTIPLEXER REALIZATIONS

Aim:

To realize the multiplexer and demultiplexer circuit using logic gates and to

verify the truth table.

Apparatus Required:

4:1 Multiplexer:

Theory: A multiplexer or mux (occasionally the terms muldex or muldem are also

found[1]

for a combination multiplexer-demultiplexer) is a device that performs

multiplexing; it selects one of many analog or digital input signals and forwards the

selected input into a single line. A multiplexer of 2n inputs has n select lines, which are

used to select which input line to send to the output.


1 Trainer Kit - 1

2 AND Gate (3 input) IC 7411 3

3 OR Gate IC 7432 1

4 NOT Gate IC7404 1


http://en.wikipedia.org/wiki/Multiplexer#cite_note-0

http://en.wikipedia.org/wiki/Multiplexing



Pre Laboratory work for 4x1 Multiplexer




1:4 Demultiplexer:

Theory:

The de-multiplexer performs the reverse operation of a multiplexer. It is a

combinational circuit which accepts a single input and distributes it over several

outputs. The number of output lines is „n‟ and the number of select lines is 2n lines. De-

multiplexer ICs may have an enable input to control the operation of the unit. When the

enable input is in a given binary state (the disable state), the outputs are disabled, and

when it is in the other state (the enable state), the circuit functions as normal de-

multiplexer. The size of the de-multiplexer is specified by the single input line and the

number 2n of its output lines.



Pre Laboratory work for 4x1 Demultiplexer




On Laboratory work for Multiplexer and Demultiplexer:

Multiplexer:

Selection Lines Inputs Output Output

Verified

SO S1 IO I1 I2 I3 Y (Y/N)

0 0 1 0 0 0

0 1 0 0 0 0

1 0 0 0 0 0

1 1 0 0 0 1

Demultiplexer:

Selection Lines Input Outputs Output

Verified

S0 S1 I YO Y1 Y2 Y3 (Y/N)

0 0 1

0 1 0

1 0 1

1 1 0



Procedure:

1. The Multiplexer and demultiplexer circuit is designed and the Boolean

function is found out.

2. The Low level input is Grounded and the HIGH level input is connected to

the +5V supply.

3. The inputs and selection lines are given from the input switches.

4. Connections are made as per the circuit given

5. Observe the output for various combinations of inputs.



1. What is data selector and data distributor? And Justify.

2. Differentiate a decoder from a Demultiplexer.

3. Implement full adder using Multiplexer.



4. Implement full subtractor using Demultiplexer.

5. What are the applications of multiplexer and Demultiplexer?



Knowledge 20

Design 30

Analysis 20

Ethics 10

Communication 10

Team work 10

Total 100

Signature

RESULT:



Date:

EX.NO:5 REALIZATIONS OF ENCODER AND DECODER

Aim:

To realize the Encoder and Decoder circuit using logic gates and to verify the

truth table.

Apparatus Required:

ENCODER:(8:3)

Theory:

An encoder has 2n (or fewer) input lines and „n‟ output lines. The output lines

generate the binary code corresponding to the input value. In encoders, it is assumed

that only one input has a value of 1 at any given time. The encoders are specified as m-

to-n encoders where m ≤ 2n.


1 Trainer Kit - 1

2 OR Gate IC 7432 3

3 AND gate (3 input) IC7411 2

4 NOT gate IC 7404 1




Pre Laboratory work for 8:3 Encoder




DECODER :( 3:8)

Theory:

A decoder is a combinational circuit that converts binary information from „n‟

input lines to a maximum of 2n unique output lines. It performs the reverse operation of

the encoder. If the n-bit decoded information has unused or don‟t-care combinations,

the decoder output will have fewer than 2n outputs. The decoders are represented as n-

to-m line decoders, where m ≤ 2n. Their purpose is to generate the 2

n (or fewer)

minterms of n input variables. The name decoder is also used in conjunction with some

code converters such as BCD-to-seven-segment decoders. Most, if not all, IC decoders

include one or more enable inputs to control the circuit operation. A decoder with an

enable input can function as a de-multiplexer.



Pre Laboratory work for 3:8 Decoder




On Laboratory work for Encoder and Decoder:

8:3 Encoder:

Input Output Output

Verified

I0 I1 I2 I3 I4 I5 I6 I7 E0 E1 E2 (Y/N)

1 0 0 0 0 0 0 0

0 1 0 0 0 0 0 0

0 0 1 0 0 0 0 0

0 0 0 1 0 0 0 0

0 0 0 0 1 0 0 0

0 0 0 0 0 1 0 0

0 0 0 0 0 0 1 0

0 0 0 0 0 0 0 1

3:8 Decoder

Input Output Output

Verified

I0 I1 I2 D0 D1 D2 D3 D4 D5 D6 D7 (Y/N)

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1



Procedure:

1. The Encoder and Decoder circuit is designed and the Boolean function is

found out.


+5V supply.





1. Differentiate Encoder and Multiplexer.

2. Implement Full subtractor using 3:8 decoder.

3. Define Priority encoder.



4. What are all the applications of Encoder and decoder?

5. What is binary decoder?



Knowledge 20

Design 30

Analysis 20

Ethics 10

Communication 10

Team Work 10

Total 100

Signature

Result:



Date:

EX.NO:6 ITERATIVE CIRCUITS Aim:

To design a magnitude comparator using basic logic gates and verify the truth

table.

Apparatus Required:

Theory:

A magnitude comparator is a combinational circuit that compares the magnitude

of two numbers (A,B) and generates one of the following outputs.

1. A=B

2. A>B

3. A<B

Let A and B two input numbers A=A1A0 and B=B1B0

1. If A1 is greater than B1 then A>B

2. If A1 is less than B1 then A<b

3. If A1 is equal to B1 then we have to check the next bit.

4. If A0 is greater than B0 then A>B

5. If A0 is less than B0 then A<b

If A1 is equal to B1 then A=B.


1 Trainer Kit - 1


3 3-i/p AND Gate IC 7411 2

4 OR Gate IC 7432 1

5 EX-OR IC7486 1





Pre Laboratory work for Comparator




On laboratory Work for Comparator:

Input Output Output

Verified

A0 A1 B0 B1 A>B A=B A<B (Y/N)

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1



Procedure:

1. The circuit is implemented using logic gates.


+5V supply.

3. The logic inputs are given as per the truth table.

4. The outputs are observed.

5. Compare the theoretical and practical and verify the output.


1. What is a digital comparator?

2. Differentiate comparator and converter?

3. Design a 1-bit comparator using gates.



4. List out some applications of comparator.

5. What are all the outputs of 4-bit magnitude comparator?



Knowledge 20

Design 30

Analysis 20

Ethics 10

Communication 10

Team Work 10

Total 100

Signature

Result:



Date:

EX.NO.7 PARITY CHECKERS AND GENERATORS

Aim:

To implement the odd and even parity checkers using the logic gates and also to

generate the odd parity and even parity numbers using the generators.

Apparatus required:

Theory:

Parity checking is used for error detection in data transmission.

Odd parity checkers:

It counts the number of 1‟s in the given input and produces a 1 in the output

when the number of 1‟s is odd.

Even parity checker:

It counts the number of 1‟s in the given input and produces a 1 in the output

when the number of 1‟s is even.

Odd parity generators:

It generates an odd parity number. The odd parity checker circuit is used with

the inverted output and also the input bits. So when the input is a 4-bit number then the

output of the generator circuit will have 5 bits which is an odd parity number.

Even parity generator: It generates an even parity number. The even parity checker circuit is used with

the inverted output and also the input bits. So when the input is a 4-bit number then the

output of the generator circuit will have 5 bits which is an even parity number.


1 Trainer Kit - 1

5 EX-OR IC7486 1





Pre Laboratory work for Parity Generator




Pre Laboratory work for Parity checkers




On Laboratory work for Parity generators and checkers:

Odd parity generator:

3-bit Message

Odd

Parity

Generator

Even

Parity

Generator

Output

Verified

A B C Y Y (Y/N)

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

Odd Parity Checker:

3-bit Message Parity

bit

Odd

Parity

Checker

Even

Parity

Checker

Output

Verified

A B C P Y Y (Y/N)

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1



Procedure:

1. The circuit is implemented using logic gates.

2. The inputs are given as per the truth table.

3. The corresponding outputs are noted.

4. The theoretical and practical values were verified.


1. Why parity checker is needed?

2. List out some applications of comparator.

3. What is a parity bit?



4. Explain even parity checker.

5. Draw the output logic diagram of 4-bit even parity checker.



Knowledge 20

Design 30

Analysis 20

Ethics 10

Communication 10

Team Work 10

Total 100

Signature

Result:



Date:

EX.NO:8 REALIZATIONS OF SHIFT REGISTERS

Aim:

To Realize the Shift Registers using IC 74XX IC‟s and to verify the truth table.

Apparatus required:

Theory:

Introduction

Shift registers are a type of sequential logic circuit, mainly for storage of

digital data. They are a group of flip-flops connected in a chain so that the output from

one flip-flop becomes the input of the next flip-flop. Most of the registers possess no

characteristic internal sequence of states. All the flip-flops are driven by a common

clock, and all are set or reset simultaneously.

In this chapter, the basic types of shift registers are studied, such as Serial In -

Serial Out, Serial In - Parallel Out, Parallel In - Serial Out, Parallel In - Parallel Out,

and bidirectional shift registers. A special form of counter - the shift register counter, is

also introduced.

Serial In - Serial Out Shift Registers:

A basic four-bit shift register can be constructed using four D flip-flops, as

shown below. The operation of the circuit is as follows. The register is first cleared,

forcing all four outputs to zero. The input data is then applied sequentially to the D

input of the first flip-flop on the left (FF0). During each clock pulse, one bit is

transmitted from left to right. Assume a data word to be 1001. The least significant bit

of the data has to be shifted through the register from FF0 to FF3.

Serial In - Parallel Out Shift Registers:

For this kind of register, data bits are entered serially in the same manner as

discussed in the last section. The difference is the way in which the data bits are taken

out of the register. Once the data are stored, each bit appears on its respective output

line, and all bits are available simultaneously.

Parallel In - Serial Out Shift Registers:

A four-bit parallel in - serial out shift register is shown below. The circuit uses

D flip-flops and NAND gates for entering data (ie writing) to the register D0, D1, D2

and D3 are the parallel inputs, where D0 is the most significant bit and D3 is the least

significant bit. To write data in, the mode control line is taken to LOW and the data is


1 Trainer Kit - 1

2 D Flip Flop IC 7474 2




clocked in. The data can be shifted when the mode control line is HIGH as SHIFT is

active high. The register performs right shift operation on the application of a clock

pulse, as shown in below.

Parallel In - Parallel Out Shift Registers:

For parallel in - parallel out shift registers, all data bits appear on the parallel

outputs immediately following the simultaneous entry of the data bits. The following

circuit is a four-bit parallel in - parallel out shift register constructed by D flip-flops.

The D's are the parallel inputs and the Q's are the parallel outputs. Once the

register is clocked, all the data at the D inputs appear at the corresponding Q outputs

simultaneously.



Pre Laboratory work for Serial in Serial out Shift register




Pre Laboratory work for Serial in Parallel out Shift register




Pre Laboratory work for Parallel in Serial out Shift register




Pre Laboratory work for Parallel in Parallel out Shift register




ON LABORATORY WORK FOR SHIFT REGISTERS:

SISO:

CLOCK RESET INPUT FF0(Q) FF1(Q) FF2(Q) OUTPUT(Q) OUTPUT

VERIFIED(Y/N)

- 0 0 0 0 0

1 1 1 1 0 0 0

1 1 1 1 1 0 0

1 1 1 1 1 1 1

SIPO:

CLOCK RESET INPUT FF0(Q) FF1(Q) FF2(Q) OUTPUT(Q) OUTPUT

VERIFIED(Y/N)

- 0 0 0 0 0

1 1 1 1 0 0 1

1 1 1 1 1 0 1

1 1 1 1 1 1 1

PISO:

CLOCK RESET LOADSHIFT / I0 I1 I2 OUTPUT(Q) OUTPUT

VERIFIED(Y/N)

- 0 - - - - 0

1 1 0 1 1 1 0

1 1 1 1 1 1 0

1 1 1 1 1 1 0

1 1 1 1 1 1 1

PIPO:

CLOCK RESET I0 I1 I2 Q0 Q1 Q2 OUTPUT

VERIFIED

0 - - - 0 0 0

1 1 1 0 1 1 0 1



Procedure:

1. The Johnson Counter circuit is designed and the Boolean function is found out.



+5V supply.




1. Define shift registers.

2. What is the difference between serial and parallel transfer? Which type of

register is used in each case?

3. What is universal shift registers?



4. What are the applications of shift registers?

5. What are all the types of shift registers?



Knowledge 20

Design 30

Analysis 20

Ethics 10

Communication 10

Team Work 10

Total 100

Signature

Result:



Date:

EX.NO:9 RIPPLE COUNTERS AND SYNCHRONOUS COUNTERS

Aim:

To Realize the Ripple Counter and Synchronous counter using IC 74XX‟s and

to verify the truth table.

Apparatus required:

Ripple Counter:

Theory:

In a ripple counter, the flip-flop output transition serves as a source for

triggering other flip-flops. In other words, the Clock Pulse inputs of all flip-flops

(except the first) are triggered not by the incoming pulses, but rather by the transition

that occurs in other flip-flops. A binary ripple counter consists of a series connection of

complementing flip-flops (JK or T type), with the output of each flip-flop connected to

the Clock Pulse input of the next higher-order flip-flop. The flip-flop holding the LSB

receives the incoming count pulses. All J and K inputs are equal to 1. The small circle

in the Clock Pulse /Count Pulse indicates that the flip-flop complements during a

negative-going transition or when the output to which it is connected goes from 1 to 0.

The flip-flops change one at a time in rapid succession, and the signal propagates

through the counter in a ripple fashion. A binary counter with reverse count is called a

binary down-counter. In binary down-counter, the binary count is decremented by 1

with every input count pulse.


1 Trainer Kit - 1

2 J-K Flip Flop IC 7476 4

3 AND (2 input) IC 7408 2

4 OR gate IC 7432 1

Connecting wires - Required



Pre Laboratory Work For Ripple Counter:

(Truth Table, Design and Logical Diagram)



Synchronous Counters:

Ring counter:

Theory:

A ring counter is a circular shift register with only one flip-flop being set at ay

particular time; all others are cleared. The single bit is shifted from one flip-flop tot the

other to produced the sequence of timing signals.

Pre laboratory work for Ring Counter:




Johnson counter:

Theory:

A Johnson counter (or switchtail ring counter, twisted-ring counter, walking-

ring counter, or Moebius counter) is a modified ring counter, where the output from the

last stage is inverted and fed back as input to the first stage.[1][2][3]

A pattern of bits

equal in length to twice the length of the shift register thus circulates indefinitely. These

counters find specialist applications, including those similar to the decade counter,

digital to analogue conversion, etc.

Pre laboratory work for Ring Counter:


http://en.wikipedia.org/wiki/Counter#cite_note-0





On Laboratory Work for Ripple counter and Synchronous counter:

Ripple Counter:

CLOCK RESET Q0 Q1 Q2 OUTPUT

VERIFIED(Y/N)

- 0 0 0 0

1 1 0 0 1

1 1 0 1 0

1 1 0 1 1

1 1 1 0 0

1 1 1 0 1

1 1 1 1 0

1 1 1 1 1

Ring Counter

CLOCK PRESET Q0 Q1 Q2 OUTPUT

VERIFIED(Y/N)

- 0 1 0 0

1 1 1 0 0

1 1 0 1 0

1 1 0 0 1

Jhonson Counter

CLOCK RESET Q0 Q1 Q2 OUTPUT

VERIFIED(Y/N)

- 0 0 0 0

1 1 1 0 0

1 1 1 1 0

1 1 1 1 1

1 1 0 1 1



Procedure:

1. The Ring and Johnson Counter circuit is designed.


+5V supply.





1. What is a counter?

2. Differentiate synchronous and asynchronous counter.

3. What is a ripple counter?



4. What is meant by programmable counter? Mention its applications.

5. What are the applications of counter?



Knowledge 20

Design 30

Analysis 20

Ethics 10

Communication 10

Team Work 10

Total 100

Signature

Result:



Date: Ex.No:10 SEVEN SEGMENT DECODER

Aim:

To set up and test a 7-segment static display system to display numbers 0 to 9.

Apparatus required:

THEORY:

Decoder is combinational circuit that converts binary information from the n coded inputs to a

maximum of 2n

unique outputs. The decoder presented on this experiment are called n-to-m line

decoder where m≤ 2n. Its purpose is to generate the 2

n (or fewer) minterms of n input

variables

The operation of 7447 decoders may be clarified form the truth table. For each possible

input combination, there are seven outputs that are equal to 0 and only one that is equal to 1. The

output variable equals to 1 represents the minterm equivalent of the binary number that is applied to

the input lines.

A seven segment display, as its name indicates, is composed of seven elements. Individually

on or off, they can be combined to produce simplified representations of the arabic numerals.

Seven-segment displays may use liquid crystal display (LCD), arrays of light-emitting diodes

(LEDs), and other light-generating or controlling techniques such as cold cathode gas discharge,

vacuum fluorescent, incandescent filaments, and others.

A resistor is a two-terminal electronic component that produces a voltage

across its terminals that is proportional to the electric current through it in

accordance with Ohm's law V= IR. This is used to impede the flow of current. Four-

band identification is the most commonly used color-coding scheme on resistors. It

consists of four colored bands that are painted around the body of the resistor. The first

two bands encode the first two significant digits of the resistance value, the third is a

power-of-ten multiplier or number-of-zeroes, and the fourth is the tolerance accuracy,

or acceptable error, of the value.


1 Trainer Kit - 1

2 Decoder IC7447 1

3 7 Segment Display 1

4 Resistor

Connecting wires - Required



http://www.bragitoff.com/wp-content/uploads/2015/10/seven-segment-dispay-7.png



Pre Laboratory work for Seven Segment Display:

(Truth Table , Logical Diagram)

Truth Table:

BCD Outputs Output

Verified

A B C D a b c d e f g (Y/N)

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

Circuit Diagram:



Procedure:

a) Write down the truth table with 4 inputs and 7 outputs.

b) For only the output “a”, obtain a minimum logic function. Realize this function

using NAND gates and inverters only. For example, if decimal 9 is to be displayed

a, b, c, d, f, g must be 0 and the others must be 1 (For common anode type display

units), if decimal 5 is to be displayed then a, f, g, c, d must be 0 and the others must

be 1.

c) Connect the output “a” of your circuit to appropriate input of 7-segment display

unit. By applying BCD codes verify the displayed decimal digits for that segment

for “a” of the display.

d) Replace your circuit by a decoder IC 7447 for all of the seven segments. Observe

the display and record the segments that will light up for invalid inputs sequence.

e) Comment on the design if you don‟t want to see any digit for invalid input

sequence.


1. What is seven segment decoder?

2. What are the applications of seven segment decoder?



3. Differentiate LCD with seven segment display.

4. What is BCD adder?

5. Can a decoder function as a Demultiplexer?





Knowledge 20

Design 30

Analysis 20

Ethics 10

Communication 10

Team Work 10

Total 100

Signature

Result:



Date:

EX.NO.:11 MEMORY DEVICES Aim:

To store a set of data in a RAM using IC 2114 starting from location ------- to

location----- --- and retrieve the same data.

Apparatus Required:


1 Prototyping Board (Bread Board) - 1

2 DC power supply 5v - 1

3 IC IC2114 1


Theory: Static random-access memory (SRAM) is a type of semiconductor memory

that uses bistable latching circuitry to store each bit. The term static differentiates it from dynamic RAM (DRAM) which must be periodically refreshed. SRAM exhibits data, but it is still volatile in the conventional sense that data is eventually lost when the memory is not powered.

Pin Diagram for IC 2114:

Pin Names A0 - A9 Address Inputs I/O1 - I/O4 Data Input/Output

WE*- Write Enable Input (Active LOW) CS* - Chip Select Input (Active LOW) Vcc -

Power (+5Vdc)



Address Inputs

A3 A2 A1 A0

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

Data Inputs

I/O4 I/O3 I/O2 I/O1

0 0 1 0

0 1 0 0

0 1 0 1

0 1 1 0

Data Outputs

I/O4 I/O3 I/O2 I/O1

0 0 1 0

0 1 0 0

0 1 0 1

0 1 1 0

GND - Ground (0Vdc)

Example for Data Input:-

Example for Data Output:

Address Inputs

A3 A2 A1 A0

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1



Pre Laboratory Work for Memory Devices:



Procedure:

1. Circuits connections are made to the appropriate pins of IC 2114

2. First you have to write the data and then read the data, for writing data make WE to

low and

CS input to low.

3. For a 4-bit data select any address input from A0 to A9. For ex, select A3 to

A0 and connect the data inputs/ outputs i.e., I/O4 – I/O1

4. Write a 4-bit data of your choice in each of the required address inputs or memory

locations

5. By doing the above steps 2, 3 and 4 the data will be stored in the memory location

6. For reading data

a. Make WE to high and CS input to low

b. Disconnect the data inputs I/O4 – I/O1 from input lines and

connect them to output lines to read the data

c. Give the address inputs of the data you have stored and observe the

outputs through

I/O4 – I/O1.


1. How the memories are classified?

2. Compare and contrast static RAM and dynamic RAM.



3. What is PLD? List their types.

4. Distinguish between PAL and PLA.

5. Which memory is called volatile? Why?





Knowledge 20

Design 30

Analysis 20

Ethics 10

Communication 10

Team Work 10

Total 100

Signature

Result:



Date:

EX.NO:12 ANALOG TO DIGITAL CONVERTERS

Aim:

To rig up circuit to convert an analog voltage to its digital equivalent

Apparatus Required:


1 Prototyping Board (Bread Board)

- 1


3 IC IC LM 324, IC 7400 1,1

4 Resistors 10k,100k 4,1

5 Multimeter - 1


Theory:

A Flash ADC (also known as a Direct conversion ADC) is a type of

analog-to-digital converter that uses a linear voltage ladder with a comparator at each "rung" of the ladder to compare the input voltage to successive reference voltages. Often these reference ladders are constructed of many resistors; however modern implementations show that capacitive voltage division is also possible. The output of these comparators is generally fed into a digital encoder which converts the inputs into a binary value.



Pre laboratory work for Analog to Digital Convertor:



Circuit Diagram:



PROCEDURE: 1. Connect the circuit as per the circuit diagram. 2. Verify the digital O/P for different analog voltages.

Note: (1). Connect V+ (pin 4) terminal of the OPAMP to +5V

(2). Connect V- (pin 11) terminal of the OPAMP to ground

Design: Number of comparators required = 2n-1 Where n = desired number of bits C1, C2 & C3 = Comparator o/p D0 & D1 = Encoder (Coding network) O/P.


1. Why ADC?

2. Explain the operation of basic sample and hold circuit.

3. What are the types of ADC?



4. What is the difference between direct ADC and integrating type ADC?

5. What are the applications of ADC?



Knowledge 20

Design 30

Analysis 20

Ethics 10

Communication 10

Team Work 10

Total 100

Signature

Result:



Date:

EX.NO:13 SYNCHRONOUS FINITE STATE MACHINE

Aim:

To understanding Mealy and Moore machine analysis of a sequence detector

and compare the results.

Apparatus Required:


1 Prototyping Board (Bread Board)

- 1


3 IC IC 7476, IC7402 1,1


Theory:

A sequence detector accepts as input a string of bits: either 0 or 1. Its

output goes to 1 when a target sequence has been detected. There are two basic

types: overlap and non-overlap. In sequence detector that allows overlap, the final

bits of one sequence can be the start of another sequence. Our example will be a

11011 sequence detector. It raises an output of 1 when the last 5 binary bits received

are 11011. At this point, a detector with overlap will allow the last two 1 bits to

serve at the first of a next sequence. By example we show the difference

between the two detectors. Suppose an input string 11011011011.

11011 detector with overlap X 11011011011

Z

00001001001

11011 detector with no overlap

Z

00001000001

The sequence detector with no overlap allowed resets itself to the start state when the

sequence has been detected. Write the input sequence as 11011 011011. After the

initial sequence 11011 has been detected, the detector with no overlap resets and

starts searching for the initial 1 of the next sequence. The detector with overlap

allowed begins with the final 11 of the previous sequence as ready to be applied as

the first 11 of the next sequence; the next bit it is looking for is the 0.



Preliminary Lab. Work:

Design a circuit which detects (011) sequences in a string of bits coming

through an input line (i.e., the input is a serial bit stream). Once the (011) sequence

is detected, output becomes (1), otherwise it stays as (0). A sample input and output

bit streams (sequence) are given below. First bit coming to the input is the one

shown on the far left.

Example Input bit stream: 01101111011

Example Output bit stream: 00100100001

Before coming to LAB, find the state diagrams of this

sequence detector a) As a Mealy machine

b) As a Moore machine.

Two realizations (Mealy, Moore) of the above sequence detector are given below.

Moore and Mealy Realization of (011) sequence detector.



Pre laboratory work for Moore and Mealy machine:



Procedure: 1. Set up the above given Mealy machine on your board. 2. Do not forget power and ground connections.

3. Use standard switches (TTL SWT) for the preset and the clear control inputs as

required.

4. Use a standard switch (TTL SWT) for the x input.

5. Use negative pulsar switch for the clock input.

6. Use LED s for states and z output observations.

7.Verify your Mealy machine realization on the breadboard with state diagram you

found in prelab work.

8.Apply the above given sample input bit stream (sequence) and observe output

stream.

9. Draw time diagrams for the (x) input, (y1, y2) state variables and z output

Attention: 1.For each input there should be a clock pulse (In this case 18 pulses required) 2. Initial state: 00 should be arranged by preset and clear inputs. You have to

rearrange above example input stream right after initial state has been applied.


1. Compare Asynchronous and Synchronous sequential logic.

2. What is latch? What is the difference between latch and flip flop?



3. Define the terms State table and State Assignment.

4. What are races and cycles?

5. What are hazards?





Knowledge 20

Design 30

Analysis 20

Ethics 10

Communication 10

Team Work 10

Total 100

Signature

Result:



APPENDICES



Rubric for Pre-Lab Work

Criteria Beginning or

incomplete

Developing Accomplished Exemplary

Knowledge

No grasp of

required subject

matter. No

understanding

of major issues.

(0)

Only basic

concepts are

demonstrated

and interpreted.

(1-10)

Able to

elaborate and

explain to some

degree.

(10-15)

Demonstration of

full knowledge of

the subject with

explanations and

elaboration.

(15-20)

Design

Very

ineffective.

Would not

allow

experimenters

to achieve any

goals

(0-5)

Somewhat

ineffective.

Would allow

experimenter(s)

to achieve some

goals.

(5-10)

Somewhat

effective.

Would allow

experimenter(s)

to achieve most

goals.

(10-20)

Effective. Would

allow

experimenter(s) to

achieve all goals.

(20-30)

Analysis

Analysis

methods were

completely

misapplied or

absent.

(0)

Analysis

methods were

attempted.

Some methods

were applied

but with

significant

errors or

omissions.

(1-10)

Analysis

methods were

attempted.

Most methods

were correctly

applied but

more could

have been done

with the data.

(10-15)

Analysis methods

were fully and

correctly applied.

(15-20)

Ethics

Not handed in

more than one

week late. Does

not follow

instructions.

(0)

Up to one week

late. Rarely

follows

instructions

and/or requires

constant

assistance.

(1-5)

Up to two days

late. Reads and

follows

instructions but

requires

assistance.

(5-8)

Handed in on

time. Reads and

follows

instructions

competently and

accurately.

(8-10)

Communication

-Presentation

has limited

organization.

(1-3)

-Presentation is

fairly well

organized

(3-5)

-Presentation is

well organized

(5-8)

-Presentation is

exceptionally well

organized

(8-10)

Team work

Does not work

with group

members to

complete tasks

(0)

Rarely works

collaboratively

with group

members to

complete tasks

(1-5)

Sometimes

works

collaboratively

with group

members to

complete tasks

(5-8)

Works

collaboratively

with group

members to

complete tasks.

(8-10)



Rubric for Model Lab

Criteria

Exemplary

Proficient

Fair

poor

Analysis

and Design

(All circuit

diagrams

programs,

& truth

tables.)

(35pts)

The program,

diagrams and

truth tables are

95- 100%

accurate, and

are very neatly

designed &

drawn

(30 -35 pts)

The programs,

diagrams and

truth are 70 -

95% correct

and/or is sub-

exemplary in

designing &

drawing

quality.

(25 -30 pts)

The programs,

diagrams and

truth tables are

40 to 70%

correct and/or

is poor in

designing &

drawing

quality.

(15 -25 pts)

The programs,

diagrams and

truth tables are <

40 % correct and

are poor in

designing &

drawing quality.

Does not know

how to design

(0-15 pts)

Experimen

t

Conductio

n

(25 pts)

80-100% of the

required design

elements are

obtained

properly.

(20-25) pts)

80 -60 % of the

design

elements are

obtained

properly

(15 -20 pts).

60-40% design

elements are

obtained

properly.

(10 -20 pts)

Less than 40%

design elements

are obtained

properly

(0-10 pts)

Completed

all parts of

the

laboratory

(20 pts)

90-100%

Completed

(18-20 pts)

75%-

90%completed,

without any

help

(15- 20 pts)

40-75%

completed,

with help

(10-15 pts)

<40% completed

or not done

(0-10 pts)

Interpretat

ion

(10 pts)

The results are

interpreted

correctly and

with

demonstrated

understanding

of the design.

(9-10 pts)

The results are

interpreted

correctly not in

a complete

manner with a

little

bunderstanding

of the design.

(6-8 pts)

The results are

not interpreted

correctly.

(4-6 pts)

Does not know

about the

material.

(0-3pts)

Safety

(10 pts)

Safety

instructions

were carried

completely;

(10 pts)

Safety

instructions

were carried

after

instruction

from faculty;

(7-9pts)

Safety

instructions

were carried

after many

instructions

from faculty;

(4-7 pts)

Safety

instructions were

not carried;

(0-3 pts)



Rubric For Mini Project

Criteria Poor Fair Good Very

good

The project is written

The project is a little

The project is The project is neat

Attractiveness and

on notebook

paper,

messy or

disorganized.

somewhat neat

and and organized.

or is very sloppy.

organized.

Organization

Project does not Project is missing Project meets Project exceeds

Requirements meet some requirements requirements.

requirements. requirements.

The student spent little

The student did not

The student spent some

The student spent a great

or no time

planning the

spend enough

time

time planning.

The

deal of time

planning.

Creativity and

planning

project. The

project

planning. The

project

project is

somewhat The project

shows no original is lacking in

creativity

creative and

original.

is creative and

original. thought or

creativity. and originality.

Student put in little

Student put in some

Student spent a great

Student went above

Teamwork and

Effort effort. time and effort.

deal of time and

effort. and beyond.

Responses to Responses are partially

Most questions are

All questions are

Responses to

specific

questions are correct but show

major

answered

correctly.

answered

correctly.

completely

incorrect conceptual errors.

questions



PIN DIAGRAMS





IC7411

IC7474

IC7474

IC7476

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Realization of Logic Gates - WordPress.com...Basic Electrical and Electronics Engineering (EEE101), Digital Electronics (ECE202) Course Description This course will impart the concepts