RBSP Radiation Belt Storm Probes RBSP Radiation Belt Storm Probes RBSP/EFW I-PER 21 January EFW Instrument Testing to Date Michael Ludlam for EFW Team Space Sciences Laboratory University of California, Berkeley RBSP/EFW I-PER 21 January 2011Michael Ludlam 72 Overview IDPU Board Testing DCB & FSW LVPS BEB DFB Boom Qualification AXB SPB Instrument Testing IDPU Integration Boom Deployments AC Test / BEB sensor control Noise, Timing, Phasing Calibration RBSP/EFW I-PER 21 January 2011Michael Ludlam 73 DCB Testing Both FM DCB boards have completed & passed their board functional test (RBSP_EFW_DCB_009) Boards have been integrated into IDPU and function correctly with other boards and booms. FSW v3.00 burned into PROMs. Installed on boards. Initially some problems, but failure analysis is pointing towards lead bending procedure. New parts bent correctly both work on flight units. Limited thermal testing was conducted & passed to verify no thermal issues. Other DCB modifications Flash FET switches layout reversed. Rework fix. Addition of inductor to suppress SEE induced transients from MSK regulators. Flight board termination was different than ETU requiring a number of resistor changes. RBSP/EFW I-PER 21 January 2011Michael Ludlam 74 DCB Photo RBSP/EFW I-PER 21 January 2011Michael Ludlam 75 FSW Status FSW complete. Burned in PROMs after completion of CPT on ETU. All Analyses completed : RBSP_EFW_FSW_004_Analyses.xls Comprehensive Test Report : RBSP_EFW_FSW_020C_CPT_ pdf Code Inspection Report : RBSP_EFW_FSW_021_Inspection.pdf Long Duration Stress Test Report : RBSP_EFW_FSW_022B_LDS_Report.pdf RBSP/EFW I-PER 21 January 2011Michael Ludlam 76 Summary FSW Development PROM Software Contains all Required Functions EEPROM is empty at this point On-Board Scripts Room Available in PROM No Scripts Defined Verification at the Box & Instrument levels (Not FSW-level) GSE/SOC Flash Memory MET-to-Block data management Boom Door Opening & Wire Deployment Real Data Compression (Requires Signals In, SOC to decode) EEPROM test in TVAC RBSP/EFW I-PER 21 January 2011Michael Ludlam 77 RBSP LVPS Testing (1) LVPS Testing completed on both boards. All functions passed. LVPS Testing is divided into sections 1- BEB Digital and Analog 2- IDPU Digital 3- IDPU Analog 4- BEB 225V These four sections have the same topology. The following tests were performed to verify their function individually: Frequency Adjustment to 187KHz FET Gate and Drain Waveform Check Verify Output Voltages Load Test (half load/ full load/no load) Output Ripple Measurement Line Test where S/C Voltage is varied from 24V to 35V Short Circuit Protection Test where a 1 Ohm resistor load is applied and the circuit recovers from this large load. RBSP/EFW I-PER 21 January 2011Michael Ludlam 78 RBSP LVPS Testing (2) LVPS Testing completed on both boards. All functions passed. LVPS Testing is divided into sections - section 5: 5- Floaters Output Voltage Range Load tests Output Ripple Measurement Line Voltage Test Short Circuit Protection Test SYNC test Verified that all sections are operating at 200KHz when the internal clock is activated Verified that when an external Clock is applied all sections are synchronized Verified that internal crystal is turned off when an external clock is applied Housekeeping Inrush Current 40V Survival test RBSP/EFW I-PER 21 January 2011Michael Ludlam 79 RBSP LVPS testing (3) Power Control Board Testing Reference Voltage is verified Housekeeping Monitor values are verified. Motors, Doors and Stacers Activation verified using a tester that consists of resistors and LEDs Each command was sent separately and the current consumption is recorded. RBSP/EFW I-PER 21 January 2011Michael Ludlam 80 LVPS Photo RBSP/EFW I-PER 21 January 2011Michael Ludlam 81 All Digital Fields Boards Delivered All 3 DFBs delivered to Berkeley All tested and qualified for flight DFBs meet or exceed all performance requirements No known performance deficiencies RBSP/EFW I-PER 21 January 2011Michael Ludlam 82 DFB Entrance Criteria All Met All Requirements Verified Release/signature process complete All RFAs closed Deviation or Waivers Completing release/signature process on 1 remaining waiver for PCB bake-out recording. CCB approved 1/3/11. One Part issue in resolution Op-Amp failure analysis in process by APL End-Item-Data Packages completing FM-1 complete and delivered to Berkeley FM-2 & FM-3 waiting on outstanding waiver RBSP/EFW I-PER 21 January 2011Michael Ludlam 83 Extensive Testing on all DFBs All board-level testing complete on all DFBs per the test plan Tested the full default configuration of each DFB Science data products including: Survey and Burst data from the digital filters, Trigger data, Spectral data, and Cross spectral data Synch to 1 PPS test, super-synch (long and 1sec) Full Analog section testing - 16K ADC sampling Stimulated analog inputs create proper response on the appropriate digital outputs Verified that each digital data product can access all its commandable sources. Obtained calibration data Gains, Offsets, Crosstalk and Noise Characteristics Long duration testing ran on each board 3-4 days each Thermal cycle testing between -25 to +55 on all DFBs No open work remaining on any DFB RBSP/EFW I-PER 21 January 2011Michael Ludlam 84 DFB Tests Performed Register Read TestSpectral Dynamic Enable Test Spectral IDL CompareCross-Talk Test Full Default TestSpectral Bins TestCross-Spectral IDL Compare Noise Test ADC MUX Switching Test Cross-Spectral Bins Test FAP Initial Functionality Test Gain Test Waveform Verify Channel Test Spectral Dynamic Bins Test Spectral FAP TestThermal Test Trigger Vavg TestSpectral Cycle Ncad Test Super-synch Test IPower Draw Waveform Maximum Bandwidth Test Cross-spectral Cycle Ncad Test Super-synch Test IIFAP IDL Comparison Spectral Bandwidth Test Spectral Dynamic Ncad and Navg Test Trigger Frequency Response Test Invalid Configurations Test Trigger Cycle Sources Test Triggers Speed Select Test Waveform Frequency Response Test Digital Filter Delays Spectral Cycle Sources Test Waveform IDL Compare Test AC Common Mode Rejection Test Frequency Response Testing Cross-Spectral Cycle Sources Test Trigger IDL Compare Test DC Common Mode Rejection Test Signal Integrity and Timing Tests RBSP/EFW I-PER 21 January 2011Michael Ludlam 85 BEB Testing The following tests were performed during bench testing of the BEB. DC offset Test DAC and MUX Setting Verification test DC Gain Verification Frequency Response Verification EMFISIS Distortion Test EMFISIS Frequency Response AC Test Line Verification RBSP/EFW I-PER 21 January 2011Michael Ludlam 86 BEB Example Results All measurements were in specification. More details in Calibration slides. Gain Frequency (Hz) RBSP/EFW I-PER 21 January 2011Michael Ludlam 87 BEB Photo RBSP/EFW I-PER 21 January 2011Ludlam 88 Boom Qualification All AXB and SPB units have completed qualification program RBSP/EFW I-PER 21 January 2011Ludlam 89 Axial Booms (AXB) Jeremy McCauley Aerospace Engineer Space Sciences Laboratory, UCB AXB Spacecraft +Z RBSP/EFW I-PER 21 January 2011Ludlam 90 EFW AXB Environmental Testing Integrate Stacer, Whip and Cage Electrical Functional Test Science Calibration Whip and Cage Mechanical Functional Stacer Mech Functional, Length & Runout Measurement, Continuity Check PER Mass Properties Integrated Vibration Test Electrical Functional Test Dis-Integrate Stacer, Whip and Cage Stacer Mech TV Hot Deploy, Length & Runout Measurement, Continuity Check Integrate Stacer, Whip and Cage PSR Whip and Cage TV Hot Deploy Whip and Cage TV Cold Deploy RBSP/EFW I-PER 21 January 2011Ludlam 91 EFW AXB I&T: Deployments Functional Deployments Expected number of deployments on the instrument at launch: 5 Functional (MIP) Post Vibe Functional (test as you fly exception) Thermal Vacuum Hot Thermal Vacuum Cold INT Deployment with IDPU and Flight Harness Deployments of Whip and Cage at SC Level after Vibe All stacer deployments include: Frangibolt and Motor trending, EOT Switch verification, Continuity verification, Runout and Stiffness testing. RBSP/EFW I-PER 21 January 2011Ludlam 92 EFW AXB I&T: Alignment Alignment Testing Runout Requirement: