PT TAU 2011 Paper Singhal

1© Synopsys 2011

Comparing Constraint Behavior

to Determine Equivalency

TAU 2011

Sonia Singhal

Loa Mize

Subramanyam Sripada

Szu-Tsung Cheng

Cho Moon

2© Synopsys 2011

Communicate design requirements and intent to

implementation and analysis tools

Constraints

MCP 2create_clock

–name CLKA

–period 10

–edges {0 5 10}

[get_port clka]

create_clock

–name CLKB

–period 50

–edges {0 20 50}

[get_port clkb]

set_input_delay

2.75

-clock CLK1

-setup

[get_ports in1]

set_output_delay

1.5

–clock CLK1

–setup

[get_ports out1]

set_multicycle_path 2

-from [get_pins

ff1/CP

- to [get_pins

ff2/D]

set_false_path

-from CLKA –to CLKB

set_false_path

-from CLKB –to CLKA

Constraint file size can be more than a few gigabytes

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• Constraints in different forms can have the same effect– compressed vs. non-compressed constraints

set_false_path –from A –to Z

set_false_path –from B –to Z

vs.

set_false_path –from {A B} –to Z

- set_false_path, set_case_analysis, set_disable_timing, set_clock_group

- Different syntax and representation

- Different propagation effects on the netlist

- Similar effect (disable) on the design

• Constraints change form during the flow– Implementation and Analysis tools

– Experts know which form has potential benefits in runtime and faster timing closure

Motivation

Pair-wise comparison not enough

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• Partially overridden, partially invalid constraints along with constraint precedence cannot be matched simply by comparing the netlist objects of the constraints

MotivationConstraints overlap and override

rA

rB

rX

rY

inv

and

set_multicyle_path 3 \

–through [get_pins inv/Z]

set_multicycle_path 2 \

-through [get_pins and/Z]


–from [get_pins rA/CP]


–through [get_pins and/Z]

Behavior Not

Equivalent

5© Synopsys 2011

?

Motivation

rA

rB

rX

rY

u1

u2

rA

rB

rX

rY

u1

u3

set_false_path –from rB

–through u1/Zset_false_path –from rB

–through u1/Z

Netlist optimizations – 2 netlists, same constraint-set

• Netlist optimizations have led to bad chips despite no changes in logical functionality and constraints• There is a strong need to compare constraint behaviors (effects of constraints on designs)

6© Synopsys 2011

Timing relationships

rA

rB

rX

rY

and

Clk

Clk

Clk

Clk

create_clock –period 10

–name Clk[get_ports Clk}

set_multicyle_path 2

–through [get_pins inv/Z]

set_false_path

-through [get_pins and/B]

Timing

start-point

Timing

end-point

Launch

clock

Capture

clock

Min/ Max/

Rise/ Fall

State

* rX/D Clk(r) Clk(r) All MCP(2)

rA rY/D Clk(r) Clk(r) All MCP(2)

rB rY/D Clk(r) Clk(r) All FP

We create a minimal set of Timing Relationships necessary to describe

the design and its constraints.

Constraint representation for a set of paths

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Compares the timing relationships of a set of paths across 2 netlist-constraint sets using a multi-pass gradual refinement method:

– Pass 1: Fast method to detect mismatches of all paths reaching an endpoint.

– Pass 2: Main method to detect matches/mismatches for all paths between a startpoint-endpoint pair.

– Pass 3: Detailed method to remove remaining potential mismatches involving reconvergence points

Constraint Comparison AlgorithmThree Pass Approach

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• Check same state for each endpoint timing relationship

• Fast - Single bread-first traversal on netlist.

• Only endpoints with multiple matching timing relationships need further analysis

Pass 1Compare the effect of constraints on timing path endpoints between 2 netlist/constraint pairs

Exception state

- None

- False

- Cycle relationship

- set_min_delay/set_max_delay

value

Value

- Launch clock and clock edge

- Timing Endpoint

- Capture clock and clock edge

- Endpoint data rise/fall

- Min and Max path

Key

9© Synopsys 2011

Pass 1Example

rB

rC

rY

rZ

inv2

and

Clk

Clk

Clk

Clk

rA rX

inv1

ClkClkset_false_path –from [get_pins rA/CP]

set_false_path –from [get_pins rB/CP]


–from [get_pins rC/CP]

set_false_path –from [get_pins rA/CP]


–from [get_pins rB/CP]

set_false_path –from [get_pins rC/CP]

First constraint set

Second constraint set

Timing

start-point

Timing end-

point

Launch

Clock

Capture

Clock

Min/Max/

Rise/ Fall

1st set’s

state

2nd set’s

state

Pass1

Result

* rX/D Clk(r) Clk(r) All FP FP Match

* rY/D Clk(r) Clk(r) All FP MCP Mis-match

* rZ/D Clk(r) Clk(r) All FP, MCP (2) FP, MCP (2) Needs

further

analysis

10© Synopsys 2011

• Check same state for each startpoint-endpoint pair’s timing relationship

Pass2Compare the effect of constraints on timing path between startpoint-endpoint pairs across 2 netlist/constraint pairs

-Timing Startpoint

- Launch clock and clock edge

- Startpoint data rise/fall

- Timing Endpoint

- Capture clock and clock edge

- Endpoint data rise/fall

- min and max path

Exception state

- None

- False

- Cycle relationship

- set_min_delay/set_max_delay

value

KeyValue

• Each inconclusive endpoint left over from Pass1 is analyzed

• Data gathered for all startpoints to the endpoint to be analyzed and

cleared before proceeding to next endpoint

• Highly parallelizable

11© Synopsys 2011

Pass 2Example

rB

rC

rY

rZ

inv2

and

Clk

Clk

Clk

Clk

set_false_path –from [get_pins rB/CP]


–from [get_pins rC/CP]


–from [get_pins rB/CP]

set_false_path –from [get_pins rC/CP]



Timing

start-

point

Timing

end-

point

Launch

clock

Capture

clock

Min/

Max/

Rise/

Fall

1st set’s

state

2nd

set’s

state

Result

rB/CP rZ/D Clk(r) Clk(r) All FP MCP

(2)

Mismatch

rC/CP rZ/D Clk(r) Clk(r) All MCP (2) FP Mismatch

12© Synopsys 2011

Pass 3Compare multiple timing relationships due to reconvergent points

rA

mux

rB

set_multicycle_path 2 -through mux/B



set_multicycle_path 2 –through mux/A

Timing

start-

point

Timing

end-

point

Re-

convergent

Points

1st Set

State

2nd Set State Result

rA/CP rB/D mux/A MCP(2) Cycle (1) Mismatch

rA/CP rB/D mux/B Cycle(1) MCP(2) Mismatch

13© Synopsys 2011

Block constraints vs Top ConstraintsBottom-up or Top-down design flow validation

MCP 2create_clock

–name CLKA

–period 10

–edges {0 5 10}

[get_port clka]

create_clock

–name CLKB

–period 50

–edges {0 20 50}

[get_port clkb]

set_input_delay

2.75

-clock CLK1

-setup

[get_ports in1]

set_output_delay

1.5

–clock CLK1

–setup

[get_ports out1]


-from [get_pins

ff1/CP

- to [get_pins

ff2/D]

set_false_path

-from CLKA to CLKB

set_false_path

-from CLKB to CLKA

Bottom-up flow:

1. Block-level constraints are created

2. Block is optimized alone then integrated with chip

USB core

Chip_Top

Clock

Signals?

Input

Signal?

Output

Signal ?

MCP?

False clock

relationship?

Bottom-up flow:

3. Constraints are propagated up to top level

4. User wants to ensure that top-level constraints are complete

14© Synopsys 2011

Design #instances

(M)

Single

Core

(sec)

4 cores

(sec)

X factor Single

Core

(GB)

4 cores

(GB)

D1 0.7 97 45 2.2 1.70 1.70

D2 1.2 215 60 3.6 5.43 5.43

D3 2.2 7 2 3.5 0.29 0.29

D4 2.2 58 24 2.4 2.84 2.84

D5 3.5 1442 718 2 26.7 26.7

D6 4.4 59952 15901 3.8 7.85 7.85

D7 4.7 420 133 3.2 7.94 7.94

D8 5.4 5952 2521 2.4 12.55 12.55

ResultsSingle netlist and 2 constraints

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Design #instances in

Top (M)

#instances in

Block (M)

Runtime (CPU

Sec)

Top1/Block1 4.7 1.5 182

Top1/Block2 4.7 0.9 212

Top2/Block1 1.4 0.6 109

Top2/Block2 1.4 0.5 309

Top3/Block1 1.1 0.2 14

Top3/Block2 1.1 0.2 8

ResultsBlock Constraints vs top Constraints

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• Efficient solution that compares two constraint behaviors

– Compare compressed vs. non-compressed exceptions

– Compares different constraints with similar affects (false paths vs. set_case_analysis)

– Accounts for precedence rules

• Easily parallelizable

• Timing relationships help report mismatches in form of original user constraints

• Many applications

Advantages of our approach

Summary

17© Synopsys 2011

Questions…

Thank You

Documents

PT TAU 2011 Paper Singhal