PSP model update Gert-Jan Smit, Andries Scholten, D.B.M. Klaassen (NXP Semiconductors)

Ramses van der Toorn (Delft University of Technology)

MOS-AK, San Francisco

12 December 2012

outline

some history

brief overview of PSP – benefits for analog/RF design

recent updates – simulation speed (not shown)

– self heating

– improved thermal noise model implementation

summary

2

history

2005: PSP created by merging SP (Pennsylvania State University) and

MOS Model 11 (Philips)

2005: PSP 102 is elected as CMC standard MOS model – Arizona State University (formerly PennState): supporting institution

– NXP Semiconductors (formerly Philips): co-developer

2005-2010: several model improvements, introduction of PSP103

2011 – cooperation CMC and Arizona State University ends

– NXP and Delft University of Technology start cooperation on PSP

2012 – CMC re-instates PSP as CMC-standard model

– Delft University of Technology (Prof. Ramses v.d. Toorn):

supporting institution

– December: first PSP release (103.2) from Delft University of Technology

3

PSP-update, MOS-AK 12 December 2012

PSP is available as built-in model in all major circuit simulators

Verilog-A code & documentation available from http://psp.ewi.tudelft.nl

C-code (SiMKit) available from http://www.nxp.com/models

outline

some history

brief overview of PSP – benefits for analog/RF design

recent updates – simulation speed (not shown)

– self heating

– improved thermal noise model implementation

summary

4

core model: surface potential calculation

Poisson equation + Gauss’s law leads

to implicit equation for ψs

ψs can be calculated – with iterative methods (HiSIM, MM1102)

– with analytical approximations

(PSP, SP, MM1101)

PSP: explicit analytical approximation – accuracy <1nV under all relevant conditions)

11 T

s

T

s

T

B

TTs

2

sFBGB

eee

VVV

o

-0.4

0

0.4

0.8

1.2

-1 0 1 2

V GB - V FB (V)

s (

V)

V = 0 V

substrate gate

ox

ide

ψs

EC

EV

5

long channel output conductance

0.0 0.2 0.4 0.6 0.8 1.0 0.0

0.2

0.4

0.6

0.8

1.0

V DS (V)

I D (m

A)

VDS (V)

I D (

mA

)

0.0 0.2 0.4 0.6 0.8 1.0 10

-9

10-8

10-7

10-6

10-5

10-4

10-3

10-2

V DS (V)

g D

S(A

/V)

VDS (V)

gD

S (

A/V

)

ID-VDS and gDS-VDS for VSB=0V and T=25°C

10µm/1µm NMOS (65nm process technology)

symbols measurements lines PSP simulations

6

crucial for analog design!

higher order conductance

0.0 0.4 0.8 1.2 10

-5

10-4

10-3

10-2

10-1

V GS (V)

g m

i (A

/Vi )

0.0 0.3 0.6 0.9

10-3

10-2

10-1

V DS (V)

g D

Si

(A/V

i )

gmi (= iID/ VGSi) vs. VGS

VGS=1.2V

VDS (V) VGS (V)

gD

Si

(A

/Vi )

gm

i (

A/V

i )

PSP ●●● measurement

10/0.12 NMOS

gDSi (= iID/ VDSi) vs. VDS

VDS=1.2V

gm1

gm2

gm3

gDS1

gDS2

gDS3

good results due to PSP’s mobility model and implementation of SCEs 7

crucial for distortion (IP3) modeling

1.E-14

1.E-13

1.E-12

1.E-11

1.E-10

1.E-09

-1.5 -1 -0.5 0 0.5 1 1.5

V GS (V)I G

(

A)

Measurements

MM11

I GB I GS + I GD

I GOV

model

measurements

leakage: gate current

3 components:

S

D

IG

IGD IGS IGB

IGOV

• gate-to-channel current

• gate-overlap current

• gate-to-bulk current

PSP features dynamic (bias dependent)

S/D-partitioning of gate current

8

leakage: junction current

NMOS PMOS

junction voltage (V) junction voltage (V)

I gate

-ed

ge (

A/m

)

BBT

BBT

T=-400C

T=2000C

-2.0 -1.5 -1.0 -0.5 0 0.5 -2.0 -1.5 -1.0 -0.5 0 0.5

10-4

10-6

10-8

10-10

10-12 I g

ate

-ed

ge (

A/m

)

10-4

10-6

10-8

10-10

10-12

advanced CMOS: increasing importance of BBT

65nm technology

9

Non-quasi-static effects

PSP NQS model based on ‘spline collocation method’ – predictive model (no parameter extraction needed)

– based on same physics as segmentation

– more computationally efficient

10

107

108

109

1010

1011

1012

10-4

10-3

10-2

10-1

F (Hz)

Im( Y

11)

( 1

)

V DS = 1 . 2 V

107

108

109

1010

1011

1012

10-5

10-4

10-3

10-2

10-1

F (Hz)

Im( Y

21)

( 1

) V DS = 1 . 2 V

measurement

PSP imag(Y11) imag(Y21)

L=2um (90nm technology), NMOS, various VGS

11

thermal noise modeling

thermal noise originates from resistive nature of MOSFET channel

PSP has a predictive model for thermal noise – based on pure thermal noise

– includes drain current noise, induced gate noise, and correlation

– proper integration along channel, correct transfer to terminals

– valid in all operating regions (linear, saturation, sub-threshold)

source drain local noise

source

gate

correlation

induced gate noise

drain current noise

offset frequency (MHz) 10

-110

0 10

1

-100

-90

-80

-70

of fset frequenc y (MHz)

phas

e nois

e (d

Bc/

Hz)

Digitally controlled oscillator (center frequency 3.43 GHz)

ph

ase

no

ise

(d

Bc/H

z)

PSP w/o induced

gate noise

PSP with induced

gate noise

measurements

outline

some history

brief overview of PSP – benefits for analog/RF design

recent updates – simulation speed (not shown)

– self heating

– improved thermal noise model implementation

summary

12

new in PSP: self heating (i)

motivation: – create possibility to use PSP in macro model for DMOS devices

– possibly also useful for ‘normal’ high-power devices

– useful when analyzing simulation/measurement discrepancies

simple RC thermal network, external thermal node – V(dt)=ΔT

– I0 = Pdiss = Ids * Vds + ...

13

Cth Rth

dt

I0

new in PSP: self heating (ii)

identical parameter sets; with and without self heating

14

Id vs. Vd gds vs. frequency

PSP103 PSP103t

(dc-simulation) (ac-simulation)

new in PSP: self heating (iii)

Vds=2V, pulse Vgs 02V and 20V

15

PSP103 PSP103t ΔT

(tr-simulation)

outline

some history

brief overview of PSP – benefits for analog/RF design

recent updates – simulation speed (not shown)

– self heating

– improved thermal noise model implementation

summary

16

new in PSP: improved noise implementation (i) simplified verilog-A implementation

originally: three independent white noise sources (+ four controlled

sources)

new: two independent white noise sources (+ four controlled sources) – two independent sources are sufficient to create two (partially) correlated

sources

– noise powers and transfer ratios adjusted to ensure unchanged results

– noise powers now all have ‘physical’ values

17

new in PSP: improved noise implementation (ii) improved symmetry

PSP 103.1.1 and before:

Sig-source changes location

when Vds crosses 0

causes a discontinuity in drain

current noise around Vds=0 – only visible at very high frequency

– thought to be harmless

– recently found that this may cause

non-convergence in transient

noise analysis

18

N.B. VX on drain, -VX on source

Vds > 0 Vds < 0 s d

g

s d

g

Sig Sig

new in PSP: improved noise implementation (iii)

solution: induced gate noise partitioning over source and drain – fully physical, bias-dependent, partitioning seems over-the-top

– PSP103.2: 50/50 partitioning (removes discontinuity and solves

convergence issue)

19 N.B. A truly symmetrical plot is obtained when plotting SId+SIs,

but such a plot fails to show the original problem in SId itself!

all Vds s d

g

Sig/2 Sig/2

PSP 103.2 PSP 103.2 older PSP

new in PSP: improved noise implementation (iv)

bonus from 50/50 partitioning:

1st-order NQS effect in Sid!

explanation: – induced gate noise is essentially a

NQS effect

– same effect gives f-dependence on Sid

old model (PSP103.1.1 and before): – induced gate noise source between g & s

– no NQS effect in drain current noise

new model (PSP 103.2.0): – 50/50 partitioning

– induced-gate noise partly flows to drain

– correct 1st-order f-dependence in Sid!

20

comparison of segmentation

(1, 2, 4, 8 segments) with

1-segment model with 50/50

partitioning

summary

PSP is re-instated as CMC-standard model

supporting institution: Delft University of Technology – Prof. Ramses van der Toorn

– also hosts MEXTRAM model

co-developer: NXP Semiconductors

new PSP 103.2 recently released – improved simulation speed

– self heating

– improved implementation of thermal noise model

21

PSP-update, MOS-AK 12 December 2012

self heating: scaling

geometrical scaling – adapted from first version: more PSP-like parameter names and constant

term added

T-scaling for RTH – exponential T-scaling with parameter STRTH

– base on ambient temperature (not device-T), to avoid convergence issues

23

induced gate noise & S/D interchange (iv)

For comparison:

BSIM4, 4.7, tnoimod=2

same problem as previously in PSP, but

smaller magnitude – in BSIM4, induced gate noise is limited to

2x drain current noise

– as a consequence, discontinuity cannot

be larger than factor of 2

24