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PSI - Jun. 27th, 2006 1
Status of the electronics systems of the MEG
experiment
PSI - Jun. 27th, 2006 2
Electronic chain
216
630
ActiveSplitter
1:11:14:1
ActiveSplitter
1:11:14:1
ActiveSplitter
1:11:14:1
Ramp60 120
Pre-Amp8:1
PMT
LXe
HV
PMT
lateral
front
TC
HV
HV
APD
PMTbars
fibers
DC
HV
Wires
Strips
Pre-Amp
Pre-Amp
576
1156
atten
DRSDRS
DRSDRS
DRSDRS
5 crates512
Hit registers
4 boards
TriggerTrigger
Trigger
32
3 crates
Aux. devices
PSI - Jun. 27th, 2006 3
DAQ and control
6 crates
DRSDRS
DRSDRS
DRSDRS
Hit registers
TriggerTrigger
Trigger
3 crates
20 MHz clock
clockstartstopsync
Trigger signalEvent numberTrigger type
Trigger
BusyError
Ancillarysystem
E5 area ‘counting room’
PC (Linux)
PC (Linux)PC (Linux)PC (Linux)PC (Linux)
PC (Linux)
PC (Linux)PC (Linux)PC (Linux)
Front-End PCs
Run startRun stopTrigger config
Main DAQ PC PC (Linux)
GigabitEthernet
On-line farm
PC (Linux)PC (Linux)PC (Linux)
storage
PC (Linux)
Event builder
PSI - Jun. 27th, 2006 4
HV
PSI - Jun. 27th, 2006 5
HV
Active down regulation of an external HV supply
PSI design• 10 chn per board• 180 chn per 3 HE crate• Back side connector• Total of 6 crates
Active down regulation of an external HV supply
PSI design• 10 chn per board• 180 chn per 3 HE crate• Back side connector• Total of 6 crates
4 different requirements:– Lxe: 1000V , 100 uA– TC bars: 2400V, 1 mA– TC curved: 500V, <1 uA– DC: 2400V, ~1 uA
Commercial HV supplies delivered
Mass production in progressInstallation in September
PSI - Jun. 27th, 2006 6
Splitters
PSI - Jun. 27th, 2006 7
Splitter layout
• ERNI high bandwidth output connector
• crosstalk with ERNI connector plus 2m cable is ~ 0.6%
DRS
Trigger
Trigger or DRS Input
Power
PSI - Jun. 27th, 2006 8
Backplane layout
• Test circuit was implemented on backplane• Debug completed • PCB production in progress, mounting in house
PSI - Jun. 27th, 2006 9
Crates
• Mechanic parts and fans delivered• Power supplies delivered and tested
Frontal panel
Back panel
Output (5V-36A)
PSI - Jun. 27th, 2006 10
Cables Inputs• Single coaxial cable (RG178 – 9m
long) bundled into a polyester braided sleeve
• Negligible crosstalk between cables.
DRS outputs• High bandwidth output (DRS)• high density twisted pairs cable (0.68
pitch) 2 m long with one flat zone in the middle (Amphenol SPECTRASTRIP 68p)
Trigger outputs– Low density twisted pairs cable (1.27
pitch) 2 m long with 2 flat zone (3M 34p/10p)
PSI - Jun. 27th, 2006 11
Splitter SummarySplitter
– first prototype finished in may successfully– PCB production started the first of June– PCB production time one month – Component procurement in progress – Board mounting 2 weeks end of July – Board test 1 week – Boards ready by the beginning of September
Backplane– Crates and power supply delivered– backplane production in Lecce
Cables– Trigger cables ready– LXe cables in production– DRS cables in production
Installation– Foreseen between September 5 and 20
PSI - Jun. 27th, 2006 12
TC
PSI - Jun. 27th, 2006 13
PMT ramp generator
RAMPGEN.
RAMPGEN.D/DD/D
S TC Analog Sign. Monitor
NIM Signal for any possible use
to Splitter
BB
BBAnalog signals to DRS and trigger
PassiveSplitter
PMT
Dual Threshold ORConstant Fraction ORLeading edge discriminator
to Splitters
Signals to DRS
6U Eurocards boards
8 boards
PSI - Jun. 27th, 2006 14
ProductionPMT ramp generator• Design of the final boards in progress• Mass production September (?)• system delivery 8 boards October (?)
APD pre amplifiers• First prototype with problems on IC and cross talk• Second prototype design and test completed • Mass production and test in progress• system delivery end of July
APD hit registers • board design completed• Production and test in progress• system delivery (6 boards – 6U VME) end of July
PSI - Jun. 27th, 2006 15
Trigger
PSI - Jun. 27th, 2006 16
TriggerBoards
Type1
Front end
Type2
Ancill
PSI - Jun. 27th, 2006 17
System test
4 Type12 Type22 Ancillary
•Synchronous operation
•No transmission errors
PSI - Jun. 27th, 2006 18
Splitter-Type1 connection
Alpha and cosmic muon events from the Pisa facility
PSI - Jun. 27th, 2006 19
Number of boards: summary table
row col tot faninn.
board Type1
Connections Type1-Type2
n. board Type2
Connections Type2-Type2
n. board Type2
inner 9 24 216 1 14 1
up 9 6 54 4 1 1
down 9 6 54 4 1 1
lateral 6 24 144 4
lateral 6 24 144 4
back 9 24 234 4 4 1
Total 846 25 3
TC u.s. 15 2 30 1 2 1
TC d.s. 15 2 30 1 2 1
TC curved 256 2 512 8 4 1
Total 572 8 1
DC wires 16 16 256 8 2 1
aux dev 16 1 16 1 1 1
36 4 10.35 0.55
49 8
1
PMT Number of trigger boards
5 11 2
2
TOTAL produced
TC1 1
1
LXe
TOTAL mounted
Spare fraction
PSI - Jun. 27th, 2006 20
Number of boards: status
Boards Type1• 48 funded• 36 needed• 40 delivered• 8 not completely
mounted• 40 tested
Boards Type2• 10 funded• 5 needed• 10 delivered• 10 tested
Boards Ancill• 8 funded• 4 needed• 4 delivered• 4 not completely
mounted• 2 tested
Front-End Boards • 800 funded• 576 needed• 800 delivered• 320 tested
Done !
Done !
PSI - Jun. 27th, 2006 21
Type1 : VIRTEX II- PRO (XC2VP20-7-FF1152) • Type1-0 LXe front face • Type1-1 LXe lateral faces • Type1-2 LXe top,bottom and back face • Type1-3 TC bars • Type1-4 TC fibers
• Type1-5 DC • Type1-6 Auxiliary devices • Type1-7 LXe back face x
Type2 : VIRTEX II- PRO (XC2VP40-7-FF1152) • Type2-0 Final Level completed • Type2-1 LXe front+up/down faces
• Type2-2 LXe lateral faces • Type2-3 TC
Firmware V1.0 Present Status
PSI - Jun. 27th, 2006 22
Board Type3
PSI - Jun. 27th, 2006 23
Board Type3
• Type3 board 32 channels• Number of boards for the LXe lateral sides(612 chn): 20• Boards design : ~ ready• PCB prototype : end of July • Component delivery: (12 weeks) ~ beginning of September• Test: September• Production: October• Installation: end of October
Modified Type1 boards to produce an auxiliary digitization of the LXe signals
PSI - Jun. 27th, 2006 24
Comments on triggerInstallation
- Ready: any time from beginning of Jul. to end of Aug.- Should follow the NaI moving system- Should precede the electronic integration Sep. - DAQ computers
Configuration- Baseline version V1.0 written- Needs tuning, at least 1 month during purification- Needs analysis tools, under development
Documentation - Hardware register list available- Almost available for Type1- In progress for Type2
PSI - Jun. 27th, 2006 25
DRS
PSI - Jun. 27th, 2006 26
DRS• DRS2 available for all channels• New PMC card finished
– Reduced noise 1.2 mV → 0.5 mV RMS– Self-calibration on card– Mass production started– cards expected in August
• PSI GPVME boards in production– Delivery end of August
PSI - Jun. 27th, 2006 27
DRS2 issues
Issue Solution DRS2 DRS3Voltage nonlinearity
Calibration with cubic splines in Front-end
Clock nonlinearity Time calibration & frequency regulation
Cross talk 1% @ 7ns risetime
Redesign of CMC card with ERNI 68-pin connector and interleaved ground lines
Temperature dependence
- Calibration maybe possible to some extend- Keep electronics temperature constant- On-chip temperature compensation
?()
Self-heating of cells - Only use small signals (<0.5 V)- On-chip temperature compensation
()
Ghost pulses - Veto trigger ~5us after cosmic or LED event- Veto trigger after other calorimeter hits?- Record 2us calorimeter history in each event?- Redesign sampling cell
??
All issues could be resolved as planned
PSI - Jun. 27th, 2006 28
DRS3
• DRS3 design finished • Prototypes expected in August• Tests foreseen at the end of the year
PSI - Jun. 27th, 2006 29
DRS3 layout
• Smaller “standard cells”
• Totally > 600,000 transistors
• Smaller package (QFP64)
• 12 channels/chip• ROI readout and
parallel readout to reduced dead time:230 s → 50 s → 5 s
• Smaller “standard cells”
• Totally > 600,000 transistors
• Smaller package (QFP64)
• 12 channels/chip• ROI readout and
parallel readout to reduced dead time:230 s → 50 s → 5 s
PSI - Jun. 27th, 2006 30
DRS and Trigger Crates
Power distribution boxPower distribution box Issue: “Splitter” rack cannot be accessed easily from back side!
Issue: “Splitter” rack cannot be accessed easily from back side!
20 cm
PSI - Jun. 27th, 2006 31
DAQ cluster
PSI - Jun. 27th, 2006 32
DAQ Cluster Layout
80 GB System DiskRAID 1 (Mirror)
/home/meg
1.2 TG Data DiskRAID 5
80 GB System DiskRAID 1 (Mirror)
80 GB System DiskRAID 1 (Mirror)
Back-End
Front-End #1
Front-End #2
. . .NFS
/home/meg |-- root <- ROOTSYS |-- midas <- MIDASSYS |-- mxml |-- rome <- ROMESYS `-- meg <- MEGSYS |-- meganalyzer |-- megbartender |-- megmc `-- online |-- drivers |-- eventbuilder |-- frontend |-- slowcontrol | |-- bts | |-- calorimeter | `-- scfe |-- trigger `-- VPC
/home/meg |-- root <- ROOTSYS |-- midas <- MIDASSYS |-- mxml |-- rome <- ROMESYS `-- meg <- MEGSYS |-- meganalyzer |-- megbartender |-- megmc `-- online |-- drivers |-- eventbuilder |-- frontend |-- slowcontrol | |-- bts | |-- calorimeter | `-- scfe |-- trigger `-- VPC
VME-Interface
VME-Interface
SC-FE
Data rate100 MB/s
PSI - Jun. 27th, 2006 33
Front-end computers
Back-end1.2 TB disk
Back-end1.2 TB disk
Front-end #1Front-end #1
GBit SwitchGBit Switch
• Two DAQ computer installed with DAQ software
• Remaining computers delivered
• Installation end of July
PSI - Jun. 27th, 2006 34
Offline Cluster
Sun Fire x4100 quad core 4 GB
Sun Fire x4100 quad core 4 GB
Sun Fire x4100 quad core 4 GB
Sun Fire x4100 quad core 4 GB
Sun Fire x4100 quad core 4 GB
Fib
er
Ch
an
nel Sw
itch
15 x 500 GB SATA
• Ordered on June 14th: 20 cores + 30 TB disk• Easily extensible• Redundancy through GFS/GPFS file systems• GBit link to online cluster requested
GB
it E
thern
et
PSI - Jun. 27th, 2006 35
Slow control
PSI - Jun. 27th, 2006 36
SCS-2000 • Replaces SCS-1001 unit
• 64 I/O lines (analog, digital, opto-coupler, PT100, etc.)
• Outputs stable during CPU firmware upgrade (→ BTS control)
• “Soft” fuse
• LED pulser (40 lines, computer controllable)
• Replaces SCS-1001 unit
• 64 I/O lines (analog, digital, opto-coupler, PT100, etc.)
• Outputs stable during CPU firmware upgrade (→ BTS control)
• “Soft” fuse
• LED pulser (40 lines, computer controllable)
PSI - Jun. 27th, 2006 37
BTS slowcontrol
• Slowcontrol back-end to MSCB slow control units
• Integrated in MIDAS history system
• Monitoring and control though MIDAS web pages
• More pages added as SC equipment gets operational
PSI - Jun. 27th, 2006 38
MIDAS history
PSI - Jun. 27th, 2006 39
Conclusions
• All the key elements of the electronic system are available for integration in September
• Some parts will arrive with ~1 month delay
PSI - Jun. 27th, 2006 40
Rack space