© 2018 Electric Power Research Institute, Inc. All rights reserved.

Deepak Ramasubramanian, EPRIdramasubramanian@epri.com

Evangelos Farantatos, EPRIAnish Gaikwad, EPRI

Wenzong Wang, Texas A&M University

WECC REMTFMay 10th 2018

Salt Lake City, UT

Proposal for improved

voltage source converter

model – an update

2© 2018 Electric Power Research Institute, Inc. All rights reserved.

This model is neither expected to nor can it accurately represent

the complete all encompassing behavior of a converter.

It is not expected that this model will replace existing second

generation generic models. It is however intended for use as a

screening model in an additional step before performing a

PSCAD type of simulation.

DISCLAIMERS

3© 2018 Electric Power Research Institute, Inc. All rights reserved.

Questions and comments from March 2018 WebEx

meeting

Is the inner current control loop required?

– Can only the PLL model be represented in detail and represent the inner

current control loop by single time constant.

Should the PLL interface be added to the current source

REGC_A model?

Are limits required in the PLL model for frequency calculation?

– Depending on the vendor, this may or may not be a feature in the model.

Addition of rate limits on the current commands.

– And LVPL? (may not be required if VDL blocks are present?)

A switch to allow bypass of PLL and inner current control loop.

4© 2018 Electric Power Research Institute, Inc. All rights reserved.

Draft block diagram

Note: The LVPL block is not represented

as REEC_A (with VDL blocks) was used

to generate current commands

∑ 𝐾𝐼𝑝 +𝐾𝐼𝑖𝑠

∑ 𝐾𝐼𝑝 +𝐾𝐼𝑖𝑠

𝐸𝑑=𝑉𝑡𝑑0+𝑖𝑝𝑟𝑒−𝑖𝑞 ′𝑥

𝑒

𝐸𝑞=𝑉𝑡𝑞0+𝑖𝑞𝑟𝑒+𝑖𝑝 ′𝑥

𝑒

1

1 + 𝑠𝑇𝑒

1

1 + 𝑠𝑇𝑒

𝑗 ∑Iterate

with

network

solution

to enforce

current

limit

෨𝐸

𝐼𝑞𝑐𝑚𝑑

𝐼𝑝𝑐𝑚𝑑

𝑑𝐼𝑝𝑚𝑎𝑥

𝑖𝑞

𝑖𝑝

𝑖𝑝′

𝑖𝑞′ 𝑟𝑒 𝑥𝑒

𝐾𝑃𝐿𝐿𝑝 +𝐾𝑃𝐿𝐿𝑖𝑠

1

𝑠𝜃

Δ𝜔

𝑉𝑡𝑟𝑒𝑎𝑙

𝑉𝑡𝑖𝑚𝑎𝑔

𝑉𝑡𝑑

𝑉𝑡𝑞

𝐼𝑟𝑒𝑎𝑙

𝐼𝑖𝑚𝑎𝑔

𝑖𝑝

𝑖𝑞

s4s5

1

1 + 𝑠𝑇𝑖

1

1 + 𝑠𝑇𝑖

𝑉𝑡

tan−1 𝑦𝑥

y x

s0

Y

s0

s1

s1

s2

s3+

-

-

+

+

+

N

N

N

N

N

Y

Y

Y

Y

𝑉𝑡

Y – Use PLL and PI Loop

N – Do not use

Δ𝜔𝑚𝑎𝑥

Δ𝜔𝑚𝑖𝑛

5© 2018 Electric Power Research Institute, Inc. All rights reserved.

Three versions of the model created

Version 1:

– Inner current control PI loop,

– Representation of the PLL,

– Voltage source interface,

– Iteration with network solution.

Version 2:

– Inner current control PI loop, Replaced by first order time constant

– Representation of the PLL,

– Voltage source interface,

– Iteration with network solution.

Version 3: Same as Version 1 but with inclusion of ramp rate limit

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Preliminary validation results – requirement for inner current control

loopVersion 1 – with PLL and inner current control loop

Version 2 – with PLL without inner current control loop

• PLL control gains:

• Kp = 20.0

• Ki = 2400.0

• Inner current control gains:

• Version 1:

• Kp = 5.0

• Ki = 70.0

• Version 2:

• T = 0.07s

• 7 cycle fault solid fault (X =

0.005pu) applied in both

cases

• Current commands provided

by REEC_A

• SCR ≈ 2.48

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PLL frequency limits?

6.81 cycle fault

6.80 cycle fault

5.52 cycle fault

5.46 cycle fault

• Open PLL limits in both positive sequence and 3 phase simulation

• Relative angle in positive sequence is against swing generator

• PLL Gain: Kp = 20.0; Ki = 2400.0

Positive sequence simulation 3 phase point on wave simulation

• ‘Pole-slip’ effect occurs in 3 phase simulation under certain circumstances

• Positive sequence angle always stabilizes at a larger value

8© 2018 Electric Power Research Institute, Inc. All rights reserved.

6.81 cycle fault

6.80 cycle fault

5.46 cycle fault

5.52 cycle fault

Limitation of the positive sequence model in that the angle would probably always settle at the higher value

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Version 3 of model – ramp rate limit

10000 pu/s

0.1 pu/s

• PLL Gain: Kp = 20.0; Ki = 2400.0

• Presently ramp rate only on Ipcmd

• PLL Limits: ± 12 Hz

10© 2018 Electric Power Research Institute, Inc. All rights reserved.

Can such a behavior be represented by the model?

Source: “Deploying Utility-Scale PV Power Plants in Weak Grids”, First Solar, 2017 PES General Meeting, Chicago, IL, July 2017

• Actual measurement data of a

bulk power system connected

PV plant presented by First

Solar.

• No large scale disturbance in the

immediate vicinity of the plant.

• Most probably a small

signal stability issue.

• Occurs only for certain levels of

active power output.

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System setup

Source at Bus 1 represented by classical machine with large MVA and H.

Source at Bus 20004 represented by REEC_A and:– Version 2 of REGC_B with KpPLL = 20.0; KiPLL = 1500.0; T = 0.07

– Version 3 of REGC_B with KpPLL = 20.0; KiPLL = 1500.0; KpICC = 5.0; KiICC = 70.0; Ramp rate = 100.0 pu/s

– Elliptical change in Pgen

Two values of X to represent different system strengths:– X = 0.01 pu

– X = 0.505 pu

R =

X =

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Low/high grid strength – X = 0.505/0.01 pu

Version 2

Version 3 ~5.35 Hz Oscillation

X = 0.01 pu

X = 0.505 pu

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Discussion

The positive sequence model with the added features is able

to replicate the trend observed in PSCAD simulations.

It is however not yet a one-to-one comparison both from a

performance and control gain point of view.

Blocking of PLL for low voltage, ramp rate on reactive

current, freezing of states have not been implemented in the

models.

Is this model worth pursuing?

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Together…Shaping the Future of Electricity