Prof. Lei HeElectrical Engineering Department

University of California, Los Angeles

URL: eda.ee.ucla.eduEmail: lhe@ee.ucla.edu

Chapter 2

Interconnect Analysis

Delay Modeling

2

Outline

Delay models

RC tree Elmore delay (First Order)

Second Order Analysis (S2P algorithm)

Gate delay

3

The circuit delay in VLSI circuits consists of two components:

The 50% propagation delay of the driving gates (known as the gate delay)

The delay of electrical signals through the wires (known as the interconnect delay)

A B C

Inv 1 Inv 2

BCABAC DelayDelayDelay

Input-to-Output Propagation Delay

4

Lumped vs Distributed Interconnect Model

Lumped Distributed

R

C

r

c

r

c

r

c

r

c

How to analyze the delay for each model?

5

Lumped RC Model

Rv(t)u(t)

C

Impulse response and step response of a lumped RC circuit

6

Analysis of Lumped RC Model

S-domain ckt equation (current equation)

match initial state:

Time domain responsefor step-input:

v0v0

v0(1-eRC/T))1()( 0RC

tevtv

R

C

)(tv)(tu

Time domain responsefor impulse:

sC

sv

R

svsu )()()(

)())()(( sRvsvsusC

)()( susCR

sCsv

Frequency domain response for step-input sCR

Csv

)(

Frequency domain response for impulse sCR

sCsv

)(

RCt

evtv

0)(

7

A B C

Inv 1 Inv 2

( ) 1

t

RCV t e

R

C

V(t)1v

How about more complex circuits?

50% Delay for lumped RC model

1

0.5

50% delayRCt

e RC

t

69.0

5.0

8

Distributed RC-Tree

The network has a single input node All capacitors between node and ground The network does not contain any resistive loop

R1

C1

s

R 2

C2

R 4

C4

C3

R3

Ci

Ri

1

2

3

4

i

9

RC-tree Property

Unique resistive path between the source node s and any other node i of the network path resistance Rii

Example: R44=R1+R3+R4

R1

C1

s

R 2

C2

R 4

C4

C3

R3

Ci

Ri

1

2

3

4

i

10

RC-tree Property

Extended to shared path resistance Rik:

Example: Ri4=R1+R3Ri2=R1

)])()([( s.t. kspathispathRRR jjik

R1

C1

s

R 2

C2

R 4

C4

C3

R3

Ci

Ri

1

2

3

4

i

11

Elmore Delay

Assuming:– Each node is initially discharged to ground

– A step input is applied at time t=0 at node s The Elmore delay at node i is:

Theorem: The Elmore delay is equivalent to the first-order time constant of the network

– Proven acceptable approximation of the real delay– Powerful mechanism for a quick estimate

N

kikkDi RC

1

69.0

0th(t)dt

12

Example

Elmore delay at node i is

))()( iii433i43211

ii314313312111

iii4i43i32i21i1Di

CRCCCCCCCC0.69(R

))CRR(R)CR(R)CR(RCRC0.69(R

)CRCRCRCRC0.69(Rτ

R

R1

C1

s

R 2

C2

R 4

C4

C3

R3

Ci

Ri

1

2

3

4

i

13

Interpretation of Elmore Delay

Definition h(t) = impulse response TD = mean of h(t)

=

Interpretation H(t) = output response (step process) h(t) = rate of change of H(t) T50%= median of h(t) Elmore delay approximates the median of

h(t) by the mean of h(t)

0

dtt h(t)

medianof h(t)(T50%)

h(t) of mean

th(t)dtT0D

h(t) = impulse response

H(t) = step response

14

Elmore Delay Approximation

15

RC-chain (or ladder)

Special case: Shared-path resistance path resistance

N

kkkkDN RC

1

R1

C1

R2

C2

RN

CN

Vin VN

16

RC-Chain Delay

22

1

2

)1( 22

11

rcL

N

NrcL

NNRCCkRRC

N

N

k

N

kkkkDN

R

C

R

C

R

C

Vin VN

R=r · L/N

C=c·L/N

– Delay of wire is quadratic function of its length– Delay of distributed rc-line is half of lumped RC

17

Outline

Delay models

RC tree Elmore delay (First Order)

Second Order Analysis (S2P algorithm)

Gate delay

18

The Elmore delay is the metric of choice for performance-driven design applications due to its simple, explicit form and ease with which sensitivity information can be calculated

However, for deep submicron technologies (DSM), the accuracy of the Elmore delay is insufficient

Stable 2-Pole RC delay calculation (S2P)

19

Moments of H(s)

Moments of H(s) are coefficients of the Taylor’s Expansion of H(s) about s=0

0

1( ) ( )! s

jdjm H sjj ds

0 0 0

2 31 12 3( ) ( ) ( ) ( ) ...0 2 32! 3!s s s

d d dH s H s H s s H s s H s

ds ds ds

(0) (1) 2 (2) 3 (3) ...m sm s m s m

20

Let Y(s) be an driving point admittance function of a general RC circuit. Consider its representation in terms poles and residues

where q is the exact order of the circuit

Moments of Y(s) can be written as:

( ) 0

1

qknY s k

s pnn

01

1

qknm ii ipnn

Driving Point Admittance

21

Compute m1, m2, m3 and m4 for Y(s)

Find the two poles at the driving point admittance as follows:

To match the voltage moments at the response nodes, choose

and the S2P approximation is then expressed as:

Note that m0* and m1*

are the moments of H(s). m0* is the Elmore delay.

S2P Algorithm

22

S2P Vs. Elmore Delay

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

0.4

0.5

0.6

0.7

0.8

0.9

1

t

Vol

tage

SPICE

Elmore

S2P

23

Outline

Delay models

RC tree Elmore delay (First Order)

Second Order Analysis (S2P algorithm)

Gate delay

24

The gate delay and the output transition time are functions of both input slew and the output load

Gate/Cell

T in

Cload

( , )in loadGate Delay f T C

( , )in loadOutput Transition Time f T C

Gate Delay and Output Transition Time

25

General Model of a Gate

26

in

Wp

Wn

CM

out

in

Wp

Wn

CM

out

Cdiff Cload

Vin Vout

Cout

Definitions

VinVout

Time

Gate Delay

90%

10%

Output Transition Time

27

Output Response for Different Loads

28

Output transition time as a function of input transition time and output load

Output Transition Time

2 2.4 2.8 3.2 3.6 4

x 10-10

5

6

7

8

9

10

11 x 10-11

Size=69 Cout=23fFSize=48 Cout=15fFSize=90 Cout=18fF

Input Transition Time (s)

Ou

tpu

t T

ran

siti

on t

ime

(s)

10-10

1 1.4 1.8 2.2 2.6 3

x 10-14

6

7

8

9

10

11 x 10-11

Size=60 Tin=300pSSize=81 Tin=350pSSize=45 Tin=200pS

Ou

tpu

t T

ran

siti

on t

ime

(s)

CLoad (F)10-14

29

Three approaches for gate propagation delay computation are based on:– Delay look-up tables– K-factor approximation – Effective capacitance

Delay look-up table is currently in wide use especially in the ASIC design flow

Effective capacitance promises to be more accurate when the load is not purely capacitive

ASIC Cell Delay Model

30

What is the delay when Cload is 505f F and Tin is 90pS?

Cload (fF)

Tin

(pS)

0 5 10 500 505 51050

70

90

110

310

330

115pS

Table Look-Up Method

31

We can fit the output transition time v.s. input

transition time and output load as a polynomial function, e.g.

A similar equation gives the gate delay

2( )1 2 3 4 5T k k C T k k C k Coutput load in load load

K-factor Approximation

2 2.4 2.8 3.2 3.6 4

x 10-10

5

6

7

8

9

10

11 x 10-11

Size=69 Cout=23fFSize=48 Cout=15fFSize=90 Cout=18fF

Input Transition Time (s)

Ou

tpu

t T

ran

siti

on t

ime

(s)

10-10

1 1.4 1.8 2.2 2.6 3

x 10-14

6

7

8

9

10

11 x 10-11

Size=60 Tin=300pSSize=81 Tin=350pSSize=45 Tin=200pS

Out

put

Tra

nsit

ion

tim

e (s

)

CLoad (F)10-14

32

One Dimensional Table

( 1) 1

( )2 2

( ) 1 2

2 11

2 1

1 2 2 122 1

2 1 1 2 2 1( )2 1 2 1

t C tr r

t C tr r

t C a C ar

t tr raC C

t C t Cr raC C

t t t C t Cr r r rt C Cr L LC C C C

Linear model

33

Two Dimensional Table

( , ) 1 2 3 4

( ) /1 4 11 3 2 1 2 1 2 1 2 2( ) /2 3 1 4 1 1 2 2 2

3 ( ) /2 1 4 1 1 2 3 24 ( ) /1 2 3 4

( )( )1 2 1 2

D C t k k C k t k C tin L in L in

D C t D C t D C t D C t WkD t D t D t D t Wk

k D C D C D C D C Wk D D D D W

W C C t t

D1

D4D3

D2

Quadratic model

34

Gate /Cell

T in

2 31 2 3( ) .....inY s A s A s A s 2 2 2 3 3

1 2 2 2( ) ( ) .....inY s C C s R C s R C s

22 232 2

1 1 233 32

AA AC A R C

A AA

Gate /Cell

Tin R

C1

C2

Using Taylor Expansion around s = 0

Second-order RC- Model

35

Gate /Cell

Tin R

C1

C2

1 2( , , , )inGate Delay f T C R C

This equation requires creation of a four-dimensional table to achieve high accuracy

This is however costly in terms of memory space and computational requirements

Second-order RC- Model (Cont’d)

36

The “Effective Capacitance” approach attempts to find a single capacitance value that can be replaced instead of the RC- load such that both circuits behave similarly during transition

Gate /Cell

Tin R

C1

C2

Gate /Cell

T in

Ceff

Effective Capacitance Approach

37

Output Response for Effective Capacitance

38

Effective Capacitance (Cont’d)

39

0<k<1

Gate /Cell

Tin R

C1

C2

21 kCCCeff

Because of the shielding effect of the interconnect resistance , the driver will only “see” a portion of the far-end capacitance C2

R

k = 1

R

∞k = 0

Gate /Cell

T in

Ceff

Effective Capacitance (Cont’d)

40

Effective Capacitance for Different Resistive Shielding

41

Assumption: If two circuits have the same loads and output transition times, then their effective capacitances are the same

=> the effective capacitance is only a function of the output transition time and the load

GATE 2

Tin2 R

C1

C2

GATE 1

Tin1 R

C1

C2

Macy’s Approach

42

1. Compute from C1 and C2

2. Choose an initial value for Ceff

3. Compute Tout for the given Ceff and Tin

4. Compute 5. Compute from and 6. Find new Ceff

7. Go to step 3 until Ceff converges

GATE 1

Tin1 R

C1

C2

21

1

CC

C

2CR

Tout

21 CC

Ceff

Macy’s Iterative Solution

43

Summary

43

Delay model– Elmore delay– Gate delay: look-up table, k-factor approximation, effective capacitance

44

References

44

R. Macys and S. McCormick, “A New Algorithm for Computing the “Effective

Capacitance” in Deep Sub-micron Circuits”, Custom Integrated Circuits Conference

1998, pp. 313-316

J. Qian, S. Pullela, and L. T. Pileggi, "Modeling the "effective capacitance" for the RC

interconnect of CMOS gates," IEEE Trans. on Computer-Aided Design of Integrated

Circuits and Systems, vol. 13, pp. 1526-1535, Dec. 1994.

Jason Cong , Lei He , Cheng-Kok Koh , Patrick H. Madden, Performance optimization of

VLSI interconnect layout, Integration, the VLSI Journal, v.21 n.1-2, p.1-94, Nov. 1996

(Section 2.1-2.2)

W. C. Elmore, “The Transient Response of Damped Linear Networks with Particular

Regard to Wideband Amplifiers”, Journal of Applied Physics, 1948.

Jorge Rubinstein, and etc. “Signal Delay in RC Tree Networks”, TCAD'83

Emrah Acar, Altan Odabasioglu, Mustafa Celik, and Lawrence T. Pileggi. 1999. “S2P: A

Stable 2-Pole RC Delay and Coupling Noise Metric”. In Proceedings of the Ninth Great

Lakes Symposium on VLSI(GLS '99).