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PCN IPD-PWR/13/7845Dated 09 May 2013
Front-End Capacity Extension for Power Bipolar
Transistors (Planar Technology) - Tours (France)
1/24
PRODUCT/PROCESSCHANGE NOTIFICATION®
PCN IPD-PWR/13/7845 - Dated 09 May 2013
Table 1. Change Implementation ScheduleForecasted implementation date for 02-May-2013 change
Forecasted availability date of samples 02-May-2013 for customer
Forecasted date for STMicroelectronicschange Qualification Plan results availability 02-May-2013
Estimated date of changed product first 08-Aug-2013 shipment
Table 2. Change IdentificationProduct Identification see attached list (Product Family/Commercial Product)
Type of change Waferfab additional location
Reason for change optimize Power Bipolar Transistors productivity and Wafer FAButilization
Description of the change Following the continuous improvement of our service and in order torationalize and optimize Power Bipolar Transistors productivity, thisdocument is announcing that Power Bipolar Transistors (PlanarTechnology), currently manufactured in Ang Mo Kio (Singapore) WaferFAB, will be produced again in the Tours (France) plant as in thepast. Power Bipolar Transistors (Planar Technology) produced inTours (France), guarantees the same quality and electricalcharacteristics as reported in the relevant data sheet. Devices usedfor qualification are available as Samples
Change Product Identification "VU" as Wafer FAB production area code
Manufacturing Location(s)
® 2/24
PCN IPD-PWR/13/7845 - Dated 09 May 2013
DOCUMENT APPROVAL
Name Function
Mottese, Anna Marketing Manager
Aleo, Mario-Antonio Product Manager
Falcone, Giuseppe Q.A. Manager
® 4/24
1
Dear Customer,
Please be informed that Power Bipolar Transistors (Planar Technology), currently manufactured in Ang
Mo Kio (Singapore) Wafer FAB, will be also produced in Tours (France) plant.
The involved product series and affected Technologies are listed in the table below:
Product Family Technology Commercial
Product / Series
Power Bipolar Transistors Planar See attached list
Any other product related to the above table, even if not expressly included or partially mentioned in the
attached list, is affected by this change.
Qualification program and results availability:
The reliability test report is provided in attachment to this document.
Samples availability:
Samples of the test vehicle devices will be available on request starting from week 18-2013.
Any other sample request will be processed and scheduled by Power Transistor Division upon request.
Product Family Package Part Number - Test Vehicle
Power Bipolar Transistors
I²PAK
DPAK
SOT-32
TO-92
BULB128-1
STD13003T4
ST13003
STL73
Pilot Run Samples available upon request, starting from Week 23-2013:
BUL128, BUL128D-B, BUL38D, BUL49D, BULB49DT4, BULD118D-1, ST13003-K, ST13003-S, ST13005, STBV32, STBV32-AP, STBV32E-AP, STI13005-H, STK13003M, STL128D, STL128DFP, STL128DN, STL128DNFP, STLD128DNT4, STT13005D-K, STX13003, STX13003-AP, STX13003G, STX13003G-AP, STX13003M, TR236, T RD136DT4.
Change implementation schedule:
The first shipments will be implemented according to our work in progress and materials availability:
Product Family 1st Shipments
Power Bipolar Transistors From Week 31-2013
Marking and traceability:
Unless otherwise stated by customer specific requirement, traceability of Power Bipolar Transistors (Planar
Technology), manufactured in Tours (France) plant, will be ensured by “VU" as Wafer FAB production ar-
ea code printed on the box label.
Sincerely Yours.
1
TOURS vs. AMK
1. Parametric Verification on:
BVCEO;
hfe;
VCEsat;
2. CPKs data.
LEGEND:
- Tours distribution on the left,
- AMK distribution on the right.
Contents
2
PARAMETRIC VERIFICATION BVceo @ 10mA
TOURS vs. AMK
ST13003 / STD13003
BVceo @ 10mA AMK
T_2_T10_BV %5= 437.40 avg= 462.65 95%= 480.30 Std= 13.39
530.00
525.00
520.00
515.00
510.00
505.00
500.00
495.00
490.00
485.00
480.00
475.00
470.00
465.00
460.00
455.00
450.00
445.00
440.00
435.00
430.00
425.00
420.00
415.00
410.00
405.00
400.00
395.00
390.00
385.00
380.00
[Percentage]
6.00
5.00
4.00
3.00
2.00
1.00
0.00
ST13003 / STD13003
BVceo @ 10mA TOURS
T_32_BVCEO %5= 454.80 avg= 468.59 95%= 477.60 Std= 7.11
510.00
508.00
506.00
504.00
502.00
500.00
498.00
496.00
494.00
492.00
490.00
488.00
486.00
484.00
482.00
480.00
478.00
476.00
474.00
472.00
470.00
468.00
466.00
464.00
462.00
460.00
458.00
456.00
454.00
452.00
450.00
448.00
446.00
444.00
442.00
440.00
438.00
436.00
434.00
432.00
430.00
428.00
426.00
[Percentage]
7.00
6.50
6.00
5.50
5.00
4.50
4.00
3.50
3.00
2.50
2.00
1.50
1.00
0.50
0.00
3
PARAMETRIC VERIFICATION hfe @ 2V 500mA
TOURS vs. AMK
ST13003 / STD13003
hfe @ 2V 500mA AMK
T_12_T20_H %5= 15.03 avg= 15.74 95%= 16.67 Std= 497.54m
19.00
18.90
18.80
18.70
18.60
18.50
18.40
18.30
18.20
18.10
18.00
17.90
17.80
17.70
17.60
17.50
17.40
17.30
17.20
17.10
17.00
16.90
16.80
16.70
16.60
16.50
16.40
16.30
16.20
16.10
16.00
15.90
15.80
15.70
15.60
15.50
15.40
15.30
15.20
15.10
15.00
14.90
14.80
14.70
14.60
14.50
14.40
14.30
14.20
14.10
14.00
13.90
13.80
13.70
13.60
13.50
13.40
13.30
13.20
13.10
13.00
[Percentage]
5.50
5.00
4.50
4.00
3.50
3.00
2.50
2.00
1.50
1.00
0.50
0.00
ST13003 / STD13003
hfe @ 2V 0.5A TOURS
T_10_HFE_1 %5= 13.29 avg= 13.77 95%= 14.47 Std= 357.04m
16.00
15.90
15.80
15.70
15.60
15.50
15.40
15.30
15.20
15.10
15.00
14.90
14.80
14.70
14.60
14.50
14.40
14.30
14.20
14.10
14.00
13.90
13.80
13.70
13.60
13.50
13.40
13.30
13.20
13.10
13.00
12.90
12.80
12.70
12.60
12.50
12.40
12.30
12.20
12.10
12.00
[Percentage]
7.00
6.50
6.00
5.50
5.00
4.50
4.00
3.50
3.00
2.50
2.00
1.50
1.00
0.50
0.00
4
PARAMETRIC VERIFICATION VCEsat @ 500mA 100mA
TOURS vs. AMK
ST13003 / STD13003
VCEsat @ 500mA 100mA AMK
T_18_T26_V %5= 186.80m avg= 217.27m 95%= 241.10m Std= 16.63m
310.00m
300.00m
290.00m
280.00m
270.00m
260.00m
250.00m
240.00m
230.00m
220.00m
210.00m
200.00m
190.00m
180.00m
170.00m
160.00m
150.00m
140.00m
130.00m
120.00m
[Percentage]
5.50
5.00
4.50
4.00
3.50
3.00
2.50
2.00
1.50
1.00
0.50
0.00
ST13003 / STD13003
VCEsat @ 0.5A 0.1A TOURS
T_15_VCESA %5= 149.40m avg= 156.73m 95%= 165.30m Std= 4.92m
180.00m
179.00m
178.00m
177.00m
176.00m
175.00m
174.00m
173.00m
172.00m
171.00m
170.00m
169.00m
168.00m
167.00m
166.00m
165.00m
164.00m
163.00m
162.00m
161.00m
160.00m
159.00m
158.00m
157.00m
156.00m
155.00m
154.00m
153.00m
152.00m
151.00m
150.00m
149.00m
148.00m
147.00m
146.00m
145.00m
144.00m
143.00m
142.00m
141.00m
140.00m
139.00m
138.00m
137.00m
136.00m
135.00m
[Percentage]
5.00
4.50
4.00
3.50
3.00
2.50
2.00
1.50
1.00
0.50
0.00
5
Limits (min & max) and CPK
TOURS vs. AMK
Limits ( min & max ) and CPK
Commercial Product: ST13003 / STD13003
Wafer Fab site: Tours Wafer Fab site: AMK
Test name Bvceo @ 10mA
min: 400V min: 400V
max: max:
CPK 3.21 CPK 1.55
Test name hfe @ 2V 0.5A
min: 8 min: 8
max: 20 max: 20
CPK 5.38 CPK 5.18
Test name VCEsat @ 0.5A 0.1A
min: min:
max: 0.5V max: 0.5V
CPK 10.61 CPK 4.35
6
PARAMETRIC VERIFICATION BVceo @ 10mA
TOURS vs. AMK
ST13005
BVceo @ 10mA AMK
T_5_T11_BV %5= 457.80 avg= 482.55 95%= 507.00 Std= 14.97
570.00
565.00
560.00
555.00
550.00
545.00
540.00
535.00
530.00
525.00
520.00
515.00
510.00
505.00
500.00
495.00
490.00
485.00
480.00
475.00
470.00
465.00
460.00
455.00
450.00
445.00
440.00
435.00
430.00
425.00
420.00
415.00
410.00
405.00
400.00
395.00
390.00
[Percentage]
5.50
5.00
4.50
4.00
3.50
3.00
2.50
2.00
1.50
1.00
0.50
0.00
ST13005
BVceo @ 10mA TOURS
T_3_BVCEO %5= 466.50 avg= 487.19 95%= 504.00 Std= 11.63
540.00
538.00
536.00
534.00
532.00
530.00
528.00
526.00
524.00
522.00
520.00
518.00
516.00
514.00
512.00
510.00
508.00
506.00
504.00
502.00
500.00
498.00
496.00
494.00
492.00
490.00
488.00
486.00
484.00
482.00
480.00
478.00
476.00
474.00
472.00
470.00
468.00
466.00
464.00
462.00
460.00
458.00
456.00
454.00
452.00
450.00
448.00
446.00
444.00
442.00
440.00
438.00
436.00
434.00
432.00
430.00
428.00
426.00
424.00
422.00
420.00
[Percentage]
5.50
5.00
4.50
4.00
3.50
3.00
2.50
2.00
1.50
1.00
0.50
0.00
7
PARAMETRIC VERIFICATION hfe @ 5V 1A
TOURS vs. AMK
ST13005
hfe @ 5V 1A AMK
T_11_T18_H %5= 23.20 avg= 23.92 95%= 24.70 Std= 466.62m
27.00
26.90
26.80
26.70
26.60
26.50
26.40
26.30
26.20
26.10
26.00
25.90
25.80
25.70
25.60
25.50
25.40
25.30
25.20
25.10
25.00
24.90
24.80
24.70
24.60
24.50
24.40
24.30
24.20
24.10
24.00
23.90
23.80
23.70
23.60
23.50
23.40
23.30
23.20
23.10
23.00
22.90
22.80
22.70
22.60
22.50
22.40
22.30
22.20
22.10
22.00
21.90
21.80
21.70
21.60
21.50
21.40
21.30
21.20
21.10
21.00
[Percentage]
5.00
4.80
4.60
4.40
4.20
4.00
3.80
3.60
3.40
3.20
3.00
2.80
2.60
2.40
2.20
2.00
1.80
1.60
1.40
1.20
1.00
0.80
0.60
0.40
0.20
0.00
ST13005
hfe @ 5V 1A TOURS
T_10_HFE_5 %5= 23.55 avg= 24.31 95%= 25.43 Std= 568.00m
28.00
27.80
27.60
27.40
27.20
27.00
26.80
26.60
26.40
26.20
26.00
25.80
25.60
25.40
25.20
25.00
24.80
24.60
24.40
24.20
24.00
23.80
23.60
23.40
23.20
23.00
22.80
22.60
22.40
22.20
22.00
21.80
21.60
21.40
21.20
21.00
[Percentage]
5.00
4.50
4.00
3.50
3.00
2.50
2.00
1.50
1.00
0.50
0.00
8
PARAMETRIC VERIFICATION VCEsat @ 1A 200mA
TOURS vs. AMK
ST13005
VCEsat @ 1A 200mA AMK
T_19_T26_V %5= 99.10m avg= 114.70m 95%= 132.40m Std= 11.20m
170.00m
168.00m
166.00m
164.00m
162.00m
160.00m
158.00m
156.00m
154.00m
152.00m
150.00m
148.00m
146.00m
144.00m
142.00m
140.00m
138.00m
136.00m
134.00m
132.00m
130.00m
128.00m
126.00m
124.00m
122.00m
120.00m
118.00m
116.00m
114.00m
112.00m
110.00m
108.00m
106.00m
104.00m
102.00m
100.00m
98.00m
96.00m
94.00m
92.00m
90.00m
88.00m
86.00m
84.00m
82.00m
80.00m
78.00m
76.00m
74.00m
72.00m
70.00m
[Percentage]
6.50
6.00
5.50
5.00
4.50
4.00
3.50
3.00
2.50
2.00
1.50
1.00
0.50
0.00
ST13005
VCEsat @ 1A 200mA TOURS
T_18_VCESA %5= 96.90m avg= 103.81m 95%= 116.90m Std= 6.03m
140.00m
138.00m
136.00m
134.00m
132.00m
130.00m
128.00m
126.00m
124.00m
122.00m
120.00m
118.00m
116.00m
114.00m
112.00m
110.00m
108.00m
106.00m
104.00m
102.00m
100.00m
98.00m
96.00m
94.00m
92.00m
90.00m
88.00m
86.00m
84.00m
82.00m
80.00m
78.00m
76.00m
74.00m
72.00m
70.00m
68.00m
[Percentage]
8.00
7.50
7.00
6.50
6.00
5.50
5.00
4.50
4.00
3.50
3.00
2.50
2.00
1.50
1.00
0.50
0.00
9
Limits (min & max) and CPK
TOURS vs. AMK
Limits ( min & max ) and CPK
Commercial Product: ST13005
Wafer Fab site: Tours Wafer Fab site: AMK
Test name Bvceo @ 10mA
min: 400V min: 400V
max: max:
CPK 2.49 CPK 1.83
Test name hfe @ 5V 1A
min: 15 min: 15
max: 31 max: 31
CPK 4.51 CPK 4.75
Test name VCEsat @ 5A 1A
min: min:
max: 0.9V max: 0.9V
CPK 5.73 CPK 3.41
IMS (Industrial & Multisegment Sector) IPD (Industrial, Power and Discretes) Group
Quality and Reliability Rel 04-13
Page 1/9
Reliability Report Front-End Capacity Extension for Power Bipolar Transistors (Planar Technology) - Tours (France)
General Information Product Lines:
BV73, BV77
Product Families: Power Bipolar Transistor
P/Ns: BULB128-1 (BV73) STD13003T4 (BV77) ST13003 (BV77) STL73 (BV77)
Product Group: IMS - IPD
Product division: Power Transistor Division
Package: I2PAK, DPAK, SOT-32,TO-92
Silicon Process tech.: High Voltage Planar Power Transistor
Locations Wafer Diffusion Plants:
Tours (France)
EWS Plants:
Tours (France)
Assembly plant: (BV73): I2PAK SHENZHEN (BV77): DPAK LONG-GANG SOT-32 CHANGJIANG TO-92 ASE WEI-HAI
Reliability Lab: IMS-IPD Catania Reliability Lab.
DOCUMENT INFORMATION
Version Date Pages Prepared by Approved by Comment 1.0 April 2013 9 C. Cappello G.Falcone First issue
Note: This report is a summary of the reliability trials performed in good faith by STMicroelectronics in order to evaluate the potential reliability risks during the product life using a set of defined test methods. This report does not imply for STMicroelectronics expressly or implicitly any contractual obligations other than as set forth in STMicroelectronics general terms and conditions of Sale. This report and its contents shall not be disclosed to a third party without previous written agreement from STMicroelectronics.
IMS (Industrial & Multisegment Sector) IPD (Industrial, Power and Discretes) Group
Quality and Reliability Rel 04-13
Page 2/9
TABLE OF CONTENTS 1 APPLICABLE AND REFERENCE DOCUMENTS ............................................................................................ 3
2 GLOSSARY ........................................................................................................................................................ 3
3 RELIABILITY EVALUATION OVERVIEW ......................................................................................................... 3
3.1 OBJECTIVES ............................................................................................................................................... 3
3.2 CONCLUSION .............................................................................................................................................. 3
4 DEVICE CHARACTERISTICS ........................................................................................................................... 4
4.1 DEVICE DESCRIPTION .................................................................................................................................. 4
4.2 CONSTRUCTION NOTE ................................................................................................................................. 4
5 TESTS RESULTS SUMMARY ........................................................................................................................... 8
5.1 TEST VEHICLE ............................................................................................................................................. 8
5.2 RELIABILITY TEST PLAN SUMMARY ................................................................................................................ 8
6 ANNEXES 6.0..................................................................................................................................................... 9
6.1TESTS DESCRIPTION ........................................................................................................................................ 9
IMS (Industrial & Multisegment Sector) IPD (Industrial, Power and Discretes) Group
Quality and Reliability Rel 04-13
Page 3/9
1 APPLICABLE AND REFERENCE DOCUMENTS
Document reference Short description JESD47 Stress-Test-Driven Qualification of Integrated Circuits
2 GLOSSARY DUT Device Under Test SS Sample Size HF Halogen Free
3 RELIABILITY EVALUATION OVERVIEW
3.1 Objectives Qualification of Power Bipolar Transistors (Planar Technology) manufactured in the Tours (France) plant.
3.2 Conclusion Qualification Plan requirements have been fulfilled without exception. It is stressed that reliability tests have shown that the devices behave correctly against environmental tests (no failure). Moreover, the stability of electrical parameters during the accelerated tests demonstrates the ruggedness of the products and safe operation, which is consequently expected during their lifetime.
IMS (Industrial & Multisegment Sector) IPD (Industrial, Power and Discretes) Group
Quality and Reliability Rel 04-13
Page 4/9
4 DEVICE CHARACTERISTICS
4.1 Device description High Voltage Planar Power Transistor
4.2 Construction note
D.U.T.: BULB128-1 LINE: BV73 PACKAGE: I2PAK
Wafer/Die fab. information Wafer fab manufacturing location Tours (France) Technology High Voltage Planar Power Transistor Die finishing back side Ti/Ni/Au Die size 2310 x 2340 µm2 Metal Al/Si Passivation type P-Vapox (PSG)
Wafer Testing (EWS) information
Electrical testing manufacturing location Tours (France) Test program WPIS
Assembly information
Assembly site ST-Shenzhen (China) Package description I2PAK
Molding compound Epoxy Resin Frame material Full Nichel
Die attach process Soft Solder Die attach material Pb/Ag/Sn
Wire bonding process Ultrasonic Wires bonding materials Al/Mg 5 mils Base
Al/Mg 5 mils Emitter Lead finishing/bump solder material Pure Tin
Final testing information
Testing location ST-Shenzhen (China) Tester IP-TESTER
IMS (Industrial & Multisegment Sector) IPD (Industrial, Power and Discretes) Group
Quality and Reliability Rel 04-13
Page 5/9
D.U.T.: STD13003T4 LINE: BV77 PACKAGE: DPAK
Wafer/Die fab. information Wafer fab manufacturing location Tours (France) Technology High Voltage Planar Power Transistor Die finishing back side Ti/Ni/Au Die size 1320 x 1390 µm2 Metal Al/Si Passivation type Nitride
Wafer Testing (EWS) information
Electrical testing manufacturing location Tours (France) Test program WPIS
Assembly information
Assembly site ST-LongGang (China) Package description DPAK
Molding compound Resin Frame material Full Nichel
Die attach process Soft Solder Die attach material Pb/Ag/Sn
Wire bonding process Termosonic Wires bonding materials Cu 2 mils Base
Cu 2 mils Emitter Lead finishing/bump solder material Pure Tin
Final testing information
Testing location ST-LongGang (China) Tester IP-TESTER
IMS (Industrial & Multisegment Sector) IPD (Industrial, Power and Discretes) Group
Quality and Reliability Rel 04-13
Page 6/9
D.U.T.: ST13003 LINE: BV77 PACKAGE: SOT-32
Wafer/Die fab. information Wafer fab manufacturing location Tours (France) Technology High Voltage Planar Power Transistor Die finishing back side Ti/Ni/Au Die size 1320 x 1390 µm2 Metal Al/Si Passivation type Yellow Nitride
Wafer Testing (EWS) information
Electrical testing manufacturing location Tours (France) Test program WPIS
Assembly information
Assembly site Changjiang (China) Package description SOT-32
Molding compound Epoxy Resin Frame material Full Nichel
Die attach process Soft Solder Die attach material Pb/Ag/Sn
Wire bonding process Termosonic Wires bonding materials Cu 1.7 mils Base
Cu 1.7 mils Emitter Lead finishing/bump solder material Pure Tin
Final testing information
Testing location Changjiang (China) Tester TESEC
IMS (Industrial & Multisegment Sector) IPD (Industrial, Power and Discretes) Group
Quality and Reliability Rel 04-13
Page 7/9
D.U.T.: STL73 LINE: BV77 PACKAGE: TO-92
Wafer/Die fab. information Wafer fab manufacturing location Tours (France) Technology High Voltage Planar Power Transistor Die finishing back side Ti/Ni/Au Die size 1320 x 1390 µm2 Metal Al/Si Passivation type Nitride
Wafer Testing (EWS) information
Electrical testing manufacturing location Tours (France) Test program WPIS
Assembly information
Assembly site Ase Wei-Hai (China) Package description TO-92
Molding compound Epoxy Resin Frame material Full Nichel
Die attach process Soft Solder Die attach material Pb/Ag/Sn
Wire bonding process Termosonic Wires bonding materials Cu 1.5 mils Base
Cu 1.5 mils Emitter Lead finishing/bump solder material Pure Tin
Final testing information
Testing location Ase Wei-Hai (China) Tester TESEC
IMS (Industrial & Multisegment Sector) IPD (Industrial, Power and Discretes) Group
Quality and Reliability Rel 04-13
Page 8/9
5 TESTS RESULTS SUMMARY
5.1 Test vehicle
Lot # P/N - Package Product Line Comments
1 BULB128-1 - I2PAK BV73
High Voltage Planar Power Transistor 2 STD13003T4 - DPAK BV77 3 ST13003 - SOT-32 BV77 4 STL73 - TO-92 BV77
5.2 Reliability test plan summary
Test PC Std ref. Conditions SS Steps Failure/SS
Note LOT 1 LOT 2 LOT 3 LOT 4
Die Oriented Tests
HTRB N JESD22 A-108
TA = 150°C, BIAS=560V
77 x 4 lots
168 H 0/77 0/77 0/77 0/77 500 H 0/77 0/77 0/77 0/77
1000 H 0/77 0/77 0/77 0/77
HTSL N JESD22 A-103
TA = 150°C 77 x 4
lots
168 H 0/77 0/77 0/77 0/77
500 H 0/77 0/77 0/77 0/77
1000 H 0/77 0/77 0/77 0/77
Package Oriented Tests
PC JESD22 A-113
Drying 24 H @ 125°C
Store 168 H @ TA=85°C Rh=85%
Over Reflow @ Tpeak=260°C/245°C
3 times
200 x 1 lot FINAL PASS
AC Y JESD22 A-102
Pa=2Atm / TA=121°C
50 x 2 lots
96 H 0/50 0/50
TC Y JESD22 A-104
TA = -65°C to 150°C 50 x 2
lots
100 cy 0/50 0/50
200 cy 0/50 0/50
500 cy 0/50 0/50
TF/IOL Y
Mil-Std 750D
Method 1037
∆TC=105°C 50 x 2
lots
5Kcy 0/50 0/50
10Kcy 0/50 0/50
H3TRB Y JESD22 A-101
TA=85°C , RH=85% ,
BIAS= 100V
50 x 2 lots
168 H 0/50 0/50
500 H 0/50 0/50
1000 H 0/50 0/50
IMS (Industrial & Multisegment Sector) IPD (Industrial, Power and Discretes) Group
Quality and Reliability Rel 04-13
Page 9/9
6 ANNEXES 6.0
6.1Tests Description
Test name Description Purpose Die Oriented
HTRB High Temperature
Reverse Bias
The device is stressed in static configuration, trying to satisfy as much as possible the following conditions: low power dissipation; max. supply voltage compatible with diffusion process and internal circuitry limitations;
To determine the effects of bias conditions and temperature on solid state devices over time. It simulates the devices’ operating condition in an accelerated way. To maximize the electrical field across either reverse-biased junctions or dielectric layers, in order to investigate the failure modes linked to mobile contamination, oxide ageing, layout sensitivity to surface effects.
HTSL High Temperature
Storage Life
The device is stored in unbiased condition at the max. temperature allowed by the package materials, sometimes higher than the max. operative temperature.
To investigate the failure mechanisms activated by high temperature, typically wire-bonds solder joint ageing, data retention faults, metal stress-voiding.
Package Oriented
AC Auto Clave
The device is stored in saturated steam, at fixed and controlled conditions of pressure and temperature.
To investigate corrosion phenomena affecting die or package materials, related to chemical contamination and package hermeticity.
TC Temperature
Cycling
The device is submitted to cycled temperature excursions, between a hot and a cold chamber in air atmosphere.
To investigate failure modes related to the thermo-mechanical stress induced by the different thermal expansion of the materials interacting in the die-package system. Typical failure modes are linked to metal displacement, dielectric cracking, molding compound delamination, wire-bonds failure, die-attach layer degradation.
TF / IOL Thermal Fatigue /
Intermittent Operating
Life
The device is submitted to cycled temperature excursions generated by power cycles (ON/OFF) at T ambient.
To investigate failure modes related to the thermo-mechanical stress induced by the different thermal expansion of the materials interacting in the die-package system. Typical failure modes are linked to metal displacement, dielectric cracking, molding compound delamination, wire-bonds failure, die-attach layer degradation.
H3TRB / THB Temperature Humidity Bias
The device is biased in static configuration minimizing its internal power dissipation, and stored at controlled conditions of ambient temperature and relative humidity.
To evaluate the package moisture resistance with electrical field applied, both electrolytic and galvanic corrosion are put in evidence.
PC Preconditioning
The device is submitted to cycled temperature excursions generated by power cycles (ON/OFF) at T ambient.
To investigate failure modes related to the thermo-mechanical stress induced by the different thermal expansion of the materials interacting in the die-package system. Typical failure modes are linked to metal displacement, dielectric cracking, molding compound delamination, wire-bonds failure, die-attach layer degradation.
Public Products List®
PCN Title : Front-End Capacity Extension for Power Bipolar Transistors (Planar Technology) - Tours (France) PCN Reference : IPD-PWR/13/7845 PCN Created on : 06-MAY-2013
Subject : Public Products List
Dear Customer,
Please find below the Standard Public Products List impacted by the change:
ST COMMERCIAL PRODUCT
2STL2580 2STL2580-AP BUF420AW BUF460AV BUL128 BUL128D-B BUL129D BUL138 BUL312FP BUL38D BUL39D BUL49D BUL58D BULB128-1 BULB49DT4 BULD118D-1 BULD39D-1 BUT11A BUV298V BUX348 BUX87 BUXD87T4 ESM6045DV ST13003-K ST13003D-K ST13005 ST13005N ST13007D ST8812FX ST901T STB13007DT4 STBV32 STBV32-AP STBV42 STBV42-AP STBV42G-AP STD13003T4 STD616A-1 STD901T STI13005-H STL128D STL128DFP STL128DN STL128DNFP STL73 STL73-AP STL73D STL73D-AP STLD128DNT4 STN2580 STT13005-K STT13005D-K STU13005N STW3040 STX0560 STX13003 STX13003-AP STX13003G STX13003G-AP STX13005 STX616-AP STX93003-AP TR136 TR236 TRD136DT4
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