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Master’s Thesis
October 2011
School of Engineering (ING)
Blekinge Institute of Technology
SE – 371 79 Karlskrona
Sweden
Processing Power Estimation of Encoders
for Wireless Capsule Endoscopy
Swarnalatha Mannar Mannan
Srinivasa Kranthi Kiran Kolachina
ii
This thesis is submitted to the School of Engineering at Blekinge Institute of Technology in
partial fulfillment of the requirements for the degree of Master of Science in Electrical
Engineering. The thesis is equivalent to 20 weeks of full time studies.
Contact Information: Author(s): Swarnalatha Mannar Mannan
E-mail: [email protected]
Srinivasa Kranthi Kiran Kolachina
E-mail: [email protected]
External advisor(s):
Prof. Tor A. Ramstad
Signal Processing Group Dept. of Electronics and Telecommunication
Norwegian University of Science and Technology Norway
Phone: +47 7359 4314
University Examiner:
Prof. Abbas Mohammed
Department of Electrical Engineering School of Engineering (ING)
Blekinge Institute of Technology
School of Engineering
Blekinge Institute of Technology
SE – 371 79 Karlskrona
Sweden
Internet : www.bth.se/com
Phone : +46 455 38 50 00
Fax : +46 455 38 50 57
1
ABSTRACT
Context: This particular project deals with video capture and compression of
Capsule Endoscopy (CE). Most video compression algorithms are of high-
complexity with heavy processing, substantial storage and data transfers. It will be a
great interest to clarify power consumption in different kinds of operations, which
could help in deciding among different compression algorithms. One consideration is
whether one has to resort to still image coding of frames (possibly at a decimated
frame rate with interpolation at the receiver), or to store frames in the encoder and
thus exploit the correlation between frames to reduce the bit rate. Our particular
interest in this project would be to decide how to integrate signal capture from the
sensor and compression algorithms in order to avoid excessive storage and read/write
operations. Furthermore, the compression algorithms must be simple to minimize
multiplications and additions. Suggested algorithms comprise 2 Dimensional (2D)
Differential Pulse Code Modulation (DPCM) with prediction coefficients and
transform coders with simple transforms.
Aims & Objectives: The aim of this project is to estimate the complexity/power
consumption of suggested system. This aim is achieved through the following
objectives
1. Identifying various available compression techniques for CE
2. Selecting the appropriate compression technique
3. Estimating the processing power of the selected compression technique
Tools: MATLAB, C
Algorithms: DPCM, Stack – Run Length Coding
Results: The power consumed/pixel by ADSP – BF – 533 processor operating at
1.14 V with 400 MHz of frequency produces 74.3 nW
Conclusions: The suggested system consumes less power.
Keywords: Capsule Endoscopy, Image
Compression, Power Estimation
2
ACKNOWLEDGEMENTS
It is a pleasure to thank the many people who made this thesis possible.
It is difficult to overstate our gratitude to our supervisor, Prof Tor A. Ramstad for
accepting us as his Master Thesis students at NTNU, Norway. With his enthusiasm,
his inspiration, and his great efforts to explain things clearly and simply, he helped to
make image processing fun for us. Throughout our thesis-writing period, he and Dr.
Anna N. Kim and Dr. Pål A. Floor provided encouragement, sound advice, good
teaching, and lots of good ideas. We would have been lost without them.
We are deeply grateful to our internal supervisor, Prof Abbas Mohammed, BTH,
for his detailed and constructive comments, and for his important support throughout
this work.
We warmly thank Dineshkumar Muthuswamy and Abhijith Gopalakrishna, for
their valuable advice and friendly help. Their extensive discussions around our work
and interesting explorations in operations have been very helpful for this study.
Special thanks to Revanth Parvathi, Poornima Vandhana Ravi and Ayswarya
Sankaran for their efforts in proof reading the report and making the work a neat
presentation.
We would like to express our deepest sense of gratitude to our GOD, Almighty
who gave us strength and courage to complete this gigantic task.
I Srinivasa Kranthi Kiran Kolachina, would like to thank my parents
Mrs. Revathi Kolachina & Mr. SanyasiRao Kolachina for their love and support. I
would also like to thank my brother Mr. Ramakrishna Kolachina, who is my role
model and my constant encouragement in the course of my Masters.
I Swarnalatha Mannar Mannan, very grateful to my parents Mrs. Bhanumathi
Mannar Mannan & Mr. Mannar Mannan. S. They bore me, raised me, supported
me, taught me and loved me. This thesis has only been possible through their
significant sacrifices and devotion to provide me a brighter future. Their strength,
devotion towards work and encouragement has taught me 'not to give up anything'
and has made me the person I am today.
3
I wish to express gratitude my brother Mr. Saravanan Chidambaram for helping
me get through the difficult times and for all the emotional support, camaraderie, and
caring he provided.
Last but not the least, my deepest appreciation goes to Mr. Balamurugan
Mohandoss. He forms the backbone and origin of my happiness. His love and
support with any complaint or regret enabled me to overcome the frustrations in
writing this thesis. He took every responsibility and suffered all the bitterness so as to
enable me to concentrate on my thesis work. I owe my every achievement to him.
4
Table of Contents
ABSTRACT .......................................................................................................................................... 1
ACKNOWLEDGEMENTS ................................................................................................................. 2
1 INTRODUCTION ....................................................................................................................... 7
2 BACKGROUND .......................................................................................................................... 8
2.1 RELATED WORK .................................................................................................................... 8
3 RESEARCH AGENDA ............................................................................................................. 11
3.1 RESEARCH FOCUS ................................................................................................................ 11
3.2 OBJECTIVES ......................................................................................................................... 11
4 SYSTEM MODEL ..................................................................................................................... 12
4.1 INTRODUCTION .................................................................................................................... 12
4.1.1 Image capturing .............................................................................................................. 12
4.1.2 Source encoder ............................................................................................................... 14
5 ADSP- BF-533 PROCESSOR DESCRIPTION ...................................................................... 19
5.1 INTRODUCTION .................................................................................................................... 19
5.2 ARCHITECTURAL FEATURES ................................................................................................ 19
5.3 ADSP - BF-533 FEATURES .................................................................................................. 19
5.4 ADSP - BF-533 SPECIFICATIONS ......................................................................................... 20
5.5 FUNCTIONAL BLOCK DIAGRAM ADSP - BF-533 ................................................................. 20
5.6 RECOMMENDED OPERATING CONDITIONS ........................................................................... 21
6 ANALYSIS AND EXPERIMENTAL RESULTS ................................................................... 22
6.1 CODE COMPLEXITY CALCULATION - SUGGESTED SYSTEM .................................................. 24
6.1.1 RGB to YUV .................................................................................................................... 25
6.1.2 DPCM_YUV_ENC .......................................................................................................... 26
6.1.3 FRAME_SRENCODE ..................................................................................................... 27
6.1.4 SR_ENCODE .................................................................................................................. 28
6.1.5 Overall Code Complexity ................................................................................................ 30
6.2 POWER CONSUMPTION CALCULATION – SUGGESTED SYSTEM ............................................ 31
6.3 POWER CONSUMPTION OF DCT ALGORITHM BY ADSP- BF-533 ......................................... 33
6.4 RESULTS .............................................................................................................................. 35
7 CONCLUSION AND FUTURE WORK ................................................................................. 36
8 REFERENCES ........................................................................................................................... 37
5
List of Figures
Figure 1 System Model ........................................................................................................... 12
Figure 2 Image Capture Block ................................................................................................ 12
Figure 3 Interpolation Step [19] ............................................................................................. 12
Figure 4 Source Encoder Block .............................................................................................. 14
Figure 5 Original Image.......................................................................................................... 17
Figure 6 Reconstructed Image ................................................................................................ 17
Figure 7 Functional Block Diagram of BF-533 [7, 8] ............................................................ 20
Figure 8 Analysis Model ........................................................................................................ 23
Figure 9 Block Diagram for Code Complexity ...................................................................... 24
Figure 10 The JPEG Compression Algorithm [18] ................................................................ 33
6
List of Tables Table 1 Design Comparison ................................................................................................... 10
Table 2 BF-533 Specifications [7, 8] ...................................................................................... 20
Table 3 Recommended Operation Conditions - BF533 [7, 8] ................................................ 21
Table 4 Code Complexity - RGB to YUV .............................................................................. 25
Table 5 Lines of Code - RGB to YUV .................................................................................. 25
Table 6 Code Complexity - DPCM_YUV_ENC .................................................................... 26
Table 7 Lines of Code - DPCM_YUV_ENC ........................................................................ 26
Table 8 Code Complexity - FRAME_SRENCODE ............................................................... 27
Table 9 Lines of Code - FRAME_SRENCODE .................................................................... 27
Table 10 Case 1: If input values and the array values are zero ............................................... 28
Table 11 Case 2: Input is zero and Non-Zero value in later part of array .............................. 29
Table 12 Case 3: If all inputs are Non-Zero values ................................................................ 29
Table 13 Total No of Operations in SR_Encode .................................................................... 30
Table 14 Overall Code Complexity ........................................................................................ 30
Table 15 Power Consumption at 400 MHz & 1.14 V ............................................................ 32
Table 16 Power Consumption at 500 MHz & 1.2 V .............................................................. 32
Table 17 Power Consumption at 533MHz & 1.2 V ............................................................... 33
Table 18 Quantization Table T [18] ....................................................................................... 34
Table 19 Comparison - Power Consumed by Suggested System and Other System ............. 35
7
1 INTRODUCTION
Visual scrutiny of inner digestive track is required for diagnosis of many Gastro
Intestinal (GI) diseases. Only after the development of Capsule Endoscope (CE) the
observation in small bowel became possible [34]. Disease in the alimentary canal as
well as in diagnosing inflammatory disease like Crohn’s Disease, Celiac Disease, and
other kinds of malabsorption disease, malignant tumors of the small intestine, small
bowel injury due to medication can be diagnosed using GI endoscopy. There are two
different kinds of GI endoscopy namely wired active endoscopy and CE. Though
wired active endoscopy is efficient in diagnosis on biopsy samples and real time
images it causes severe pain for the patients due to pushing of large sized cables into
the digestive track [24]. CE was developed to reduce the patients suffering [13, 26,
51].
CE reduced the physical pains caused by the wired capsule endoscopy [36]. CE
comes with a camera in a pill shaped capsule which is used to produce images or
video of the digestive track. The images produced by the camera are then transmitted
to a receiver or receivers which are placed around the waist connected through a
wireless interface.
Though CE has reduced the physical pain caused by the traditional endoscopy
there are some limitations in it. It does not provide the picture quality as produced in
wired version. The frame rate of the capsule is as low as 2 frames per second (fps) to
as high as 10 fps [36]. The power consumed by the pill is also a constraint since it is
battery operated.
In this report we will make a feasibility study of estimating the processing power
of the suggested system for different blocks at an algorithmic level. This will serve as
a background for some practical experiments at different levels later on.
In order to minimize the power consumption in this process, the video should be
compressed as much as possible using low complexity algorithms
Suitable schemes were suggested in Medical Sensing, Localization and
Communication using Ultra Wideband Technology (MELODY) projects’ initial
proposal and technical specifications. The schemes applied in the demonstrator will
mainly be built on these suggestions: Differential Pulse Code Modulation (DPCM)
compression will be applied for video compression and quantization additional
processing like entropy coding.
We will still try to keep the processing power as low as possible, also due to the
complexity and size of the hardware [12, 14]. In this report we considered only about
the processing power consumption. Lighting up the digestive tube is also a main
issue, but this is outside the scope of our research.
8
2 BACKGROUND
The resolution of the image is determined by the size of the sensor. Power
consumption increases with increase in the size of the sensor. Hence applying image
compression techniques is required for power saving [24]. Papers [10, 24, 27, 32, 35,
36, 40, 41, 42, 44] have provided various compression standards to decrease the
power consumption.
The scope of this thesis work is to calculate the complexity/power consumed by
the suggested system. The numbers achieved through this study can be used for
comparison to other schemes and determine whether modifications and replacements
are beneficial or necessary.
2.1 Related Work
There are many publications describing the current trend on CE and technologies.
One of the recent papers [22] gives a good history of capsules from their early
development to clinical implementation. The design of wireless capsules started
around 1950’s, since then they have been called as endoradiosondes, capsule,
electronic pill, wireless capsule, CE and so forth. The early attempts were based on
low frequencies and with simple structures [21, 25]. Despite simplicity, the early
systems were bulky due to large electronic components and batteries used and were
targeting temperature, pH and pressure [20, 45].
Few years ago, the small bowel was an organ which was very difficult to explore
with the available endoscopic, radiological and nuclear medicine techniques. Sonde
enteroscopy had been abandoned in the 90’s because it was a tedious technique (long
duration of procedure) and it had several technical limitations. Push enterscopy is
limited by the depth of insertion of the scope and is poorly tolerated. Intraoperative
enteroscopy is the most effective of these techniques, but it is the most invasive with
a significant percentage of adverse side effects [29].
With CE one can provide a simple, safe, non-invasive, reliable procedure well
accepted by patients, which has revolutionized the study of the small bowel. This
technique evaluates endoscopically with high resolution images, the whole small
bowel, avoiding any sedation, surgery or radiation exposure [29].
Ongoing research is continuing in the United States, Japan, Israel, South Korea and
United Kingdom to improve Capsule Endoscope technology. Sayaka Capsule by RF
system of Japan is an advanced capsule with power supplied wirelessly from an
external source [46]. In Japan, capsule endoscopy is now approved for use in the
small bowel and in Europe, capsule endoscopy is being used for several areas
including colon screening since July 2007.
9
Capsule endoscopy is a new technology that was recently introduced into clinical
practice for the diagnosis of gastrointestinal diseases. As of today, three different
capsule types have been produced, designed for the exploration of the small bowel
(Pillcam SB), the esophagus (Pillcam ESO) and the colon (Pillcam colon). The
Pillcam SB has gained widespread acceptance as a powerful tool for the diagnosis of
bleeding from the small bowel as well as for other indications. The Pillcam ESO has
been used to study patients with gastroesophageal reflux diseases, for the screening
of Barrett’s esophagus and for the screening and surveillance of esophageal varies in
patients with cirrhosis.
Table 1 summarizes the commercially available electronic pill technologies that
are already been used in clinical environments. Current CE device by “Given
Imaging” is used to diagnose disorders such as Crohn's disease, Celiac disease,
benign and cancerous tumors, ulcerative colitis, gastrointestinal reflux disease
(GERD), and Barrett's esophagus [48]. The pill uses the Zarlink’s RF chip for
wireless transmission [4]. The chip uses the MICS band that allows channels with
only 300 kHz. It is thus difficult to assign enough data rate for the high quality
image and video data at the moment for a real time data transfer and
monitoring.
RF Norika by RF system lab has a wireless power capability and localization
capabilities. Another endoscope EndoCapsule was developed by Olympus was
mainly used in Europe. The device contains 6 LED’s with adjustable illumination to
maintain optimal imaging. Currently all video based commercial systems being
designed are based on illumination. With information available from public domain,
these pills are described in Table 1 [43].
There have been some papers reported on the image compressor of the capsule. In
[24, 35, 33], Discrete-cosine-transform (DCT) based image compressors are
proposed. In DCT-based image compressors, 4 × 4 or 8 × 8 pixel blocks need to be
accessed from the image sensor. However, commercial CMOS image sensors [49,
50] send pixels in a row-by-row (i.e., raster-scan) fashion and do not provide buffer
memory. So, to implement these DCT-based algorithms, buffer memory needs to be
implemented inside the capsule to store an image frame. For instance, in order to
store a 256 × 256 size color image (i.e., 24 bits per pixel), a minimum size of
1.57 Mbits buffer memory is required. The memory takes large area and consumes
sufficient amount of power which can be a noticeable overhead. Moreover, the
computational cost associated in such transform-coding (i.e., multiplications,
additions, data scheduling, etc.) results in high area and power consumption.
DCT-based compression algorithms are lossy. For proper medical diagnostics,
lossless images are more desirable [32].
10
Table 1 gives a comparison of designs from different vendors, [47, 48, 49].
Table 1 Design Comparison
Model Company Camera Frequency
(MHz)
Data
Rate
Power
Source
Physical
Dimension
(mm x
mm)
Image Rate &
Resolution
PillCam
(SB)
Given
Imaging
Micro,
CMOS
402 – 405
& 433
(Zarlink)
800
Kbps
(FSK)
Battery 11 X 26
<4gr
14
images/second
or 2,600 color
images
EndoCapsule Olympus
Optical
CCD
Camera
N/A N/A Battery 11 X 26 2
images/second
Norkia RF
System
Lab
CCD
Image
Sensor
N/A N/A Wireless
Power
9 X 23 N/A
In this report we mainly focus on processing power consumption. DPCM
compression will be applied for video compression and some additional processing
like entropy coding is used to reduce the bit rate.
11
3 RESEARCH AGENDA
3.1 Research Focus
To calculate the complexity/power consumed by the system we intend to
investigate the various compression techniques that are presented in papers [10, 24,
27, 32, 35, 36, 40, 41, 42, 44]. The best compression technique is selected. For
further research and development, a compression technique is selected which
consumes low power.
3.2 Objectives
The below given are the objectives of this thesis
1. Identifying the various compression techniques present for CE
2. Selecting the appropriate compression technique
3. Estimating the processing power of the compression technique
12
4 SYSTEM MODEL
4.1 Introduction
In this section the necessary system components are presented in Figure 1.
Suggested solutions for the different blocks will be given in the following.
Figure 1 System Model
4.1.1 Image capturing
Capturing of an image is represented in a block in Figure 2. The below block
diagram represents Lens, Sensor, CFA/ demosaicking, and finally JPEG image in
order of flow of information.
Figure 2 Image Capture Block
Figure 3 Interpolation Step [19]
13
CMOS image sensors [23, 30, 38, 52] are fabricated using CMOS processes with
no or minor modifications. Addressing of each pixel in the array is done through a
horizontal word line and the charge or voltage signal is read out through a vertical bit
line. Analog to digital conversion is done by the transistors neighboring each pixel.
Reading out the row using the column decoders and multiplexers is done after the
transferring of one row at a time to the column storage capacitors is performed. The
memory structure is similar to the readout method. The three commonly seen pixel
architectures are [5]
• Passive pixel sensor (PPS)
• Active pixel sensor (APS)
• Digital pixel sensor (DPS)
Raw formats are typically either uncompressed or use lossless compression, so that
maximum amount of image details is always kept within the raw file. The contents of
raw files include more information, and potentially higher quality, than the converted
results, in which the rendering parameters are fixed, the color gamut is clipped, and
there may be quantization and compression artifacts.
A raw file is a record of the data captured by the sensor. There are many ways of
encoding this raw sensor data into a raw image file, in each case the unprocessed
sensor data files are recorded. In the category of “digital camera,” a number of
different technologies are included that shoot raw are known as “mosaic sensor” or
“color filter array” (CFA) cameras [53].
The photos that are present in the image are collected using CFA camera 2D area
array. The array is built up with rows and columns of photosensitive detectors-using
either CCD (charge-coupled device) or CMOS (complementary metal oxide
semiconductor) technology to form the image. A key point is that raw files from
color filter array cameras are grayscale [53].
The role of the color filter array is to create color images from the raw grayscale
capture. Each element in the array is covered by a color filter, so that each element
captures only red, green, or blue light. Many cameras apply the filters in a Bayer
pattern. Some cameras use CMY rather than RGB filters because they transmit more
light. The common factor in all color filter array cameras is that, each element in the
sensor captures only one color [53].
The CMOS sensor’s surface is covered with a color filter array (CFA). The CFA
consists of a set of spectrally selective filters that are arranged in an interleaving
pattern so that each sensor pixel samples one of the three primary color values (for
example, red, green and blue values). These sparsely sampled color values are
referred to as CFA samples. To render a full-color image from the CFA samples, an
image reconstruction process commonly referred to as CFA demosaicking or CFA
interpolation method is required to estimate for each pixel its two missing color
values. There different types of CFA interpolation techniques such as Linear,
Bilinear and bicubic etc., [19].
14
Many demosaick methods have been proposed in the literature [1, 2, 6, 11, 16, 37].
Linear interpolation is probably the simplest one as it fills missing color values with
weighted averages of their neighboring pixel values. Although computationally
efficient and easy to implement, bilinear interpolation introduces severe
demosaicking artifacts and smears sharp edges. To obtain more visually pleasing
results, many adaptive CFA demosaicking methods have been proposed to exploit
the spectral and spatial correlations among neighboring pixels [19].
Demosaicking is not used in an endoscope application since it uses a floating point
operation, which can rather be complex or power consuming. The researchers either
work directly on the raw image i.e in RGB colour space or apply simple transforms
to convert to YUV colour space. The latter is used in our application.
In addition the experts also decide the video resolution of the still image which has
a direct influence on the following factors
1. Complexity
2. Bandwidth
3. Power consumption of the system
There is a possibility to construct the system with dual mode where one mode with
standard resolution and the other with higher resolution. When a return channel is
available, the physician could change to the high resolution mode when required or
else keep it at the low resolution in order to save the power.
4.1.2 Source encoder
The image capture block is followed by a source encoder block as shown in
Figure 1. Figure 4 shows the source encoder block.
Figure 4 Source Encoder Block
As shown in Figure 4, the source encoder block contains a lossy video
compression scheme followed by digitization and run length coding.
4.1.2.1 Video Compression
The bit rate can be considerably reduced when sub band decomposition techniques
are used in standard video coders. But still, this method generally needs to store the
entire frame for processing and can be computationally extensive. Hence a less
15
complex Differential Pulse Code Modulation (DPCM) algorithm is considered. This
scheme uses spatial correlation by 2-Dimensional (2D) pixel-by-pixel predictions.
Later the prediction error is quantized and encoded using entropy or run length
coding in order to achieve a low bit rate.
The inter frame prediction and encoding of the motion vectors can be used to
exploit the temporal correlation. But, this may require storing at least one full image
frame which in turn results in too much power consumption due to access of memory
in hardware. Hence in order to increase the frame rate without increasing complexity,
power consumption and bit rate at the encoder one has to perform motion
compensation and prediction at the decoder. This can be combined with different
techniques of interpolation and inter frame manipulation and transforms.
Thus the video encoder will operate on a frame basis and the components of video
encoder are given below
a) Simple transform from RGB space to YUV space
b) Compression using 2D DPCM
c) Quantization and coding
Red (R), Green (G) and Blue (B) are different color information present in the raw
data which is directly captured by the image sensor. Since the human eye is more
sensitive to Green colour, normally there will be twice as many G components
compared to R and B components. The work can be carried out either directly on the
raw colour data or converting them to Luminance (Y) and Chrominance (U and V)
components. Working on the raw colour data has the advantage of avoiding floating
point calculations, which is required by the standard colour space transform.
However, better compression efficiency is normally predicted from processing in
YUV space. As suggested in [36], the simple colour space transform can be applied.
Initially one of the two G components is skipped. The transform that operates on
RGB space needs only addition, subtraction and division of 2. Hence the complexity
in hardware is much reduced
+
−
−=
128
128
0
5.005.0
5.05.00
125.05.025.0
B
G
R
V
U
Y
The DPCM coder is used to compress each component after conversion to YUV
colour space. This compression removes the spatial correlation between the image
pixels. The maximum energy is carried by the luminance component (Y) and also
dictates the form of the image objects. The prediction of current pixel value Yp(i,j) is
calculated by using the values from two neighbouring and one diagonal pixel. The U
and V components which carry colour information and less energy are predicted by
simply copying the previous (left) pixel value.
16
)1,(),(
)1,(),(
),1()1,()1,1(),(
−=
−=
−+−−−−=
jiVjiV
jiUjiU
jiYjiYjiYjiY
p
p
p
Before encoding into bit streams the prediction error of each component is
quantized. The quantization is done in such a way that there is no greater loss in the
overall image quality. Normally the U and V components are coarsely quantized
when compared to the Y component. Since they have a smaller dynamic range only
fewer bits are normally needed to encode the quantization levels. The quantization
intervals can be tuned based on the nature of analysis, that is, either the importance is
given to the colour information or more details need to be retained in the contours
(governed by luminance).
The quantization levels need to be presented effectively in binary form in order to
reduce the actual bit rate for transmission. Applying entropy coding is a common
approach to reduce the bit rate for transmission. Information of the distribution of
the quantized values is normally required by several entropy codes. Run length
coding is a simple and also an effective substitute when compared to other entropy
codes which require knowledge about distribution of the quantized values. Run
length coding uses a string of inputs of same value (e.g. zero) can be coded as the run
length or the number of pixels carrying the same value, instead of coding the value
over and over again. As discussed in paper [34] stack-run coder is one special low
rate coding scheme. Stack run coder uses four symbols to represent the length of
zeros and the non – zero quantization levels. By using entropy coding the run-length
coded symbols can be reduced further. The use of two bits for each stack-run symbol
is a simple and straight forward method. To increase robustness against channel
noise the stack run coder can be jointly optimized with channel codes as presented in
paper [28].
The following example is used to illustrate the performance of the above described
video compression scheme. A uniform mid-tread quantizer is used for quantization.
Then stack run coding is performed on the quantized prediction errors of YUV
components for each line of the image. The performance is measured using Peak
Signal to Noise Ratio (PSNR), which is defined as (shown for the Y channel, where
Y is the reconstructed value)
[ ]∑∑= =
−
=I
i
J
j
jiYjiYIJ
PSNR
1 1
2
2
),(ˆ),(1
255log10
When a 2 bit binary representation of the encoded symbols are used directly
without applying additional entropy coding of stack run codes, the average PSNR of
the reconstructed image reaches 43dB with an average bit rate of 2.365 bits per pixel
(bpp). The resulting Compression Rate (CR) can also be noted in addition to the bit
rate. CR is defined as CR = (1 – CS / OS) * 100%, where CS is the compressed
17
image size in bits and OS is the original raw image size in bits (8 bits per colour
channel). The corresponding CR is 90%. Figure 5 shows the original image of
dimension 422 X 355 pixels and the reconstructed image on Figure 6.
Figure 5 Original Image
Figure 6 Reconstructed Image
From both the storage and processing perspective the suggested DPCM still image
coding is attractive. One fundamentally needs to store one scan-line of raw image
data then perform the colour space transform followed by one stored line of Y
component for 2D prediction. U and V channels are not stored since the prediction is
1 Dimensional (1D). Thus the resulting number of mathematical operations per pixel
is limited to simple addition, subtraction and bit shift.
18
4.1.2.1.1 Alternatives
A dead zone uniform quantizer can be used in order to further reduce the bit rate of
the coding scheme described in Section 4.1.2.1. The use of dead zone quantizer
means that around zero value of the quantization interval is larger when compared to
the other intervals; therefore more values will be quantized to zero. Then the run
length coder can take the advantage of the longer runs of zero.
To reduce the bit rate required for encoding the two chrominance components U
and V have to be subsampled. But as described in Section 4.1.2.1, the degree of
subsampling and coarse quantization will depend on the diagnostic requirements of
the reconstructed image. But in some cases it is required to maintain better colour
information.
For better compression efficiency very simple transforms like Hadamard transform
which consists of {1;-1} can be used. Two lines of image pixels are required to be
stored for a 2 X 2 transform. When compared to DPCM, the quantized transform
coefficients might have longer run-length values. If required, it can also offer better
preservation of high frequency components. Before coming to any firm conclusion
the balance between algorithmic and transmission power consumption must be
studied.
An alternative way to reduce the total bit rate required for transmission is to use a
variable frame rate. For instance, there might be a large correlation between the
frames based on the part of the Gastro Intestinal (GI) track due to that fact that the
endoscope is moving very slowly. Due to complexity requirements the motion
compensation is not considered, the inter-frame correlation can be exploited by
reducing the frame rate in these areas. In this case the two major costs are incurred:
1) Memory and 2) Power required accessing the frames for comparison. Hence a
trade-off can be made depending on the overall power estimation of the algorithms.
In addition to this, the image sensor can also be custom made for low power
consumption as shown in paper [44]. At the same time it also has an ability to store
the raw pixel values and serve as a buffer for compression and transmission. This
type of hardware can make both the above mentioned variable frame rate and sub
band decomposition type compression scheme more easily implementable.
19
5 ADSP- BF-533 PROCESSOR DESCRIPTION
5.1 Introduction
In today’s most challenging convergent signal processing applications BF-533
offers high performance and power-efficient processor. The below given
characteristics of the Blackfin processor allows various system designers to use the
flexible platform in designing a wide range of applications in numerous fields
namely consumer communications, automotive and industrial/instrumentation [8].
• 16-bit/32-bit Blackfin embedded processor core
• Flexible cache architecture
• Enhanced Direct Memory Access (DMA) subsystem
• Dynamic Power Management (DPM)
5.2 Architectural Features
The below given are the architectural features of BF-533 [7, 8]
1. High performance 16-bit/32-bit embedded processor core
2. 10-stage Reduced Instruction Set Computing (RISC) Micro
Controller Unit (MCU)/ Digital Signal Processor (DSP) pipeline
with mixed 16-bit/32-bit ISA for optimal code density
3. Full Single Instruction – Multiple Data (SIMD) architecture,
including instructions for accelerated video and image processing
4. Memory Management Unit (MMU) supporting full memory
protection for an isolated and secure environment
5.3 ADSP - BF-533 Features
ADSP - BF-533 has the below given features [7, 8]
• Application-tuned peripherals provide glueless connectivity to
general-purpose convertors in data acquisition applications
• Large on-chip SRAM for maximum system performance
20
5.4 ADSP - BF-533 Specifications
Table 2 provides the specifications for BF-533 [7, 8]
Table 2 BF-533 Specifications [7, 8]
Maximum Clock Speed 600 MHz
Million Multiply Accumulate Cycles
per Second (MMACS) – Max
1500
External Memory Bus 16 bit
PPI Yes
Core Voltage (V) 0.8 – 1.3
Core Voltage Regulation Yes
USB Device No
5.5 Functional Block Diagram ADSP - BF-533
Figure 7, shows the functional block diagram of ADSP - BF-533. Figure 7, is
taken from the Blackfin Processor manual available at [7, 8].
Figure 7 Functional Block Diagram of BF-533 [7, 8]
21
5.6 Recommended Operating Conditions
Table 3 provides the recommended operation conditions for BF-533
processor [7, 8]
Table 3 Recommended Operation Conditions - BF533 [7, 8]
Parameter Min Nor Max Unit
VDDINT Internal Supply Voltage (ADSP-
BF531 and ADSP-BF532) 0.8 1.2 1.32 V
VDDINT Internal Supply Voltage (ADSP-
BF533) 0.8 1.26 1.32 V
VDDENT External Supply Voltage 2.25 2.5 3.6 V
VDDRTC Real-Time Clock Power Supply
Voltage 2.25 3.6 V
VIH High Level Input Voltage 1, 2
@VDDEXT=maximum 2.0 3.6 V
VIHCLKIN High Level Input Voltage 3 @
VDDEXT=maximum 2.2 3.6 V
VIL Low Level Input Voltage2, 4 @
VDDEXT=minimum -0.3 0.6 V
22
6 ANALYSIS AND EXPERIMENTAL RESULTS
This chapter presents the analysis of power consumed by the given algorithm on a
Blackfin ADSP- BF-533 processor and the result is compared with the power
consumed by DCT algorithm in ADSP- BF-533. Figure 8 describes the analysis
model.
Initially RGB components of the image are converted to YUV components.
Secondly, after conversions the image is passed into two different stages like
compression and encoding. As described in Chapter 2, from various researches [10,
24, 27, 32, 35, 36, 40, 41, 42, 44] it is decided to go with 2D-DPCM algorithm for
image compression followed by stack run-length encoding technique.
After compression and encoding stage the image is reconstructed. Now the
reconstructed image is compared with the original image to identify if there are any
noticeable variations present.
After the reconstruction of the image, the code complexity and the power
consumed at the algorithmic level is calculated.
The calculated power of the suggested algorithm for ADSP- BF533 is compared
with the power consumed by the DCT algorithm for ADSP- BF-533 processors to
see if the power consumption is less. If yes, then the suggested system is validated
and no further changes or modifications are required. If no, then a new system is
suggested and necessary changes and modifications are made.
23
Figure 8 Analysis Model
24
6.1 Code Complexity Calculation - Suggested System
The complexity of the code is calculated based on the number of adders,
multipliers, shift registers, comparators, log and load operations used. Figure 9
presents a block diagram for code complexity calculation.
Initially RGB components of the image are converted to YUV components. After
which, it is passed through 2D-DPCM compression algorithm “DPCM_YUV_ENC”
block. Followed by, encoding technique performed by “FRAME_SRENCODE”
which internally calls “SR_ENCODE” block.
The results of the code complexity for each individual block and the overall
complexity of the code are presented in Table 4 – 14.
The code complexity of the suggested system is calculated assuming the image of
resolution 409 X 422.
Figure 9 Block Diagram for Code Complexity
25
6.1.1 RGB to YUV
Table 4 presents the numbers of operations required to run RGB to YUV function.
The lines of code for Table 4 are given in Table 5.
Table 4 Code Complexity - RGB to YUV
No Adders Multipliers Shift Registers Load Log Comparators
1 2 0 3 0 0 0
2 2 0 2 0 0 0
3 2 0 2 0 0 0
Total No of
Operation/Pixel6 0 7 0 0 0
No of Pixels/Line 409 409 409 409 409 409
Total No of
Operations2454 0 2863 0 0 0
RGB to YUV
Table 5 Lines of Code - RGB to YUV
No Lines of Code
1 Y[i][j]=pic[i][j][0]/4+pic[i][j][1]/2+pic[i][j][2]/8
2 U[i][j]=128-pic[i][j][1]/2+pic[i][j][2]/2
3 V[i][j]=128+pic[i][j][0]/2-pic[i][j][1]/2
26
6.1.2 DPCM_YUV_ENC
Table 6 presents the numbers of operations required to run DPCM_YUV_ENC
function. The lines of code for Table 6 are given in Table 7.
Table 6 Code Complexity - DPCM_YUV_ENC
No Adders Multipliers Shift Registers Load Log Comparators
1 1 0 0 0 0 0
2 0 1 0 0 0 0
3 1 1 0 0 0 0
4 2 3 0 0 0 0
5 1 0 0 0 0 0
6 0 1 0 0 0 0
7 1 1 0 0 0 0
8 1 0 0 0 0 0
9 0 1 0 0 0 0
10 1 1 0 0 0 0
Total No of
Operation/Pixel8 9 0 0 0 0
No of Pixels/Line 409 409 409 409 409 409
Total No of
Operations3272 3681 0 0 0 0
DPCM_YUV_ENC
Table 7 Lines of Code - DPCM_YUV_ENC
No Lines of Code
1 dY = Y[ii][jj] - Yp;
2 levelsY[ii][jj] = (int)
round(dY/deltaY);
3 Y_rec[ii][jj] = Yp + (double)
levelsY[ii][jj] * deltaY;
4 Yp = b*Y_rec[ii][jj] + a*Y_rec[ii][jj]
+ c*Y_rec[ii][jj];
5 dU = U[ii][jj] - Up;
6 levelsU[ii][jj] = (int)
round(dU/deltaU);
7 U_rec[ii][jj] = Up + (double)
levelsU[ii][jj] * deltaU;
8 dV = V[ii][jj] - Vp;
9 levelsV[ii][jj] = (int)
round(dV/deltaV);
10 V_rec[ii][jj] = Vp + (double)
levelsV[ii][jj] * deltaV;
27
6.1.3 FRAME_SRENCODE
Table 8 presents the numbers of operations required to run FRAME_SRENCODE
function. The lines of code for Table 8 are given in Table 9.
Table 8 Code Complexity - FRAME_SRENCODE
Line No. Adders Multipliers Shift Registers Load Log Comparators
34 0 1 1 0 0 0
37 0 1 1 0 0 0
40 0 1 1 0 0 0
Total No of
Operation/Pixel0 3 3 0 0 0
No of Pixels/Line 409 409 409 409 409 409
Total No of
Operations0 1227 1227 0 0 0
FRAME_SRENCODE
Table 9 Lines of Code - FRAME_SRENCODE
No Lines of Code
1 rate_srY[i-1] = 2 *
(double)len_tempY / (double)cols;
2 rate_srU[i-1] = 2 *
(double)len_tempU / (double)cols;
3 rate_srV[i-1] = 2 *
(double)len_tempV / (double)cols;
28
6.1.4 SR_ENCODE
The complexity of this algorithm depends on input values. There are three different
cases which are given below.
• Case 1: If all input values are zero then the algorithm is run only once
for given input.
• Case 2: If input is mix of zeros and non-zeros, run length of zero is
obtained and the code is processes only once for that run length.
• Case 3: If the element of input is non-zero, then for each element the
code is run.
Hence the complexity of each loop is calculated and the maximum is considered.
• Input: 32 Data Values
• Output: +/-/0 or 1 values (variable length)
• Maximum Length: 32 Characters
Table 10 shows the code complexity when all the input values and array values are
zero
Table 10 Case 1: If input values and the array values are zero
S No Lines of Code Adders Multipliers Comparator Load/store Other operation Notes
1 find(x~=0, 1) 0 0 0 32 Zero Flag Check
2 RLbin_str = dec2bin(length(x)); 0 0 0 0 -
All numbers are in
Binary
3 round(log2(length(x)+1))-log2(length(x)+1)~=0 1 0 0 0 Log2
4 sizey2 = sizey2+length(RLbin_str); 1 0 0 0
5 sizey1 = sizey2+1; 1 0 0 0
Total 3 0 0 32
These operations are
required for the array
of zeros values
Input Size is <= 32 32 0 0 0
Total operations / per call of the code 96 0 0 0 16
Case 1 If input value and the following values are all zero
29
Table 11 shows the code complexity when the input is zero and the later part of the array
has non-zero elements.
Table 11 Case 2: Input is zero and Non-Zero value in later part of array
S No Code Adders Multipliers Comparator Load/store Other operation Notes
1 marker = length(x(1:find(x~=0, 1 )-1)); 0 0 0 32 0
At the most you need
32 loaders
2 Rlbin_str = dec2bin(marker); 0 0 0 0 0
This not required in
the processor
3 round(log2(marker+1))-log2(marker+1)~=0 1 0 0 0 Log2
4 sizey2 = sizey2+length(RLbin_str); 1 0 0 0 0
5 sizey1 = sizey2+1; 1 0 0 0 0
Total 3 0 0 32 0
Input Size < 32 32 0 0 0 0
Total operations / per call of the code 96 0 0 0 16
Operations like
extracting Sign and
Absolute can be
avoided in processor if
we make use of Sign
bit and 2' Complement
Case 2 If input is zero and have a non zero value in the later part of the array
Table 12 shows the code complexity when all the inputs are non-zero elements.
Table 12 Case 3: If all inputs are Non-Zero values
S No Code Adders Multipliers Comparator Load/store Other operation Notes
1 nz_val = sign(x(1))*(abs(x(1))+1); 1 0 1 0 0
2 NZbin_str = dec2bin(abs(nz_val)); 0 0 0 0 0
3 sizey2 = sizey2+length(NZbin_str); 1 0 0 0 0
4 y(sizey1:sizey2)=NZbin_str; 0 0 0 0 0
This code is part of
control code and it
can be handled better
if the code is rewritten
5 sizey1 = sizey2+1; 1 0 0 0 0
This code is part of
control code and it
can be handled better
if the code is rewritten
Total 3 0 1 0 0
These operation are
required for one non
zero value
Input Size 32 0 32 0 0
Total operations / per call of the code 96 0 32 0 0
Operations like
extracting Sign and
Absolute can be
avoided in processor if
we make use of Sign
bit and 2' Complement
Case 3 If all input are non zero values
30
Table 13 Total No of Operations in SR_Encode
Line No. Adders Multipliers Shift Registers Load Log Comparators
96 0 0 32 16 32
Total No of
Operation/Pixel96 0 0 32 16 32
No of Pixels/Line 409 409 409 409 409 409
Total No of
Operations39264 0 0 13088 6544 13088
SR_ENCODE
6.1.5 Overall Code Complexity
Table 14 shows the numbers of operations performed in each function and also the
total numbers of operations involved in the overall process.
Since ADSP – BF – 533 is a 32 – bit processor with two 16 – bit data address we
can reduce the numbers of adders and load operators by a factor of 2.
Table 14 Overall Code Complexity
S.No Function Adders Multipliers Shift Registars Load Log Comparators
1 RGB to YUV 2454 0 2863 0 0 0
2 DPCM_YUV_ENC 3272 3681 0 0 0 0
3 FRAME_SRENCODE 0 1227 1227 0 0 0
4 SR_ENCODE 39264 0 0 13088 6544 13088
5 Total 44990 4908 4090 13088 6544 13088
6 No of Cycle/Operations 1 1 2 1 2 2
7Total No of
Cycles/Operation44990 4908 8180 13088 13088 26176
8 32-Bit Processor 22495 4908 8180 6544 13088 26176
Total No of
Cycles81391
Total No of
Cycles for an
image of
resolution 409
x 422
34347002
31
6.2 Power Consumption Calculation – Suggested System
To calculate the power consumed by an image of resolution 409 X 422 by
the suggested algorithm, Blackfin processor ADSP - BF-533 is considered.
The below given factors are assumed for power consumption calculation
1. The processors operate at three different frequencies, fCCLKi.e
400MHz, 500MHz and 533 MHz
2. The processors operate at two different voltage levels, VDD-INT i.e
1.14V and 1.2V
3. The number of cycles/pixel are taken from Table 14
VDD-INT, fCCLK, IDD-TYP values are taken from the processor data sheet
available at [7, 9].
The power consumption is calculated as below:
1. Total No of Cycles = X
2. Frequency, fCCLK = f MHz
3. Y = Total No of Cycles * (1/Frequency)
= X * (1/fCCLK)
4. Z = VDD-INT * IDD-TYP
5. Power Consumed = Y * Z (W)
For instance,
Assume Blackfin Processor ADSP- BF-533, operating at 400 MHz and
1.14V
IDD-TYP = 125 mA [7]
1. Total No of Cycles, X = 34347002
2. Frequency, fCCLK = 400 MHz
3. Y = Total No of Cycles * (1/Frequency)
Y = 34347002 * (1/400e6)
= 0.08
32
4. Z = VDD-INT * IDD-TYP
= 1.14 * 125mA
= 0.1425
5. Power = 0.08 * 0.1425
= 0.0114 W
Table 15 gives the power output values for ADSP- BF-533 operating at 400 MHz
and 1.14 V.
Total No of Cycles 34347002
Frequency f 400 MHz
No of Cycles * 1/f 0.08
Table 15 Power Consumption at 400 MHz & 1.14 V
Processor VDD-INT (V) IDD-TYP (mA) VDD-INT * IDD-TYP Power (W)
BF533 1.14 125 0.1425 0.0114
This indicates that the power consumed per pixel = 66.04 nW
Table 16 gives the power output values for ADSP- BF-533 operating at 500 MHz
and 1.2 V.
Total No of Cycles 34347002
Frequency f 500 MHz
No of Cycles * 1/f 0.06
Table 16 Power Consumption at 500 MHz & 1.2 V
Processor VDD-INT (V) IDD-TYP (mA) VDD-INT * IDD-TYP Power (W)
BF533 1.2 190 0.228 0.01368
This indicates that the power consumed per pixel = 79.25 nW
33
Table 17 gives the power output values for ADSP- BF-533 operating at 533 MHz
and 1.2 V.
Total No of Cycles 34347002
Frequency f 533 MHz
No of Cycles * 1/f 0.06
Table 17 Power Consumption at 533MHz & 1.2 V
Processor VDD-INT (V) IDD-TYP (mA) VDD-INT * IDD-TYP Power (W)
BF533 1.2 200 0.24 0.0144
This indicates that the power consumed per pixel = 83.43 nW
6.3 Power Consumption of DCT algorithm by ADSP-
BF-533
Paper [18] presents a quantitative comparison between the energy costs
associated with direct transmission of the uncompressed images and the
transmission of the JPEG compressed image data.
The main steps of JPEG compression are illustrated in Figure 10. The
original image is in RGB format, which is converted into YCbCr (similar to
YUV) format where Y is luminance component and Cb and Cr are chrominance
components. Three images were chosen, which are then tiled into sections of
8x8 blocks and processed separately which is mentioned below.
Figure 10 The JPEG Compression Algorithm [18]
Each tile is level shifted to zero mean: e.g. for a pixel depth of 8 bits, 128
would be subtracted from each pixel to bring the range to {-128,127}.
Performing a 1D DCT on rows followed by 1D DCT on columns one can
covert the level shifted blocks into frequency space by using/ performing 2D
DCT. Next quantization is performed on block by dividing each sample by a
34
quantization step size which is defined in quantization Table 18 [18], and
rounding the result of division to nearest integer value. The standard
quantization table T [18] specified in the JPEG standard for luminance is given
by
Table 18 Quantization Table T [18]
The values in the table corresponds to low frequency components of upper
left which are smaller than those corresponding to high frequency components
of lower right, resulting that low frequency components will be retained more
accurately than high frequency components. All values in table are rescaled in
inverse proportion to a quality setting Qtab which ranges from 1(very poor
quality) to 100 (very good quality), with a constant of proportionality Qtab = 50
indicates no rescaling of the table. The final step is entropy coding, a lossless
compression process involving run-length encoding and Huffman coding.
Table 6 in [18], shows a comparison between various processor for
performing DCT and quantization on a single 8 X 8 block on their proposed
“fast” method on an original image of size 128 X 128.
It can be seen from Table 6 of [18], that ADSP – BF 533 operating at 0.8 V
and 100 MHz of Clock Speed gives an active power of 24 mW and when
ADSP- BF 533 operates at 1.4 V and 756 MHz Clock Speed gives an active
power of 644 mW.
35
6.4 Results
Table 19 shows a comparison of power consumed per pixel by the
suggested system and other system given in [18] for ADSP – BF – 533
processor.
Table 19 Comparison - Power Consumed by Suggested System and Other System
Algorithm Voltage (V) Frequency
(MHz)
Power
Consumed/Pixel
2D- DPCM
1.14 400 74.3 nW
1.2 500 92.4 nW
1.2 533 97.3 nW
DCT 0.8 100 1.46 µW
1.4 756 39.3 µW
From Table 19, It can be noted that the suggested system consumes less
power when compared to the other systems.
36
7 CONCLUSION AND FUTURE WORK
This thesis work deals with video capture and compression of CE; and, to
integrate signal capture from the sensor with compression algorithms in order
to avoid excessive storage and read/write operations. Various compression
algorithms like Discrete Cosine Transformation (DCT), DPCM are studied and
2D-DPCM is chosen for further research. The chosen compression algorithms
must be simple to minimize additions and multiplications.
We have applied DPCM for video compression and have chosen PPM as
transmission scheme. In addition, processing schemes like entropy coding and
error correction codes are added in order to enhance the performance.
Complexity of the algorithm is drawn from the code which is presented in
Tables 4 - 14.
Blackfin processor ADSP – BF – 533 is chosen as the target processor and
the power consumption is calculated for the developed system. The power
consumption results are presented in Table 15 - 17.
Power consumption of the suggested system is compared with the other
systems and the results are presented in Table 19. It can also be noted from
Table 19 that the power consumed/pixel increases when the operating
frequency is increased. By comparing the two systems it can be conclude that
the suggested algorithm consumes less power.
The code optimization can be performed to get better results i.e we can still
decrease the number of adders and multipliers.
37
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