www.elsevier.com/locate/mee

Microelectronic Engineering 73–74 (2004) 730–735

Processing issues in silicon nanocrystal manufacturing byultra-low-energy ion-beam-synthesis for non-volatile

memory applications

P. Normand a,*, P. Dimitrakis a, E. Kapetanakis a, D. Skarlatos a, K. Beltsios b,D. Tsoukalas c, C. Bonafos d, H. Coffin d, G. Benassayag d, A. Claverie d,

V. Soncini e, A. Agarwal f, Ch. Sohl f, M. Ameen f

a IMEL NCSR Demokritos, 15310 Aghia Paraskevi, Greeceb Department of Materials Science and Engineering, University of Ioannina, Greece

c Faculty of Appl. Mathem. and Phys. Sc., NTUA, 15780 Athens, Greeced CEMES/CNRS, 29 rue Jeanne Marvig, BP 4347, 31055 Toulouse Cedex 4, France

e ST Central R&D Agrate, Via Olivetti 2, 20041 Agrate, Brianza, Italyf Axcelis Technologies Inc., 55 Cherry Hill Drive, Beverly, MA 01915, USA

Available online 19 March 2004

Abstract

Recent fabrication issues encountered during the synthesis of silicon nanocrystals in thin SiO2 films by the technique

of ultra-low energy ion implantation and subsequent thermal treatment (ULE-IBS) are presented. The effects of charge

neutralization of the implanted species, energy contamination and post-implantation cleaning process on the electrical

and structural properties of the processed oxides are described, with emphasis upon the technological options to control

them. While much research is still required for industrial exploitation of ULE-IBS in the fabrication of competitive and

reproducible memory structures, promising results for prototype devices aiming at low-voltage non-volatile memory

applications have been obtained and are here reported.

� 2004 Elsevier B.V. All rights reserved.

Keywords: Silicon nanocrystals; Ion beam synthesis; Silicon implantation; Nanocrystal memory; Non-volatile memory

* Corresponding author. Tel.: +301-650-3115; fax: +301-651-

1723.

E-mail address: p.normand@imel.demokritos.gr (P. Nor-

mand).

0167-9317/$ - see front matter � 2004 Elsevier B.V. All rights reserv

doi:10.1016/j.mee.2004.03.043

1. Introduction

To overcome the limitations of current memory

technologies several fabrication routes are being

actively investigated. A promising alternative for

low-cost ultra-dense low-power and fast write/

erase data storage lies in the use of single-transis-

tor memory-cell structures where the charge

ed.

P. Normand et al. / Microelectronic Engineering 73–74 (2004) 730–735 731

storage medium is composed of mutually isolated

nanocrystals in place of the continuous polysilicon

layer used in conventional floating-gate memory

devices. As the optimum mean size of the storage

dots lies below the current lithography resolution,

an attractive approach for the fabrication ofnanocrystal islands is through a self-assembling

process. Among the different processing routes

explored during the last few years the ion beam

synthesis (IBS) technique has received substantial

attention because of its flexibility and its manu-

facturing advantages [1].

The potential of IBS for nanocrystals memory

applications has been recently enhanced throughthe synthesis in the ultra-low-energy (ULE) regime

(typically 1 keV) of single silicon nanocrystals

layers in thin SiO2 films [2–5]. In terms of struc-

tural possibilities, a combination of ULE-IBS

conditions and oxide thickness allows for the for-

mation of Si nanocrystals at a location from the

SiO2/Si interface that can be tailored for DRAM-

like or EEPROM-like memory applications [5,6].However, despite these attractive technological

options, many fabrication issues remain to be

solved before establishing a reliable process lead-

ing to competitive memory devices. Some perti-

nent issues will be hereafter outlined with emphasis

on our recent research developments. Finally,

electrical properties of silicon-nanocrystal nMOS

transistors aiming at low-voltage non-volatilememory applications will be presented.

2. Processing concerns

The widespread idea that (ULE-) IBS is a sim-

pler and, hence, preferable technique compared to

the painstaking multi-step deposition ones is basedmainly on considerations being restricted to four

processing conditions: implantation dose and en-

ergy, and annealing temperature and time. In fact,

a much wider range of parameters has to be con-

sidered for obtaining structures reproducible from

a fabrication site to another and successfully using

the IBS technique. Although we have recently

tackled some of these parameters in the case offabricating silicon nanocrystals in thin SiO2 films

by ULE-IBS, many aspects discussed hereafter

apply to other implanted and host materials. Sig-

nificant issues (e.g. boron contamination [6] and

oxide swelling [2,4,6]) and alternative processing

options (e.g. annealing in N2/O2 for implantation

damage recovery [7]) for high-dose ULE silicon

implants are reported elsewhere. The effects ofcharge neutralization and energy contamination in

the ULE regime, as well as the influence of the

cleaning process on the electrical and structural

characteristics of high-dose silicon-implanted-SiO2

layers are here reviewed.

During ion implantation in insulators, charge

build-up on the wafer surface can occur and can

affect substantially the uniformity and level of theimplanted dose. Also, charge accumulation will

develop a potential between the insulator surface

and the substrate that ultimately can lead to

breakdowns [8]. Even well-below catastrophic

breakdowns, such a potential will induce a current

through the insulator that can seriously affect the

integrity of the insulator and, possibly, the distri-

bution of the implanted species as well. To avoidcharge build-up on the wafer surface and charging-

related insulator damage, modern high-current ion

implanters make use of a charge neutralization

system supplying low-energy electrons near the

wafer surface [8,9]. The effect of charge neutral-

ization on the electrical properties of 10 nm-thick

SiO2 layers grown on p-type silicon wafers im-

planted with 1 keV Si atoms to a dose of 1016 cm�2

with and without the use of a plasma electron

flood has been examined through electrical inves-

tigations of MOS capacitors. I–V measurements

performed on annealed samples reveal higher

leakage currents in both accumulation and inver-

sion regimes for ion implanted samples. Also, the

charge state effect of implanted silicon strongly

affects the charge storage properties of the oxidesas detected through high-frequency C–V mea-

surements. The flat-band voltage shift versus the

applied electric field of samples annealed after

deposition of a 15 nm-thick oxide is shown in

Fig. 1. Charge injection initiates at electric fields

lower than 4 MV/cm and around of 7 MV/cm for

oxides implanted without and with charge neu-

tralization, respectively. Taking into accountthe physical thickness (ca. 7.5 nm) of the part

of the oxide (referred as tunnel oxide) underlying

Fig. 1. Flat-band voltage shifts (DVFB) versus the applied

electric field for 10 nm-thick oxide layers implanted at room

temperature with 1 keV Siþ to a dose of 1� 1016 cm�2 using

a 8:1 keV (S1) or 5:1 keV (S2, S3) deceleration regime. A

plasma electron flood for charge neutralization was used

for S3 implant. S2 and S3 implants were carried out in the

same ion implanter. Subsequent annealing was performed at

950 �C for 30 min in N2 after deposition of a 15 nm-thick

oxide layer. Inset: Typical normalized high-frequency C–V

curves for a +8/)8/+8 V gate voltage round sweep of the S1

sample.

732 P. Normand et al. / Microelectronic Engineering 73–74 (2004) 730–735

the nanocrystal layer, the above clearly indicatesthat the tunnel oxide is more degraded in the case

of oxides implanted with silicon ions without

charge neutralization.

Another important process issue relates to en-

ergy contamination that occurs during ion im-

plantation at very low energies (ca. 6 1 keV). The

main source of energy contamination in ULE ion

implanters arises from collision of the ions withresidual gas molecules within the deceleration

column [9,10]. Such collisions generate neutral

atoms that reach the wafer surface with an energy

dispersed between the pre-deceleration energy and

the targeted energy. This energy contamination

phenomenon can affect significantly the tail of the

implant profile distribution and have severe con-

sequences on the electrical properties of the pro-cessed structures. The latter point is illustrated in

Fig. 1 for 10 nm-thick oxides implanted with 1 keV

Si ions using a pre-deceleration energy of 8 or

5 keV; the two cases will be hereafter denoted as

8:1 and 5:1 keV deceleration regimes, respectively.

Charge injection at lower electric fields and en-

hanced charge storage occur for oxides implanted

through an 8:1 keV deceleration regime. Although

transmission electron microscopy (TEM) exami-

nation reveals no significant structural changes

between the samples after annealing [6], amorph-

ization of the substrate was detected for the 8:1

keV-implanted samples before annealing. The lat-ter finding supports the idea of an enhanced tail

distribution of the 8:1 keV implant profile result-

ing to enhanced excess silicon in the tunnel oxide

underlying the nanocrystal layer that forms upon

annealing. An increased excess of silicon atoms

will enhance the conductivity of the tunnel oxide,

thus decreasing the applied electric field required

for effective charging of the nanocrystals. Thisexcess of silicon atoms may also act as effective

charge centers and contribute significantly to the

charge-trapping phenomena observed at very low

electric fields in nanocrystal memory structures

obtained by ULE-IBS [11].

The last technological concern herein discussed

relates to the wafer cleaning process used prior to

high-temperature treatments of high-dose silicon-implanted-SiO2 layers. The most common process

makes use of the RCA cleaning procedure [12] that

involves two sequential chemical solutions, a

mixture of NH4OH:H2O2:H2O (SC1) and a mix-

ture of HCl:H2O2:H2O (SC2). Standard RCA

process can become inappropriate when used for

oxide cleaning since SC1 solution dissolves SiO2 at

a rate that increases with NH4OH concentrationand bath temperature [12]. In the case of high-dose

Si implanted oxides the situation can become cat-

astrophic even when megasonic cleaning with di-

luted SC1 solutions (e.g. 1:1–2:50–100) at low

temperatures is used [6]. The effect of cleaning

using diluted SC1 (1:2:100, 70 �C, 5 min) and SC2

(1:1:50, 70 �C, 5 min) solutions on the memory

window of 7 nm-thick oxides implanted with 1 keVSiþ to a dose of 2� 1016 ions/cm2 and subsequently

annealed at 950 �C for 30 min in N2/O2 ambient is

shown in Fig. 2. Comparison is made with samples

implanted under the same conditions and subse-

quently annealed without any cleaning (NC) or

following a piranha cleaning (H2SO4:H2O2, 1:1,

SPM, 130 �C, 15 min), or after a single SC2

cleaning (1:1:50, 70 �C, 5 min). As depicted inFig. 2, the sequential treatment of SC1 and SC2

solutions affects significantly the charge storage

Fig. 2. Flat-band voltage shift as a function of the gate voltage

round sweep for 7 nm-thick oxides implanted at room tem-

perature with 1 keV Siþ (5:1 keV decel. regime) to a dose of

2� 1016 ions/cm2 and subsequently annealed at 950 �C for 30

min in N2/O2 without cleaning or after SPM, SC1/SC2, or SC2

cleaning treatments. An oxide thickness of about 1.5 nm was

etched away (right TEM picture) for samples cleaned following

the SC1/SC2 sequence as compared with the uncleaned sample

(left TEM picture). TEM examination was performed before

annealing. An amorphous silicon layer was deposited at room

temperature on the top of the samples for TEM observation

purposes.

P. Normand et al. / Microelectronic Engineering 73–74 (2004) 730–735 733

efficiency of the oxides and, thus, leads to reducedattainable memory windows compared to the non-

cleaned or SPM or SC2 cleaned samples. TEM

examination of samples after implantation and

cleaning reveals that a thickness of about 1.5 nm

was etched away in the case of SC1/SC2 cleaning

samples (see Fig. 2). The above strongly indicates

that the SC1 solution should be dropped or re-

placed by another solution to avoid any degrada-tion of high-dose implanted oxides.

3. Device fabrication and performance

In the remaining part of this paper, exploratory

silicon nanocrystal MOSFETs obtained by the

ULE-IBS technique are reported briefly. The fab-rication process was similar to that of conven-

tional nMOS transistors except for the additional

steps related to the formation of nanocrystals. For

this purpose, a 7 nm-thick gate oxide was im-

planted at room temperature with 1 keV Si ions to

a dose of 2� 1016 cm�2. Implantation was carried-

out through a 5:1 keV deceleration regime and

charge neutralization conditions in an Axcelis

GSD-implanter. Subsequently, thermal annealing

was performed at 950 �C for 30 min in N2/O2

ambient after an SPM cleaning treatment. Then, a

poly-silicon layer was deposited and etched toform the gate electrode. Formation of the source

and drain regions was achieved through ion im-

plantation and annealing at 900 �C for 20 min in

N2. From TEM examination of samples with 7

nm-thick oxides implanted and annealed (950 �C/30 min in N2/O2) under the same conditions, the

thickness of the tunnel (TO) and control (CO)

oxides and Si-nanocrystal (Si-nc) layer for thepresent devices is estimated to be ca. 6.5, 5 and 2.5

nm, respectively. It should be noted that process-

ing including Si implantation and annealing in N2/

O2 enhances significantly the thickness of the gate

oxide. Parameters contributing to the swelling of

the oxide, as well as experimental findings ob-

tained through structural and electrical analyses of

low-energy Si-implanted SiO2 layers are reportedin [6]. While oxide swelling, and in particular the

expansion of the tunnel oxide, is a complex phe-

nomenon and constitutes an important point of

technological concern regarding the use of the

ULE-IBS technique, our work shows that swelling

is reproducible and depends mainly on the im-

planted dose.

Typical transfer (ID–VG) and output (ID–VD)characteristics of the devices are shown in Fig. 3.

Application of symmetric +9/)9 V programming

pulses of 10 ms width leads to a threshold voltage

(defined at IDS ¼ðW =LÞ � 10 nA) window of

about 1.9 V. Electron and hole injection from the

substrate to the oxide occur for positive and neg-

ative pulse voltages, respectively. The subthresh-

old swing of these devices was estimated to be 115mV/decade. The memory windows attainable after

application of symmetric negative (NP) and posi-

tive (PP) programming pulses of different length

and width are shown in Fig. 4. The endurance of

the devices was tested for a 10 ms +9/)9 V

programming regime. Neither degradation nor

drift in memory window was detected after 106

PP/NP cycles (see inset of Fig. 4). The chargeretention characteristics of the devices at room

temperature, 85 and 115 �C after 106 10 ms +9/)9 V

Fig. 5. Charge retention characteristics at room temperature

(RT), 85 and 115 �C after 106 10 ms +9/)9 V PP/NP cycles.

Fig. 3. ID–VG and ID–VD (inset) characteristics of nMOS

transistors with a 7 nm-thick oxide layers implanted with 1 keV

Si atoms to a dose of 2� 1016 ions/cm2 and subsequently an-

nealed at 950 �C for 30 min in N2/O2. The unstressed curve is

obtained by sweeping the gate voltage from +2 to )2 V and

back to +2 V. ID–VG measurements for the 10 ms/+9 V (PP) or

10 ms/)9 V (NP) programming state are carried out after a

sequence of 3 PP/NP pulses and a waiting time of 5 s.

Fig. 4. Threshold voltage versus positive and negative pro-

gramming (PP/NP) pulse voltage characteristics for different

pulse durations. Measurements for both the PP and NP states

were performed following the procedure described in Fig. 3.

Inset: Endurance characteristics tested with +9/)9 V PP/NP

pulses of 10 ms width. No degradation occurs after 106 PP/NP

cycles.

734 P. Normand et al. / Microelectronic Engineering 73–74 (2004) 730–735

programming cycles are shown in Fig. 5. Memorywindows of about 1.3 and 1.2 V are detected

after 4.5 h at 85 and 115 �C, respectively. Longtime extrapolation indicates a 10-year memory

window of about 0.4 V at 85 �C. Finally, it is

pointed-out that the above characteristics obtained

throughout the measurements performed so far

suggest that the devices reported here are well-

suited for application to low-voltage EEPROMs.

4. Conclusions

Recent developments of the ULE-IBS tech-

nique for fabricating silicon nanocrystals in thin

SiO2 films were presented. Particular attention was

placed on concerns associated with the steps of

implantation and post-implantation cleaning that

might strongly affect the electrical properties of the

processed structures. Advances in fabrication al-

low for overcoming several technological issuesand exploit ULE-IBS to built new improved

memory structures as demonstrated in the case of

prototype devices aiming at low-voltage non-vol-

atile memory applications.

Acknowledgements

This work was a part of the NEON project

and was funded by the EC as GROWTH GRD1-

2000-25619.

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