Nanocrystal Floating Gate MOSFET Nonvolatile …zyang/Teaching/20192020FallECE...Nanocrystal Floating Gate MOSFET Nonvolatile Memory Zheng Yang ECE440 Nanoelectronics RAM （Random

Nanocrystal Floating Gate MOSFET Nonvolatile Memory

Zheng Yang

ECE440 Nanoelectronics

RAM （Random Access Memory）

ROM（Read- Only Memory）

Fundamentals of Memories

Nonvolatile

Volatile

Volatile memory vs Nonvolatile memory

RAM vs ROM (2 most widely used memory)

Different kinds of memory devicesROM/RAM; Hard Drive; Floppy/Tape; CDROM/DVD/Blu-ray;

Flash/Memory-card/Solid-state hard drive; MRAM; FeRAM

International Technology Roadmap for Semiconductors (ITRS)—Memory

Traditional MOSFET

n+ n+

Source

p

Drain

Gate

Silicon dioxide

Traditional Floating Gate (FG) MOSFETI D

VGVT VTProgrammedInitial

Initial

Programmed

n+ n+Source

pDrain

GatePoly FG

Pulse Generator

Agilent 4155C

VD

D

SG

• Control oxide

• Floating gate

• Tunnel oxide

Control oxide

Tunnel oxide

Limitations of Traditional FGs

Direct tunneling distance in SiO2 ~ 3.5 nm

Retention leakage occurs through traps: trap-assisted-tunneling

A minimum tunnel oxide thickness is ~ 7 nm.

FG Substrate3.5nm 3.5nm

Thinner: One weak point will drain out all charge in FG; Bad Retention

Thicker: Slower Programming/Erasing

Polysilicon Charge Storage

Defect density of tunnel oxide is critical. Source Drain

Control Gate

Substrate

Charges are mobile

~100ÅTunnelOxide

Leakage path

Traditional vs Nanocrystal FGs

Enables thinner oxide

Poly-Si Charge Storage

S D

Control Gate

Substrate

Charges are mobile

~10nmOxide

Leakage path

S D

Poly Gate

Substrate

3-4 nm Oxide

5-9 nm OxideNanocrystal

NCs

Even one conducting point can drain out all

charges in floating gate

Separate charging nodes enhances the retention

time

Thinner Tox:

• Low voltage, More reliable; Denser, Faster

Developers and Vendors of NC FG MOSFET flash memory

-- Atmel and CEA-LETI-- Freescale-- IBM-- Micron Technology-- NEC-- Numonyx-- ST Microelectronics-- Samsung-- Toshiba

Current status of NC memories

• New technologies on NC memory-- High-K blocking oxide

-- Al2O3 for 3-D self-assembled NC memory (U. of Texas)-- Integrated array of Si NC memory using HfAlOx interpoly Dielectric (CEA-LETI)-- Multi-gate FET with Al2O3 blocking dielectric and TiN NC (Nat. Chiao Tung U.)

-- Tunnel oxide engineering-- Variable oxide engineering for NC memories (U. of Texas)

-- Alternative NCs-- Ge/Si hetero-NC for improved data retention (U. of Calif., Riverside)-- Co/high-k core-shell NCs for improved data retention (U. of Calif., Riverside)-- Silicide-based NCs for nonvolatile memories (U. of Calif. Riverside)-- Ge NC in tri-layer gate stack memory (Nat. Univ. of Singapore)-- Pt NC in double layer configuration (Applied Materials, IIT)-- TiN NC laminated with Al2O3 (Chang Gung Univ.)-- Reliability and performance of devices with W NC (IIT)

Nanocrystal Flash Memory Technology & Development, June 2011

Current status of NC memories (cont’)• New Technologies on NC Memory (cont’)

-- Multi-layer NC Gates-- Double layer stacked heterometal NC of Ni/Au (KAIST)-- Double gate and tri-gate FinFET Si-NC 10nm memories (CEA-LETI)-- Tri-gate FinFlash SN memory (CEA-LETI)

-- Using NC to Improve SONOS Memory-- Embedding self-assembled Si NC in storage nitride (Macronix)-- SONOS memory with Si NC layer between double tunnel oxide (Toshiba)-- Nano-trap memory using Ti additives (NEC)-- Nano-trap memory using negative conduction band offset materials (Samsung)

-- Vertical Structures for Nanocrystal Memories-- Gate-All-Around vertical NC flash cell (U. of Texas, Austin)-- Improving the P/E window using a NC FinFET (Sungkyunkwan U.)-- Vertical flash memory with SiGe NCs grown on a pillar (U. of Texas)

Nanocrystal Flash Memory Technology & Development, June 2011

Proposal of silicide NC memory

Simulations

High density of state provides large storage capability, fast operation speed

Lower energy level in NC region provides longer retention performance

Process

Better thermal stability

Lower diffusion compared with metal

Compatible with Si technology

TiSi2 NC FG MOSFET Flash Memory

3D conduction band of Si NC and Ti silicide NC memory device

The energy level in Ti silicide NC is lower than the one in Si NC, electrons are difficult to be lost.

H. Zhou, B. Li, Z. Yang, N. Zhan, D. Yan, R. K. Lake, and J. Liu, IEEE Trans. Nanotechnol., 10, 499 (2011).

Fig. Schematic of TiSi2 NC memory device fabrication process

Device fabrication for TiSi2 NC memory


TiSi2 NC formation

One evident peak at ~460eV corresponding to Ti 2P3/2 states of TiSi2

Dome shapes in TEM image

Fig. AFM images for Si NCs a) and b) Ti silicide NCs

Fig. TEM images for TiSi2 NCs

480 475 470 465 460 455 4500.0

4.0x103

8.0x103

1.2x104

1.6x104

2.0x104

2.4x104

Cou

nts (

Arb

. Uni

t)

Binding Energy (eV)

Ti 2p 3/2

Ti 2p 1/2

TiSi2 nanocrystals

Fig. XPS spectron for TiSi2 NCs


Memory window for capacitors

-20 -15 -10 -5 0 5 10 15 20-0.2

0.0

0.2

0.4

0.6

0.8

1.0

1.2 (a)

3.1V

N

orm

aliz

ed C

apac

itor

Gate Voltage (V)

Refrence sample Si nanocrystal memory TiSi2 nanocrystal memory

1.1V

-20 -15 -10 -5 0 5 10 15 20

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

1.2

Nor

mal

ized

Cap

acito

r

Voltage (V)

Sweep from -10~10V Sweep from -12~12V Sweep from -15~15V

(b)

Fig. (a) Capacitor-Voltage (C-V) sweep measurement for the TiSi2 NC MOS memory and Si NC MOS memory capacitor, (b) C-V hysteresis of TiSi2 NC MOS memory capacitor after sweeps between 10V (-10V), 12V (-12V) and 15V (-15V)

TiSi2 NC memory shows stronger memory effects. ~3.1V and ~1.1V shift in TiSi2 and Si NC memory. Wider voltage sweep range leads to the fact that more electrons are written/erased from the TiSi2 NCs


Memory effect from TiSi2 NC memory device

Memory effect was clearly found

After writing, the shift of Ids-Vg curve indicates the electron storage in the floating gate.

Fig. Memory effect from a Ti silicide NC memory cell

-1 0 1 2 3 4 5 6 7 810-10

10-9

10-8

10-7

10-6

10-5

Dra

in C

urre

nt (A

)

Gate Voltage (V)

Nutral Writing

with 15V, 100ms


Writing performance for TiSi2 NC memory device

10-7 10-6 10-5 10-4 10-3 10-2 10-1 100 101

0.0

0.3

0.6

0.9

1.2

1.5

1.8

Vth

(V)

Writing time(Seconds)

TiSi2 nanocrystal Si nanocrystal

(a)

Higher saturation ΔVth Metallic NCs High DOS indicates more

charge storage Faster writing speed

Fig. Threshold voltage shift as a function of writing time for memory cells with TiSi2 NCs and reference Si NCs, respectively.

8 10 12 14 16 18 200.0

0.5

1.0

1.5

2.0

Vth

(V)

Writing Voltage (V)

TiSi2 nanocrystals Si nanocrystals

Writing time: 100ms

(b)

Direct tunneling. F~N tunneling when

increasing the writing voltage Increase further (>16 V), the

device becomes saturation.

Fig. Threshold voltage shift as a function of writing voltage for memory cells with TiSi2 NCs and reference Si NCs, respectively.


Erasing performance for TiSi2 NC memory device

Higher saturation window

High DOS in the TiSi2NCs and more charges are stored

Faster erasing speedFig. Threshold voltage shift as a function of erasing time for memory cells with TiSi2 NCs and reference Si NCs.

10-7 10-6 10-5 10-4 10-3 10-2 10-1 100 101

-1.5

-1.2

-0.9

-0.6

-0.3

0.0

TiSi2 nanocrystals Si nanocrystals

Vth

(V)

Erasing time(Seconds)


Retention performance for TiSi2 NC memory device

Slower charge lose rate – Lower conduction

band energy levels – difficult to go through

the tunneling oxide layer

Longer retention timeFig. Comparison of retention performance between reference Si NC and TiSi2 NC memory devices. The writing was done at 20 V for 1s.

100 101 102 103 104 105 106 107 1080.0

0.2

0.4

0.6

0.8

1.0

V

th S

hift

Rat

io (

Vth

(t)/

Vth

(0))

Waiting time (Seconds)



Energy band in writing case

0 20 40 60 80 100 120 140

-20

-15

-10

-5

0

5

Nanocrystal

Control Oxide

Z Dimention (nm)

Si nanocrystal TiSi2 nanocrystal

Writing

Ener

gy B

and

(eV

)

Si Substrate

Tunneling Oxide

Well distribution changes when applying voltage

Ec in tunnel oxide region is changed to a triangle shape – Easier F~N tunneling

Some voltages are dropped on the Si NCs

No voltage are dropped on the TiSi2 NCs– Metallic material– The angle of the triangle in the

tunneling oxide layer sharper

Faster writing speed

Fig. The edge of the conduction energy band for TiSi2 and Si NC samples in writing case


Energy band in erasing case

0 20 40 60 80 100 120 140

0

5

10

15

20

25

Control Oxide

Nanocrystal

Tunneling Oxide

Si Substrate

Si nanocrystal TiSi2 nanocrystal

Erasing

Z Dimention (nm)

Ener

gy B

and

(eV

)

Fig. The edge of the conduction energy band for TiSi2and Si NC samples in erasing case

Well distribution changes when applying voltage

Edge of EC in tunnel oxide region is changed to a triangle shape

Almost no voltage drop is applied on the TiSi2 NCs

Most of the erasing voltage is applied on oxide layer

Higher erasing speedH. Zhou, B. Li, Z. Yang, N. Zhan, D. Yan, R. K. Lake, and J. Liu, IEEE Trans. Nanotechnol., 10, 499 (2011).

W/E speed calculation

dEEFEEfETqJ )()()()( ( )f E( )E

)(EF( )T E

The impact frequencyThe 2-dimensional (2-D) density of states

The Fermi-Dirac distribution function

The tunneling probability

The time concept in a memory device can be defined as the inverse of the tunneling current density:

2LJq

The writing and erasing tunneling current densities are calculated:

Yan Zhu, Dengtao Zhao, and Jianlin Liu, J. Appl. Phys., Vol. 101, 034508, 2007B. J. Hinds, T. Yamanaka, and S. Oda, J. Appl. Phys., Vol. 90, pp. 6402-6408, 2001

W/E performance

10 12 14 16 18 2010-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3

10-2

10-1

Writ

ing

Tim

e (S

econ

ds)

Gate Voltage (V)


(a)

-27 -24 -21 -18 -15 -12 -910-7

10-6

10-5

10-4

10-3

10-2

10-1

100

Eras

ing

Tim

e (S

econ

ds)

Gate Voltage (V)


(b)

Programming/erasing speed increases with the gate voltage.As the gate voltage increases, the electric field in tunneling oxide increases, the electrons easier to go through the tunneling oxide. The electric field in tunneling oxide of TiSi2 NC memory is always larger than that in Si NC memory TiSi2 NC device shows faster W/E speed than Si NC device.

Fig. Simulated programming speed versus operation voltage. (a) writing time as a function of gate voltage, (b)erasing time as a function of gate voltage. The shift of conduction band between Si and SiO2 is set to be 3.1eV.


Retention performance

100 101 102 103 104 105 106 107 1080.0

0.2

0.4

0.6

0.8

1.0

TiSi2 SimulationTiSi2 Experiment Si Simulation Si ExperimentC

harg

e R

emai

ning

Rat

e

Time (Seconds)

Fig. Simulated retention performance of reference Si NC and TiSi2 NC memory. To match with experiment result,

)1exp(exp3

3 EqkTkT

qECJ t

The retention time of the charge storage is calculated by Poole-Frenkel effect

TiSi2 NCs store more electrons than Si NCs TiSi2 NC memory device shows slower charge loss rate and higher charge storage after 10 years, which is similar with the experiment result. The charge loss is slower due to the deeper well.More electrons left in the NCs after 10 years.


Reference/Further Reading

• S. Tiwari, F. Rana, K. Chan, L. Shi, and H. Hanafi, “Single charge and confinement effects in nano-crystal memories”, Appl. Phys. Lett. 69,1232 (1996).

• Huimei Zhou, Bei Li, Zheng Yang, Ning Zhan, Dong Yan, Roger K. Lake, and Jianlin Liu, “TiSi2 nanocrystal metal oxide semiconductor field effect transistor memory”, IEEE Trans. Nanotechnol., 10, 499 (2011)

• Huimei Zhou, James A. Dorman, Ya-Chuan Perng, Stephanie Gachot, Jian-Guo Zheng, Jane P. Chang and Jianlin Liu, “Memory characteristics of ordered Co/Al2O3 core-shell nanocrystal arrays assembled by di-block co-polymer process”, Appl. Phys. Lett., 98, 192107 (2011)

Documents

Nanocrystal Floating Gate MOSFET Nonvolatile …zyang/Teaching/20192020FallECE...Nanocrystal Floating Gate MOSFET Nonvolatile Memory Zheng Yang ECE440 Nanoelectronics RAM （Random