PowerBenchProgrammable Power Supply

Dror LazarMoran Fishman

Supervisor: Boaz Mizrahi

Winter Semester 2009/10

HS DSLHS DSL

Project Overview - Reminder

A versatile power supply unit with multiple outputs for laboratory use and testing of various electronic devices .

Active load

Power supply

Control unit

User interface for standalone operation

LCD KeysLEDs

User interface

DUT

Measurement unit

סססA brief reminder

Project Overview - Reminder

DC-DC

Converter

Post

regulator

ADC

ADC

Voltage Sense

DAC

Current Sense Output

FPGA

Controller

Block

&Registers

Output

setting

Input

voltage

sense

feed -

forward

Tempe-rature

Current

limit

PWM

Microprocessor

Overview – Control Scheme

ADC

AuxiliaryVoltage

Sense

Cypress FX2

USB Controller

USB

Cable

FPGA Design

PWMPWMCONTROLLER

PWMGENERATOR

DACINTERFACE

BUCK/CUKA/D

INTERFACE

SPI

SPI

IDDRs

DCMsODDRs

VOLTAGE SENSE DATA

Clocks, Buffers & Resets

DAC CONTROL

CURRENT SENSE DATA

PIC INTERFACE

CONTROL & STATUS

CHANNEL 1

CHANNEL 2

CHANNEL 3

CHANNEL 4

SPIINTERFACE

SPIDATA LINK

REGISTER BANK

FIFO BANK

GLUE LOGIC

CHANNEL 1

CHANNEL 2

CHANNEL 3

CHANNEL 4

BUCK/CUK A/D VOLTAGE

24 MHz

FPGA input Clock & reset

BUCK/CUK A/D CONTROL

DUTYCYCLE

SENSE A/Ds CONROL

SENSE A/Ds DDR DATA

CLOCKS

SPI BUSDATA

SPI 8-BITTRANSFER

CLOCKS & SYNC RESETS

REFERENCE INPUT

CYPRESS INTERFACE

CONTROL

BUFFERING FIFO

LOGIC

16-BIT DATA

CONTROL

ADDRESS

LEGENDDATA

CONTROL

CLOCKS & RESETS

DAC WORD

16-BIT DATA

Control Scheme

FPGA Control Infrastructure External Loop:

Determines VREF input for inner loop : LDO POWER (Pref) = (Vref – Vout) * Iout => VREF = Pref/Iout + Vout implemented using fixed LUT for Pref = 1W

LUT

Pref

Vout

Iout

Vref

FPGA Control Infrastructure Internal Loop:

Regulates DC-DC converter Implemented using Generic IIR FILTER : 1. Filter order and vectors width determined in FPGA parameter. 2. Filter coefficients determined by software

Enables control design in PC environment (MATLAB) and coefficient streaming to FPGA Control algorithm development without FPGA knowledge

Enables Same FPGA infrastructure for both DC-DCs : Buck & Cuk Converter

Implementing in FPGA: 1. Filter sample frequency is different from FPGA system frequency (much lower) 2. Sums of many vectors in one clock 2. Consecutive sums & multiples If IIR filter module is operating in sampling frequency: 1. Low frequency is difficult to create -> unwanted 2. Adds another time domain to the FPGA -> unwanted

Solution : 1. Avoiding direct implementation 2. Adding extra registers between calculative operations

Generic IIR Filter

Generic IIR Filter

++

-

++

-

++

+ -

b1

b2

b3a3

a2

a1

a0Y[n]X[n]

1z

1z

1z

Twelve 18x18 bit multipliers in FPGA Allows an order 2 IIR filter

System Modeling

PWM G(s)IIR

FILTERVoute+

-

A/D

Vref sTdePWMK

/A DK

Modeling the plant G(s) for buck & cuk converters in continues time

Translating the continues time model to discrete time model Determining required control characteristics: Steady state error, Overshoot, settling time Determining desired closed loop poles

System Modeling

Designing the IIR filter in MATLAB Simulating the system in Simulink Simulating the system in SPICE ?

Streaming (via USB) different sets of coefficients to FPGA from PC

measuring analog response with scope and comparing results

System Modeling

PC – FPGA communication

PIC software : SPI module (PIC – FPGA) PMP module (PIC – FX2) FPGA soft-reset module

FX2 software : PC enumeration (done by Greg) End-Points configuration Slave-FIFO configuration

Configure FPGA registers using PC : PC => FX2 => PIC => FPGA => PIC => FX2 => PC

FPGA Firmware UpdaterPC Firmware Updater:

FPGA Firmware UpdaterPC FX2 PIC FPGA

• Sending a vendor request to the FX2, setting an interrupt to the PIC

• Sending the data from the PC to the Cypress Bulk Endpoint

FPGA Firmware UpdaterPC FX2 PIC FPGA

• Real Time Operating System is running on the PIC. FX2 interrupt PIC Task activation

• Data transfer from the FX2 bulk endpoint to the PIC

FPGA Firmware UpdaterPC FX2 PIC FPGA

• Data transfer from the PIC to the FPGA’s SPI Flash.

• Flash FPGA Firmware download

Questions

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