Power ISA™ Version 3.0 B · 2070 Route 52, Bldg. 330 Hopewell Junction, NY 12533-6351 ... The Power ISA Version 3.0 B consists of three books and a set of appendices. Book I, Power

Power ISA™ Version 3.0 B

March 29, 2017

Version 3.0 B

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Preface

The roots of the Power ISA (Instruction Set Architec-ture) extend back over a quarter of a century, to IBMResearch. The POWER (Performance OptimizationWith Enhanced RISC) Architecture was introduced withthe RISC System/6000 product family in early 1990. In1991, Apple, IBM, and Motorola began the collabora-tion to evolve to the PowerPC Architecture, expandingthe architecture’s applicability. In 1997, Motorola andIBM began another collaboration, focused on optimiz-ing PowerPC for embedded systems, which producedBook E.

In 2006, Freescale and IBM collaborated on the cre-ation of the Power ISA Version 2.03, which representedthe reunification of the architecture by combiningBook E content with the more general purpose Pow-erPC Version 2.02. The resulting architecture includedenvironment-specific privileged architecture optimiza-tions (two Book IIIs) and optional application-specificfacilities (categories) as extensions to a pervasive basearchitecture.

Power ISA Version 3.0 B focuses this integration bychoosing a single Book III and a set of widely used cat-egories to become part of the base architecture for allforward-looking Power implementations. All otheroptional architecture categories have been eliminatedto ensure increased application portability betweenPower processors. Legacy embedded applications thatrequire the eliminated material will continue to use V.2.07B.

The Power ISA Version 3.0 B consists of three booksand a set of appendices.

Book I, Power ISA User Instruction Set Architecture,covers the base instruction set and related facilitiesavailable to the application programmer.

Book II, Power ISA Virtual Environment Architecture,defines the storage model and other instructions andfacilities that enable the application programmer to cre-ate multithreaded programs and programs that interactwith certain physical realities of the computing environ-ment.

Book III, Power ISA Operating Environment Architec-ture, defines the supervisor instructions and relatedfacilities.

As used in this document, the term “Power ISA” refersto the instructions and facilities described in Books I, II,and III.

Change bars have been included in the body of thisdocument to indicate changes from the Power ISA Ver-sion 2.07B. Change bars may be omitted for changesassociated with removing obsolete categories and thesecond Book III.

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Summary of Changes in Power ISA Version 3.0 BThis document is Version 3.0 B of the Power ISA. It isintended to supersede and replace version 2.07B. Anyproduct descriptions that reference a version of thearchitecture are understood to reference the latest ver-sion. This version was created by making miscella-neous corrections and by applying the followingrequests for change (RFCs) to Power ISA Version2.07B. Change bars in this summary of changes indi-cate new, changed, or removed changes relative to V.3.0.

Instruction Fusion: Specifies instruction sequencesthat, when placed consecutively in the program, areexpected to provide improved performance.

Hashing Support Operations: Adds new Count TrailingZeros and Modulo instructions

Decimal Integer Support Operations: Adds new BCDsupport instructions, including variable-length load/store instructions for bcd values, new format conver-sion instructions between BCD and National decimal,zoned decimal, and 128-bit signed integer formats. newBCDtruncate, round, and shift instructions, new BCDsign digit manipulation instructions. Also adds multi-ply-by-10 instructions to faciliate binary-to-decimal con-version for printf. Corrected functionality of DecimalShift and Round (bcdsr.) instruction.

Decimal Floating-Point Support Operations: Add imme-diate forms of DFP Test Significance instructions.

Binary Floating-Point Support Operations: Adds newbinary floating-point support instructions (e.g., expo-nent and significand extraction and insertion) toenhance implementation of math libraries.

Quad-Precision Binary Floating-Point Operations: Addnew instructions to support IEEE-754-2008 binary128floating-point.

String Operations (FXU option): Adds instructions toaccelerate character testing functions.

String Operations (VSU option): Adds instructions toaccelerate string processing and targeted characterextraction.

Vector Half-Precision Floating-Point Support Opera-tions: Adds support for IEEE-754-2008 binary16 float-ing-point as a transport format.

128-bit SIMD Video Compression Operations: Addsinstructions to accelerate motion estimation.

128-bit SIMD FXU Operations: Adds remaining 32-bitand 64-bit FXU functionality to vector instruction set.

128-bit SIMD Miscellaneous Operations: Enhancessupport for Little-Endian processing with new load/store instructions and new permute-class instructions,new byte and halfword element load/store instructions,and vector element insertion/extraction.

System Call Extension: Provides a new form of systemcall that can direct execution to one of a number oflocations and that provides other enhancements.

PC-Relative Addressing: Specifies a new instructionthat adds an immediate value to the program counterand writes it to the destination register in preparationfor use with a D-Form Load instructon.

Hypervisor msgsnd Instruction Enhancements:Extends the msgsnd instruction so that messages canbe sent throughout the system.

Performance Monitor Enhancements: Reserves a spe-cial no-op instruction for use by the Performance Moni-tor, and increases the scope of control of thePerformance Monitor bit of the Hypervisor Facility Sta-tus and Control register.

Radix Tree and Related MMU Extensions: Adds sup-port for the radix tree style of MMU with full virtualiza-tion and related control mechanisms that manage itscoexistence with the HPT. Also adds a tlbie variantthat invalidates multiple consecutive translations.

Copy-Paste Facility: Adds support for a new facility thatenables an application to initiate accelerator opera-tions.

Optimizing mtspr Sequences: Reserves an SPR to beused in a no-op mtspr to indicate the beginning of asequence of mtsprs that can be done without synchro-nizing each one independently.

Atomic Memory Operations: Adds support for a newfacility that performs simple atomic operations directlyin memory to avoid bringing the line through the cachehierarchy when another core is likely to be the nextuser.

Event-Based Branch Extension: Adds ExternalEvent-Based Branch exception and status bits to theBESCR.

Processor Compatibility Register: Adds a new V 2.07bit to the PCR that controls the availability facilities inproblem state that are introduced in this level of thearchitecture.

Atomicity and Alignment Enhancements: Limits thenumber of disjoint atomic storage accesses that areallowed for various non-atomic storage accesses.

Power-Saving Mode: Replaces the existing power-sav-ing mode instructions with a single stop instruction,and enables the operating system to enter a limited setof power-saving levels without hypervisor involvement.

D-form VSX Floating-Point Storage Access Instruc-tions: Adds base+displacement forms of VSR load andstore instructions.

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Integer Multiply-Add Instructions: Adds new integermultiply-add instructions to accelerate arbitrary-lengthmultiplication.

msgsndp Hypervisor Facility Availability Interrupt:Adds a new HFSCR bit to control the availability of themsgsndp instruction and the associated control regis-ters.

VSX Permute: Adds new pernute instructions that canaddress all 64 VSRs.

Array Index Support: Enhance support for mixed-data-type addressing into arrays (e.g., base + 32-bit index)

Hypervisor Virtualization Interrupt: Defines a newexception and corresponding interrupt that is causedby events external to the processor that relate to virtu-alization.

wait Instruction Enhancements: Improves the capabili-ties of the wait instruction so that resumption of pro-cessing can occur due to event-based branches andexternal signals.

Decrementer and Hypervisor Decrementer Enahnce-ments: Defines a new mode bit in the LPCR thatenables additional Decrementer and Hypervisor Decre-menter bits in order to increase the time between theassociated interrupts.

Deliver A Random Number: Adds a new instruction toplace a random number in a GPR in one of three for-mats.

Data Storage Interrupt Status Register for AlignmentInterrupt: Simplifies the Alignment interrupt by remov-ing the Data Storage Interrupt Status Register (DSISR)from the set of registers modified by the Alignmentinterrupt.

CA32 & OV32 and Move XER to CR Extended: Addedsupport for 32-bit CA & OV status in 64-bit mode fordynamically-typed languages.

VSX Shift Variable: Accelerate parallel elementextraction from packed vectors of arbitrary-width-ele-ment values.

Enhanced Virtualization for Linux: Delivers exceptionscaused by the OS attempting to use hypervisor instruc-tions and SPRs to the hypervisor instead of the OS.

Accesses to unimplemented SPRs by the OS newlycause interrupts that are also directed to the hypervisor.

Synchronizing Messages and Storage Updates: Adds anew instruction to make latent storage updates fromanother thread accessible after receiving a DirectedHypervisor Doorbell interrupt from that thread.

VSX Conditional: Adds new instruction toaccelerate conditional, maximum, and minimum opera-tions. Withdrew xscmpnedp, xvcmpnesp[.], and xvc-mpnedp[.] instructions introduced in v3.0.

FXU & Vector Extensions for Blockchain Support: Twonew instructions (addex and vmsumudm) introduced toaccelerate arbitrary-precision integer arithmetic, andspecifically to accelerate Blockchain’s implementationof elliptical curve encryption signature algorithm. TheOV bit is employed to provide an additional, indepen-dent carry status bit, allowing software to parallelizecarry propagation.

Miscellaneous Changes: Makes minor clarifications,corrections, and editorial enhancements.

FX/VSX/Vector Miscellaneous: Editorial cleanup ofBook I chapters 4, 5, and 7.

TM Multithread Overflow: Adds a bit to TEX-ASR to enable software to differentiate single threadfootprint overflow from that aggravated by multiplethreads competing for footprint.

Lightweight mffs: Modifications of mffs to acceleratesaving/setting/restoring floating-point environments(e.g., rounding modes, exception trapping enables)common in math libraries that require overriding theenvironment.

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Table of Contents

Preface. . . . . . . . . . . . . . . . . . . . . . . . . vSummary of Changes in Power ISA Ver-

sion 3.0 B . . . . . . . . . . . . . . . . . . . . . . . . vi

Table of Contents . . . . . . . . . . . . . . . . ix

Book I:

Power ISA User Instruction Set Architecture. . . . . . . . . . . . . . . . . . . . 1

Chapter 1. Introduction . . . . . . . . . . 31.1 Overview. . . . . . . . . . . . . . . . . . . . . . 31.2 Instruction Mnemonics and Operands31.3 Document Conventions . . . . . . . . . . 31.3.1 Definitions . . . . . . . . . . . . . . . . . . . 31.3.2 Notation . . . . . . . . . . . . . . . . . . . . . 41.3.3 Reserved Fields, Reserved Values,

and Reserved SPRs . . . . . . . . . . . . . . . . 51.3.4 Description of Instruction Operation 61.3.5 Phased-Out Facilities . . . . . . . . . . 81.4 Processor Overview . . . . . . . . . . . . . 91.5 Computation modes . . . . . . . . . . . . 101.6 Instruction Formats . . . . . . . . . . . . . 111.6.1 A-FORM . . . . . . . . . . . . . . . . . . . 121.6.2 B-FORM . . . . . . . . . . . . . . . . . . . 121.6.3 D-FORM . . . . . . . . . . . . . . . . . . . 121.6.4 DQ-FORM . . . . . . . . . . . . . . . . . . 121.6.5 DS-FORM . . . . . . . . . . . . . . . . . . 121.6.6 DX-FORM . . . . . . . . . . . . . . . . . . 121.6.7 I-FORM . . . . . . . . . . . . . . . . . . . . 121.6.8 M-FORM . . . . . . . . . . . . . . . . . . . 121.6.9 MD-FORM . . . . . . . . . . . . . . . . . . 121.6.10 MDS-FORM. . . . . . . . . . . . . . . . 121.6.11 SC-FORM . . . . . . . . . . . . . . . . . 121.6.12 VA-FORM . . . . . . . . . . . . . . . . . 121.6.13 VC-FORM . . . . . . . . . . . . . . . . . 121.6.14 VX-FORM . . . . . . . . . . . . . . . . . 131.6.15 X-FORM . . . . . . . . . . . . . . . . . . 131.6.16 XFL-FORM . . . . . . . . . . . . . . . . 151.6.17 XFX-FORM . . . . . . . . . . . . . . . . 151.6.18 XL-FORM . . . . . . . . . . . . . . . . . 15

1.6.19 XO-FORM . . . . . . . . . . . . . . . . . 151.6.20 XS-FORM. . . . . . . . . . . . . . . . . . 151.6.21 XX2-FORM. . . . . . . . . . . . . . . . . 151.6.22 XX3-FORM. . . . . . . . . . . . . . . . . 151.6.23 XX4-FORM. . . . . . . . . . . . . . . . . 151.6.24 Z22-FORM . . . . . . . . . . . . . . . . . 151.6.25 Z23-FORM . . . . . . . . . . . . . . . . . 161.7 Instruction Fields . . . . . . . . . . . . . . . 161.8 Classes of Instructions . . . . . . . . . . 221.8.1 Defined Instruction Class . . . . . . . 221.8.2 Illegal Instruction Class . . . . . . . . 221.8.3 Reserved Instruction Class . . . . . 221.9 Forms of Defined Instructions . . . . . 231.9.1 Preferred Instruction Forms . . . . . 231.9.2 Invalid Instruction Forms . . . . . . . 231.9.3 Reserved-no-op Instructions . . . . 231.10 Exceptions. . . . . . . . . . . . . . . . . . . 231.11 Storage Addressing . . . . . . . . . . . . 241.11.1 Storage Operands . . . . . . . . . . . 241.11.2 Instruction Fetches . . . . . . . . . . . 261.11.3 Effective Address Calculation . . . 27

Chapter 2. Branch Facility . . . . . . . 292.1 Branch Facility Overview. . . . . . . . . 292.2 Instruction Execution Order. . . . . . . 292.3 Branch Facility Registers . . . . . . . . 302.3.1 Condition Register . . . . . . . . . . . . 302.3.2 Link Register . . . . . . . . . . . . . . . . 322.3.3 Count Register . . . . . . . . . . . . . . . 322.3.4 Target Address Register. . . . . . . . 322.4 Branch Instructions . . . . . . . . . . . . . 332.5 Condition Register Instructions . . . . 402.5.1 Condition Register Logical Instruc-

tions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402.5.2 Condition Register Field Instruction .

412.6 System Call Instructions. . . . . . . . . 42

Chapter 3. Fixed-Point Facility. . . . 453.1 Fixed-Point Facility Overview . . . . . 453.2 Fixed-Point Facility Registers . . . . . 453.2.1 General Purpose Registers . . . . . 453.2.2 Fixed-Point Exception

Register . . . . . . . . . . . . . . . . . . . . . . . . . 453.2.3 VR Save Register. . . . . . . . . . . . . 463.3 Fixed-Point Facility Instructions . . . 47

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3.3.1 Fixed-Point Storage Access Instruc-tions . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

3.3.1.1 Storage Access Exceptions . . . .473.3.2 Fixed-Point Load Instructions . . . .473.3.2.1 64-bit Fixed-Point Load Instruc-

tions . . . . . . . . . . . . . . . . . . . . . . . . . . . .523.3.3 Fixed-Point Store Instructions . . . .543.3.3.1 64-bit Fixed-Point Store Instruc-

tions . . . . . . . . . . . . . . . . . . . . . . . . . . . .573.3.4 Fixed Point Load and Store Quad-

word Instructions . . . . . . . . . . . . . . . . . .583.3.5 Fixed-Point Load and Store with Byte

Reversal Instructions . . . . . . . . . . . . . . .603.3.5.1 64-Bit Load and Store with Byte

Reversal Instructions . . . . . . . . . . . . . . .613.3.6 Fixed-Point Load and Store Multiple

Instructions . . . . . . . . . . . . . . . . . . . . . . .623.3.7 Fixed-Point Move Assist Instructions

[Phased Out]. . . . . . . . . . . . . . . . . . . . . .633.3.8 Other Fixed-Point Instructions. . . .663.3.9 Fixed-Point Arithmetic Instructions 673.3.9.1 64-bit Fixed-Point Arithmetic

Instructions . . . . . . . . . . . . . . . . . . . . . . .793.3.10 Fixed-Point Compare Instructions. .

843.3.10.1 Character-Type Compare Instruc-

tions . . . . . . . . . . . . . . . . . . . . . . . . . . . .873.3.11 Fixed-Point Trap Instructions. . . .893.3.11.1 64-bit Fixed-Point Trap Instruc-

tions . . . . . . . . . . . . . . . . . . . . . . . . . . . .913.3.12 Fixed-Point Select . . . . . . . . . . . .913.3.13 Fixed-Point Logical Instructions .923.3.13.1 64-bit Fixed-Point Logical Instruc-

tions . . . . . . . . . . . . . . . . . . . . . . . . . . . .993.3.14 Fixed-Point Rotate and Shift

Instructions . . . . . . . . . . . . . . . . . . . . . .1013.3.14.1 Fixed-Point Rotate Instructions . .

1013.3.14.1.1 64-bit Fixed-Point Rotate

Instructions . . . . . . . . . . . . . . . . . . . . . .1043.3.14.2 Fixed-Point Shift Instructions .1073.3.14.2.1 64-bit Fixed-Point Shift Instruc-

tions . . . . . . . . . . . . . . . . . . . . . . . . . . .1093.3.15 Binary Coded Decimal (BCD)

Assist Instructions. . . . . . . . . . . . . . . . . 1113.3.16 Move To/From Vector-Scalar Regis-

ter Instructions . . . . . . . . . . . . . . . . . . . 1123.3.17 Move To/From System Register

Instructions . . . . . . . . . . . . . . . . . . . . . . 117

Chapter 4. Floating-Point Facility 1234.1 Floating-Point Facility Overview. . .1234.2 Floating-Point Facility Registers. . .1244.2.1 Floating-Point Registers . . . . . . .1244.2.2 Floating-Point Status and Control

Register . . . . . . . . . . . . . . . . . . . . . . . .124

4.3 Floating-Point Data. . . . . . . . . . . . 1274.3.1 Data Format. . . . . . . . . . . . . . . . 1274.3.2 Value Representation . . . . . . . . 1274.3.3 Sign of Result . . . . . . . . . . . . . . 1294.3.4 Normalization and

Denormalization . . . . . . . . . . . . . . . . . 1294.3.5 Data Handling and Precision . . . 1294.3.5.1 Single-Precision Operands. . . 1294.3.5.2 Integer-Valued Operands . . . . 1304.3.6 Rounding . . . . . . . . . . . . . . . . . . 1314.4 Floating-Point Exceptions. . . . . . . 1324.4.1 Invalid Operation Exception. . . . 1344.4.1.1 Definition. . . . . . . . . . . . . . . . . 1344.4.1.2 Action . . . . . . . . . . . . . . . . . . . 1344.4.2 Zero Divide Exception . . . . . . . . 1344.4.2.1 Definition. . . . . . . . . . . . . . . . . 1344.4.2.2 Action . . . . . . . . . . . . . . . . . . . 1354.4.3 Overflow Exception . . . . . . . . . . 1354.4.3.1 Definition. . . . . . . . . . . . . . . . . 1354.4.3.2 Action . . . . . . . . . . . . . . . . . . . 1354.4.4 Underflow Exception . . . . . . . . . 1364.4.4.1 Definition. . . . . . . . . . . . . . . . . 1364.4.4.2 Action . . . . . . . . . . . . . . . . . . . 1364.4.5 Inexact Exception . . . . . . . . . . . 1364.4.5.1 Definition. . . . . . . . . . . . . . . . . 1364.4.5.2 Action . . . . . . . . . . . . . . . . . . . 1364.5 Floating-Point Execution Models . 1374.5.1 Execution Model for IEEE Opera-

tions . . . . . . . . . . . . . . . . . . . . . . . . . . 1374.5.2 Execution Model for

Multiply-Add Type Instructions . . . . . . 1394.6 Floating-Point Facility Instructions 1404.6.1 Floating-Point Storage Access

Instructions . . . . . . . . . . . . . . . . . . . . . 1404.6.1.1 Storage Access Exceptions . . 1404.6.2 Floating-Point Load Instructions 1404.6.3 Floating-Point Store Instructions 1444.6.4 Floating-Point Load and Store Dou-

ble Pair Instructions [Phased-Out] . . . 1484.6.5 Floating-Point Move Instructions 1504.6.6 Floating-Point Arithmetic Instructions

1524.6.6.1 Floating-Point Elementary Arithme-

tic Instructions . . . . . . . . . . . . . . . . . . . 1524.6.6.2 Floating-Point Multiply-Add Instruc-

tions . . . . . . . . . . . . . . . . . . . . . . . . . . 1574.6.7 Floating-Point Rounding and Con-

version Instructions . . . . . . . . . . . . . . . 1594.6.7.1 Floating-Point Rounding Instruc-

tion . . . . . . . . . . . . . . . . . . . . . . . . . . . 1594.6.7.2 Floating-Point Convert To/From

Integer Instructions . . . . . . . . . . . . . . . 1594.6.7.3 Floating Round to Integer Instruc-

tions . . . . . . . . . . . . . . . . . . . . . . . . . . 1654.6.8 Floating-Point Compare Instructions

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4.6.9 Floating-Point Select Instruction 1684.6.10 Floating-Point Status and Control

Register Instructions . . . . . . . . . . . . . . 170

Chapter 5. Decimal Floating-Point . . 175

5.1 Decimal Floating-Point (DFP) Facility Overview . . . . . . . . . . . . . . . . . . . . . . . 175

5.2 DFP Register Handling . . . . . . . . . 1765.2.1 DFP Usage of Floating-Point Regis-

ters . . . . . . . . . . . . . . . . . . . . . . . . . . . 1765.3 DFP Support for Non-DFP Data Types

1785.4 DFP Number Representation . . . . 1795.4.1 DFP Data Format. . . . . . . . . . . . 1795.4.1.1 Fields Within the Data Format 1795.4.1.2 Summary of DFP Data Formats . .

1805.4.1.3 Preferred DPD Encoding . . . . 1815.4.2 Classes of DFP Data . . . . . . . . . 1815.5 DFP Execution Model . . . . . . . . . . 1825.5.1 Rounding . . . . . . . . . . . . . . . . . . 1825.5.2 Rounding Mode Specification . . 1835.5.3 Formation of Final Result. . . . . . 1835.5.3.1 Use of Ideal Exponent . . . . . . 1835.5.4 Arithmetic Operations . . . . . . . . 1845.5.4.1 Sign of Arithmetic Result . . . . 1845.5.5 Compare Operations . . . . . . . . . 1845.5.6 Test Operations . . . . . . . . . . . . . 1845.5.7 Quantum Adjustment Operations 1845.5.8 Conversion Operations . . . . . . . 1855.5.8.1 Data-Format Conversion . . . . 1855.5.8.2 Data-Type Conversion . . . . . . 1855.5.9 Format Operations. . . . . . . . . . . 1855.5.10 DFP Exceptions . . . . . . . . . . . . 1855.5.10.1 Invalid Operation Exception . 1875.5.10.2 Zero Divide Exception . . . . . 1885.5.10.3 Overflow Exception. . . . . . . . 1895.5.10.4 Underflow Exception. . . . . . . 1895.5.10.5 Inexact Exception . . . . . . . . . 1905.5.11 Summary of Normal Rounding And

Range Actions. . . . . . . . . . . . . . . . . . . 1915.6 DFP Instruction Descriptions . . . . 1935.6.1 DFP Arithmetic Instructions . . . . 1935.6.2 DFP Compare Instructions . . . . 1975.6.3 DFP Test Instructions. . . . . . . . . 2005.6.4 DFP Quantum Adjustment Instruc-

tions . . . . . . . . . . . . . . . . . . . . . . . . . . 2035.6.5 DFP Conversion Instructions . . . 2125.6.5.1 DFP Data-Format Conversion

Instructions . . . . . . . . . . . . . . . . . . . . . 2125.6.5.2 DFP Data-Type Conversion

Instructions . . . . . . . . . . . . . . . . . . . . . 2155.6.6 DFP Format Instructions . . . . . . 2175.6.7 DFP Instruction Summary . . . . . 221

Chapter 6. Vector Facility . . . . . . . 2236.1 Vector Facility Overview . . . . . . . . 2236.2 Chapter Conventions . . . . . . . . . . 2236.2.1 Description of Instruction Operation.

2236.3 Vector Facility Registers . . . . . . . . 2326.3.1 Vector Registers. . . . . . . . . . . . . 2326.3.2 Vector Status and Control Register .

2326.3.3 VR Save Register. . . . . . . . . . . . 2336.4 Vector Storage Access Operations 2346.4.1 Accessing Unaligned Storage Oper-

ands. . . . . . . . . . . . . . . . . . . . . . . . . . . 2366.5 Vector Integer Operations . . . . . . . 2376.5.1 Integer Saturation. . . . . . . . . . . . 2376.6 Vector Floating-Point Operations . 2396.6.1 Floating-Point Overview . . . . . . . 2396.6.2 Floating-Point Exceptions . . . . . 2396.6.2.1 NaN Operand Exception . . . . . 2396.6.2.2 Invalid Operation Exception . . 2406.6.2.3 Zero Divide Exception . . . . . . . 2406.6.2.4 Log of Zero Exception . . . . . . . 2406.6.2.5 Overflow Exception . . . . . . . . . 2406.6.2.6 Underflow Exception . . . . . . . . 2406.7 Vector Storage Access Instructions2416.7.1 Storage Access Exceptions . . . . 2416.7.2 Vector Load Instructions. . . . . . . 2426.7.3 Vector Store Instructions . . . . . . 2456.7.4 Vector Alignment Support Instruc-

tions . . . . . . . . . . . . . . . . . . . . . . . . . . . 2476.8 Vector Permute and Formatting

Instructions . . . . . . . . . . . . . . . . . . . . . 2486.8.1 Vector Pack and Unpack Instructions

2486.8.2 Vector Merge Instructions . . . . . 2556.8.3 Vector Splat Instructions . . . . . . 2586.8.4 Vector Permute Instruction. . . . . 2606.8.5 Vector Select Instruction . . . . . . 2616.8.6 Vector Shift Instructions . . . . . . . 2626.8.7 Vector Extract Element Instructions .

2676.8.8 Vector Insert Element Instructions . .

2686.9 Vector Integer Instructions . . . . . . 2696.9.1 Vector Integer Arithmetic Instructions

2696.9.1.1 Vector Integer Add Instructions 2696.9.1.2 Vector Integer Subtract Instructions

2756.9.1.3 Vector Integer Multiply Instructions

2816.9.1.4 Vector Integer Multiply-Add/Sum

Instructions . . . . . . . . . . . . . . . . . . . . . 2856.9.1.5 Vector Integer Sum-Across Instruc-

tions . . . . . . . . . . . . . . . . . . . . . . . . . . . 290

Table of Contents xi

Version 3.0 B

6.9.1.6 Vector Integer Negate Instructions.293

6.9.2 Vector Extend Sign Instructions .2946.9.2.1 Vector Integer Average Instructions

2956.9.2.2 Vector Integer Absolute Difference

Instructions . . . . . . . . . . . . . . . . . . . . . .2976.9.2.3 Vector Integer Maximum and Mini-

mum Instructions . . . . . . . . . . . . . . . . .2996.9.3 Vector Integer Compare Instructions.

3036.9.4 Vector Logical Instructions . . . . .3126.9.5 Vector Parity Byte Instructions . .3146.9.6 Vector Integer Rotate and Shift

Instructions . . . . . . . . . . . . . . . . . . . . . .3156.10 Vector Floating-Point Instruction Set .

3216.10.1 Vector Floating-Point Arithmetic

Instructions . . . . . . . . . . . . . . . . . . . . . .3216.10.2 Vector Floating-Point Maximum and

Minimum Instructions . . . . . . . . . . . . . .3236.10.3 Vector Floating-Point Rounding and

Conversion Instructions . . . . . . . . . . . .3246.10.4 Vector Floating-Point Compare

Instructions . . . . . . . . . . . . . . . . . . . . . .3286.10.5 Vector Floating-Point Estimate

Instructions . . . . . . . . . . . . . . . . . . . . . .3316.11 Vector Exclusive-OR-based Instruc-

tions . . . . . . . . . . . . . . . . . . . . . . . . . . .3336.11.1 Vector AES Instructions. . . . . . .3336.11.2 Vector SHA-256 and SHA-512

Sigma Instructions . . . . . . . . . . . . . . . .3356.11.3 Vector Binary Polynomial Multiplica-

tion Instructions . . . . . . . . . . . . . . . . . .3366.11.4 Vector Permute and Exclusive-OR

Instruction . . . . . . . . . . . . . . . . . . . . . . .3386.12 Vector Gather Instruction . . . . . . .3396.13 Vector Count Leading Zeros Instruc-

tions . . . . . . . . . . . . . . . . . . . . . . . . . . .3406.14 Vector Count Trailing Zeros Instruc-

tions . . . . . . . . . . . . . . . . . . . . . . . . . . .3416.14.1 Vector Count Leading/Trailing Zero

LSB Instructions . . . . . . . . . . . . . . . . . .3426.14.2 Vector Extract Element Instructions

3436.15 Vector Population Count Instructions .

3456.16 Vector Bit Permute Instruction . . .3466.17 Decimal Integer Instructions. . . . .3476.17.1 Decimal Integer Arithmetic Instruc-

tions . . . . . . . . . . . . . . . . . . . . . . . . . . .3476.17.2 Decimal Integer Format Conversion

Instructions . . . . . . . . . . . . . . . . . . . . . .3506.17.3 Decimal Integer Sign Manipulation

Instructions . . . . . . . . . . . . . . . . . . . . . .356

6.17.4 Decimal Integer Shift and Round Instructions . . . . . . . . . . . . . . . . . . . . . 357

6.17.5 Decimal Integer Truncate Instruc-tions . . . . . . . . . . . . . . . . . . . . . . . . . . 360

6.18 Vector Status and Control Register Instructions . . . . . . . . . . . . . . . . . . . . . 362

Chapter 7. Vector-Scalar Floating-Point Operations . . . . . . 363

7.1 Introduction. . . . . . . . . . . . . . . . . . 3637.1.1 Overview of the Vector-Scalar Exten-

sion . . . . . . . . . . . . . . . . . . . . . . . . . . . 3637.1.1.1 Compatibility with Floating-Point

and Decimal Floating-Point Operations 3637.1.1.2 Compatibility with Vector Opera-

tions . . . . . . . . . . . . . . . . . . . . . . . . . . 3637.2 VSX Registers . . . . . . . . . . . . . . . 3647.2.1 Vector-Scalar Registers. . . . . . . 3647.2.1.1 Floating-Point Registers . . . . . 3647.2.1.2 Vector Registers . . . . . . . . . . . 3667.2.2 Floating-Point Status and Control

Register. . . . . . . . . . . . . . . . . . . . . . . . 3677.3 VSX Operations . . . . . . . . . . . . . . 3727.3.1 VSX Floating-Point Arithmetic Over-

view. . . . . . . . . . . . . . . . . . . . . . . . . . . 3727.3.2 VSX Floating-Point Data . . . . . . 3737.3.2.1 Data Format . . . . . . . . . . . . . . 3737.3.2.2 Value Representation . . . . . . . 3757.3.2.3 Sign of Result . . . . . . . . . . . . . 3767.3.2.4 Normalization and Denormalization

3777.3.2.5 Data Handling and Precision . 3777.3.2.6 Rounding . . . . . . . . . . . . . . . . 3817.3.3 VSX Floating-Point Execution Mod-

els . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3847.3.3.1 VSX Execution Model for IEEE

Operations . . . . . . . . . . . . . . . . . . . . . 3847.3.3.2 VSX Execution Model for Multi-

ply-Add Type Instructions . . . . . . . . . . 3857.4 VSX Floating-Point Exceptions. . . 3877.4.1 Floating-Point Invalid Operation

Exception . . . . . . . . . . . . . . . . . . . . . . 3907.4.1.1 Definition. . . . . . . . . . . . . . . . . 3907.4.1.2 Action for VE=1. . . . . . . . . . . . 3907.4.1.3 Action for VE=0. . . . . . . . . . . . 3927.4.2 Floating-Point Zero Divide Exception

4017.4.2.1 Definition. . . . . . . . . . . . . . . . . 4017.4.2.2 Action for ZE=1. . . . . . . . . . . . 4017.4.2.3 Action for ZE=0. . . . . . . . . . . . 4027.4.3 Floating-Point Overflow Exception .

4047.4.3.1 Definition. . . . . . . . . . . . . . . . . 4047.4.3.2 Action for OE=1 . . . . . . . . . . . 4047.4.3.3 Action for OE=0 . . . . . . . . . . . 407

Power ISA™ xii

Version 3.0 B

7.4.4 Floating-Point Underflow Exception. 409

7.4.4.1 Definition. . . . . . . . . . . . . . . . . 4097.4.4.2 Action for UE=1 . . . . . . . . . . . 4097.4.4.3 Action for UE=0 . . . . . . . . . . . 4117.4.5 Floating-Point Inexact Exception 4147.4.5.1 Definition. . . . . . . . . . . . . . . . . 4147.4.5.2 Action for XE=1. . . . . . . . . . . . 4147.4.5.3 Action for XE=0. . . . . . . . . . . . 4177.5 VSX Storage Access Operations . 4207.5.1 Accessing Aligned Storage Oper-

ands . . . . . . . . . . . . . . . . . . . . . . . . . . 4207.5.2 Accessing Unaligned Storage Oper-

ands . . . . . . . . . . . . . . . . . . . . . . . . . . 4217.5.3 Storage Access Exceptions . . . . 4227.6 VSX Instruction Set . . . . . . . . . . . 4237.6.1 VSX Instruction Set Summary . . 4237.6.1.1 VSX Storage Access Instructions .

4237.6.1.2 VSX Binary Floating-Point Sign

Manipulation Instructions . . . . . . . . . . 4257.6.1.3 VSX Binary Floating-Point Arithme-

tic Instructions . . . . . . . . . . . . . . . . . . . 4257.6.1.4 VSX Binary Floating-Point Com-

pare Instructions . . . . . . . . . . . . . . . . . 4287.6.1.5 VSX Binary Floating-Point Round

to Shorter Precision Instructions . . . . . 4297.6.1.6 VSX Binary Floating-Point Convert

to Shorter Precision Instructions . . . . . 4297.6.1.7 VSX Binary Floating-Point Convert

to Longer Precision Instructions . . . . . 4297.6.1.8 VSX Binary Floating-Point Round

to Integral Instructions. . . . . . . . . . . . . 4307.6.1.9 VSX Binary Floating-Point Convert

To Integer Instructions. . . . . . . . . . . . . 4307.6.1.10 VSX Binary Floating-Point Con-

vert From Integer Instructions . . . . . . . 4317.6.1.11 VSX Binary Floating-Point Math

Support Instructions . . . . . . . . . . . . . . 4317.6.1.12 VSX Vector Logical Instructions .

4327.6.1.13 VSX Vector Permute-class

Instructions . . . . . . . . . . . . . . . . . . . . . 4327.6.2 VSX Instruction Description Conven-

tions . . . . . . . . . . . . . . . . . . . . . . . . . . 4347.6.2.1 VSX Instruction RTL Operators 4347.6.2.2 VSX Instruction RTL Function

Calls . . . . . . . . . . . . . . . . . . . . . . . . . . 4357.6.3 VSX Instruction Descriptions . . . 480

Appendix A. Suggested Floating-Point Models . . . . . . . . . 775

A.1 Floating-Point Round to Single-Preci-sion Model. . . . . . . . . . . . . . . . . . . . . . 775

A.2 Floating-Point Convert to Integer Model . . . . . . . . . . . . . . . . . . . . . . . . . 779

A.3 Floating-Point Convert from Integer Model. . . . . . . . . . . . . . . . . . . . . . . . . . 782

A.4 Floating-Point Round to Integer Model784

Appendix B. Densely Packed Decimal . . . . . . . . . . . . . . . . . . . . . . 787

B.1 BCD-to-DPD Translation. . . . . . . . 787B.2 DPD-to-BCD Translation. . . . . . . . 787B.3 Preferred DPD encoding. . . . . . . . 788

Appendix C. Assembler Extended Mnemonics . . . . . . . . . . . . . . . . . . . 791

C.1 Symbols . . . . . . . . . . . . . . . . . . . . 791C.2 Branch Mnemonics. . . . . . . . . . . . 792C.2.1 BO and BI Fields . . . . . . . . . . . . 792C.2.2 Simple Branch Mnemonics . . . . 792C.2.3 Branch Mnemonics Incorporating

Conditions . . . . . . . . . . . . . . . . . . . . . . 793C.2.4 Branch Prediction . . . . . . . . . . . 794C.3 Condition Register Logical Mnemonics

795C.4 Subtract Mnemonics. . . . . . . . . . . 795C.4.1 Subtract Immediate . . . . . . . . . . 795C.4.2 Subtract . . . . . . . . . . . . . . . . . . . 795C.5 Compare Mnemonics . . . . . . . . . . 796C.5.1 Doubleword Comparisons . . . . . 796C.5.2 Word Comparisons . . . . . . . . . . 796C.6 Trap Mnemonics . . . . . . . . . . . . . . 797C.7 Integer Select Mnemonics . . . . . . 798C.8 Rotate and Shift Mnemonics . . . . 799C.8.1 Operations on Doublewords . . . 799C.8.2 Operations on Words. . . . . . . . . 800C.9 Move To/From Special Purpose Regis-

ter Mnemonics . . . . . . . . . . . . . . . . . . . 801C.10 Miscellaneous Mnemonics . . . . . 802

Book II:

Power ISA Virtual Environment Architecture . . . . . . . . . . . . . . . . . . 807

Chapter 1. Storage Model. . . . . . . 8091.1 Definitions . . . . . . . . . . . . . . . . . . . 8091.2 Introduction . . . . . . . . . . . . . . . . . . 8101.3 Virtual Storage . . . . . . . . . . . . . . . 8101.4 Single-Copy Atomicity . . . . . . . . . 8111.5 Cache Model . . . . . . . . . . . . . . . . . 8121.6 Storage Control Attributes . . . . . . 8121.6.1 Write Through Required . . . . . . 8131.6.2 Caching Inhibited . . . . . . . . . . . 8131.6.3 Memory Coherence Required . 8131.6.4 Guarded . . . . . . . . . . . . . . . . . . 8131.6.5 Strong Access Order . . . . . . . . . 814

Table of Contents xiii

Version 3.0 B

1.7 Shared Storage . . . . . . . . . . . . . .8141.7.1 Storage Access Ordering . . . . .8151.7.2 Storage Ordering of Copy/Paste-Initi-

ated Data Transfers . . . . . . . . . . . . . . .8171.7.3 Storage Ordering of I/O Accesses. . .

8171.7.4 Atomic Update. . . . . . . . . . . . . . .8171.7.4.1 Reservations . . . . . . . . . . . . .8181.7.4.2 Forward Progress . . . . . . . . . .8201.8 Transactions. . . . . . . . . . . . . . . . . .8211.8.1 Rollback-Only Transactions . . . .8231.9 Instruction Storage . . . . . . . . . . . . .8231.9.1 Concurrent Modification and Execu-

tion of Instructions . . . . . . . . . . . . . . . .825

Chapter 2. Performance Considerations and Instruction Restart . . . . . . . . . . . . . . . . . . . . . . 827

2.1 Performance-Optimized Instruction Sequences . . . . . . . . . . . . . . . . . . . . . .827

2.1.1 Load and Store Operations . . . . .8282.1.2 32-Bit Constant Generation. . . . .8312.1.3 Sign and Zero Extension . . . . . .8312.1.4 Load/Store Addressing Relative to

Program Counter . . . . . . . . . . . . . . . . .8322.1.5 Destructive Operation Operand

Preservation . . . . . . . . . . . . . . . . . . . . .8332.2 Instruction Restart . . . . . . . . . . . .834

Chapter 3. Management of Shared Resources . . . . . . . . . . . . . . . . . . . 835

3.1 Program Priority Registers . . . . . . .8353.2 “or” Instruction . . . . . . . . . . . . . . . .835

Chapter 4. Storage Control Instructions . . . . . . . . . . . . . . . . . . 837

4.1 Parameters Useful to Application Pro-grams . . . . . . . . . . . . . . . . . . . . . . . . . .837

4.2 Data Stream Control Register (DSCR)837

4.3 Cache Management Instructions .8394.3.1 Instruction Cache Instructions. . .8404.3.2 Data Cache Instructions . . . . . . .8414.3.2.1 Obsolete Data Cache Instructions .

8524.3.3 “or” Instruction . . . . . . . . . . . . . . .8534.4 Copy-Paste Facility . . . . . . . . . . . .8544.5 Atomic Memory Operations . . . . . .8574.5.1 Load Atomic . . . . . . . . . . . . . . . .8574.5.2 Store Atomic . . . . . . . . . . . . . . . .8614.6 Synchronization Instructions . . . . .8634.6.1 Instruction Synchronize Instruction . .

863

4.6.2 Load and Reserve and Store Condi-tional Instructions . . . . . . . . . . . . . . . . 863

4.6.2.1 64-Bit Load and Reserve and Store Conditional Instructions. . . . . . . . . . . . 869

4.6.2.2 128-bit Load and Reserve Store Conditional Instructions. . . . . . . . . . . . 871

4.6.3 Memory Barrier Instructions . . . 8734.6.4 Wait Instruction . . . . . . . . . . . . . 876

Chapter 5. Transactional Memory Facility . . . . . . . . . . . . . . . . . . . . . 877

5.1 Transactional Memory Facility Over-view. . . . . . . . . . . . . . . . . . . . . . . . . . . 877

5.1.1 Definitions . . . . . . . . . . . . . . . . . 8785.2 Transactional Memory Facility States.

8805.2.1 The TDOOMED Bit . . . . . . . . . . 8825.3 Transaction Failure . . . . . . . . . . . . 8825.3.1 Causes of Transaction Failure . . 8825.3.2 Recording of Transaction Failure 8855.3.3 Handling of Transaction Failure. 8855.4 Transactional Memory Facility Regis-

ters . . . . . . . . . . . . . . . . . . . . . . . . . . . 8865.4.1 Transaction Failure Handler Address

Register (TFHAR) . . . . . . . . . . . . . . . . 8865.4.2 Transaction EXception And Status

Register (TEXASR). . . . . . . . . . . . . . . 8865.4.3 Transaction Failure Instruction

Address Register (TFIAR). . . . . . . . . . 8895.5 Transactional Facility Instructions. 890

Chapter 6. Time Base . . . . . . . . . 8976.1 Time Base Instructions . . . . . . . . . 898

Chapter 7. Event-Based Branch Facility . . . . . . . . . . . . . . . . . . . . . 901

7.1 Event-Based Branch Overview. . . 9017.2 Event-Based Branch Registers . . 9027.2.1 Branch Event Status and Control

Register. . . . . . . . . . . . . . . . . . . . . . . . 9027.2.2 Event-Based Branch Handler Regis-

ter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9037.2.3 Event-Based Branch Return Register

9047.3 Event-Based Branch Instructions . 905

Chapter 8. Branch History Rolling Buffer . . . . . . . . . . . . . . . . . . . . . . . 907

8.1 Branch History Rolling Buffer Entry Format. . . . . . . . . . . . . . . . . . . . . . . . . 908

8.2 Branch History Rolling Buffer Instruc-tions . . . . . . . . . . . . . . . . . . . . . . . . . . 909

Power ISA™ xiv

Version 3.0 B

Appendix A. Assembler Extended Mnemonics . . . . . . . . . . . . . . . . . . 911

A.1 Data Cache Block Touch [for Store] Mnemonics . . . . . . . . . . . . . . . . . . . . . 911

A.2 Data Cache Block Flush Mnemonics . 911

A.3 Or Mnemonics . . . . . . . . . . . . . . . 911A.4 Load and Reserve

Mnemonics . . . . . . . . . . . . . . . . . . . . . 911A.5 Synchronize Mnemonics . . . . . . . 912A.6 Wait Mnemonics. . . . . . . . . . . . . . 912A.7 Transactional Memory Instruction

Mnemics . . . . . . . . . . . . . . . . . . . . . . . 912A.8 Move To/From Time Base Mnemonics

912A.9 Return From Event-Based Branch

Mnemonic . . . . . . . . . . . . . . . . . . . . . . 912

Appendix B. Programming Examples for Sharing Storage . . . . . . . . . . . 913

B.1 Atomic Update Primitives . . . . . . . 913B.2 Lock Acquisition and Release, and

Related Techniques. . . . . . . . . . . . . . . 915B.2.1 Lock Acquisition and Import Barriers

915B.2.1.1 Acquire Lock and Import Shared

Storage . . . . . . . . . . . . . . . . . . . . . . . . 915B.2.1.2 Obtain Pointer and Import Shared

Storage . . . . . . . . . . . . . . . . . . . . . . . . 915B.2.2 Lock Release and Export Barriers. .

916B.2.2.1 Export Shared Storage and

Release Lock . . . . . . . . . . . . . . . . . . . 916B.2.2.2 Export Shared Storage and

Release Lock using lwsync. . . . . . . . . 916B.2.3 Safe Fetch. . . . . . . . . . . . . . . . . 916B.3 List Insertion. . . . . . . . . . . . . . . . . 917B.4 Notes . . . . . . . . . . . . . . . . . . . . . . 917B.5 Transactional Lock Elision . . . . . . 917B.5.1 Enter Critical Section. . . . . . . . . 918B.5.2 Handling Busy Lock . . . . . . . . . 918B.5.3 Handling TLE Abort . . . . . . . . . . 918B.5.4 TLE Exit Section Critical Path . . 918B.5.5 Acquisition and Release of TLE

Locks. . . . . . . . . . . . . . . . . . . . . . . . . . 918

Book III:

Power ISA Operating Environment Architecture. . . . . . . . . . . . . . . . . . 921

Chapter 1. Introduction . . . . . . . . 9231.1 Overview. . . . . . . . . . . . . . . . . . . . 9231.2 Document Conventions . . . . . . . . 923

1.2.1 Definitions and Notation . . . . . . . 9231.2.2 Reserved Fields . . . . . . . . . . . . . 9241.3 General Systems Overview. . . . . . 9251.4 Exceptions. . . . . . . . . . . . . . . . . . . 9251.5 Synchronization. . . . . . . . . . . . . . . 9251.5.1 Context Synchronization . . . . . . 9251.5.2 Execution Synchronization. . . . . 926

Chapter 2. Logical Partitioning (LPAR) and Thread Control . . . . . . 927

2.1 Overview . . . . . . . . . . . . . . . . . . . . 9272.2 Logical Partitioning Control Register

(LPCR). . . . . . . . . . . . . . . . . . . . . . . . . 9272.3 Hypervisor Real Mode Offset Register

(HRMOR). . . . . . . . . . . . . . . . . . . . . . . 9312.4 Logical Partition

Identification Register (LPIDR) . . . . . . 9312.5 Processor Compatibility Register

(PCR). . . . . . . . . . . . . . . . . . . . . . . . . . 9322.6 Other Hypervisor Resources. . . . . 9412.7 Sharing Hypervisor Resources . . . 9412.8 Sub-Processors. . . . . . . . . . . . . . . 9422.9 Thread Identification Register (TIR) . .

9422.10 Hypervisor Interrupt Little-Endian

(HILE) Bit . . . . . . . . . . . . . . . . . . . . . . . 942

Chapter 3. Branch Facility . . . . . . 9433.1 Branch Facility Overview. . . . . . . . 9433.2 Branch Facility Registers . . . . . . . 9433.2.1 Machine State Register . . . . . . . 9433.2.2 State Transitions Associated with the

Transactional Memory Facility . . . . . . . 9463.2.3 Processor Stop Status and Control

Register (PSSCR) . . . . . . . . . . . . . . . . 9493.3 Branch Facility Instructions . . . . . . 9523.3.1 System Linkage Instructions . . . 9523.3.2 Power-Saving Mode. . . . . . . . . . 9573.3.2.1 Power-Saving Mode Instruction . .

9583.3.2.2 Entering and Exiting Power-Sav-

ing Mode . . . . . . . . . . . . . . . . . . . . . . . 9583.4 Event-Based Branch Facility and

Instruction . . . . . . . . . . . . . . . . . . . . . . 960

Chapter 4. Fixed-Point Facility. . . 9614.1 Fixed-Point Facility Overview . . . . 9614.2 Special Purpose Registers . . . . . . 9614.3 Fixed-Point Facility Registers . . . . 9614.3.1 Processor Version Register . . . . 9614.3.2 Chip Information Register . . . . . 9614.3.3 Processor Identification Register 9614.3.4 Process Identification Register. . 9624.3.5 Thread ID Register. . . . . . . . . . . 9624.3.6 Control Register . . . . . . . . . . . . . 962

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4.3.7 Program Priority Register . . . . . .9634.3.8 Problem State Priority Boost Regis-

ter . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9634.3.9 Relative Priority Register. . . . . . .9634.3.10 Software-use SPRs. . . . . . . . . .9644.4 Fixed-Point Facility Instructions . . .9654.4.1 Fixed-Point Load and Store Caching

Inhibited Instructions. . . . . . . . . . . . . . .9654.4.2 OR Instruction . . . . . . . . . . . . . . .9684.4.3 Transactional Memory Instructions . .

9694.4.4 Move To/From System Register

Instructions . . . . . . . . . . . . . . . . . . . . . .970

Chapter 5. Storage Control . . . . . 9815.1 Overview . . . . . . . . . . . . . . . . . . . .9815.2 Storage Exceptions . . . . . . . . . . . .9815.3 Instruction Fetch . . . . . . . . . . . . . .9815.3.1 Implicit Branch. . . . . . . . . . . . . . .9815.3.2 Address Wrapping Combined with

Changing MSR Bit SF . . . . . . . . . . . . .9815.4 Data Access . . . . . . . . . . . . . . . . . .9825.5 Performing Operations

Out-of-Order . . . . . . . . . . . . . . . . . . . . .9825.6 Invalid Real Address . . . . . . . . . . .9825.7 Storage Addressing . . . . . . . . . . . .9835.7.1 32-Bit Mode. . . . . . . . . . . . . . . . .9835.7.2 Virtualized Partition Memory (VPM)

Mode. . . . . . . . . . . . . . . . . . . . . . . . . . .9845.7.3 Hypervisor Real And Virtual Real

Addressing Modes . . . . . . . . . . . . . . . .9845.7.3.1 Hypervisor Offset Real Mode

Address . . . . . . . . . . . . . . . . . . . . . . . .9845.7.3.2 Storage Control Attributes for

Accesses in Hypervisor Real Addressing Mode. . . . . . . . . . . . . . . . . . . . . . . . . . .984

5.7.3.2.1 Hypervisor Real Mode Storage Control . . . . . . . . . . . . . . . . . . . . . . . . .985

5.7.3.3 Virtual Real Mode Addressing Mechanism . . . . . . . . . . . . . . . . . . . . . .985

5.7.3.4 Storage Control Attributes for Implicit Storage Accesses. . . . . . . . . . .986

5.7.4 Definitions . . . . . . . . . . . . . . . . . .9865.7.5 Address Ranges Having Defined

Uses . . . . . . . . . . . . . . . . . . . . . . . . . . .9875.7.5.1 Effective Address Space Structure

for Radix-using Partitions . . . . . . . . . . .9875.7.6 In-Memory Tables . . . . . . . . . . . .9885.7.6.1 Partition Table . . . . . . . . . . . . .9895.7.6.2 Process Table. . . . . . . . . . . . . .9915.7.7 Address Translation Overview . .9915.7.8 Segment Translation . . . . . . . . . .9945.7.8.1 Segment Lookaside Buffer (SLB) .

9945.7.8.2 SLB Search . . . . . . . . . . . . . . .995

5.7.8.3 Segment Table Description and Search. . . . . . . . . . . . . . . . . . . . . . . . . 995

5.7.8.3.1 Primary Hash for 256MB Seg-ment . . . . . . . . . . . . . . . . . . . . . . . . . . 996

5.7.8.3.2 Primary Hash for 1TB Segment. 996

5.7.8.3.3 Secondary Hash for 256MB Seg-ment . . . . . . . . . . . . . . . . . . . . . . . . . . 996

5.7.8.3.4 Secondary Hash for 1TB Seg-ment . . . . . . . . . . . . . . . . . . . . . . . . . . 996

5.7.9 Hashed Page Table Translation. 9965.7.9.1 Hashed Page Table . . . . . . . . 9985.7.9.2 Page Table Search . . . . . . . . . 9995.7.10 Radix Tree Translation. . . . . . 10015.7.10.1 Radix Tree Page Directory Entry

10025.7.10.2 Radix Tree Page Table Entry10035.7.10.3 Nested Translation . . . . . . . 10035.7.11 Translation Process . . . . . . . . 10055.7.11.1 Fully-Qualified Address . . . . 10055.7.11.2 Finding the Page Tables . . . 10065.7.11.3 Obtaining Host Real Address,

Radix on Radix . . . . . . . . . . . . . . . . . 10065.7.11.4 Obtaining Host Real Address,

HPT. . . . . . . . . . . . . . . . . . . . . . . . . . 10075.7.12 Reference and Change Recording

10075.7.13 Storage Protection. . . . . . . . . 10115.7.13.1 Virtual Page Class Key Protection

10115.7.13.2 Basic Storage Protection,

Address Translation Enabled . . . . . . 10155.7.13.3 Basic Storage Protection,

Address Translation Disabled . . . . . . 10165.7.13.4 Radix Tree Translation Storage

Protection . . . . . . . . . . . . . . . . . . . . . 10165.8 Storage Control Attributes . . . . . 10175.8.1 Guarded Storage . . . . . . . . . . . 10175.8.1.1 Out-of-Order Accesses to Guarded

Storage . . . . . . . . . . . . . . . . . . . . . . . 10185.8.2 Storage Control Bits . . . . . . . . 10185.8.2.1 Storage Control Bit Restrictions . .

10195.8.2.2 Altering the Storage Control Bits .

10195.9 Storage Control Instructions . . . . 10215.9.1 Cache Management Instructions. . .

10215.9.2 Synchronize Instruction . . . . . . 10215.9.3 Lookaside Buffer

Management . . . . . . . . . . . . . . . . . . . 10225.9.3.1 Thread-Specific Segment Transla-

tions . . . . . . . . . . . . . . . . . . . . . . . . . 10235.9.3.2 SLB Management Instructions . .

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5.9.3.3 TLB Management Instructions . . . 1033

5.10 Translation Table Update Synchroni-zation Requirements . . . . . . . . . . . . . 1043

5.10.1 Translation Table Updates . . . 10445.10.1.1 Adding a Page Table Entry . 10455.10.1.2 Modifying a Translation Table

Entry . . . . . . . . . . . . . . . . . . . . . . . . . 1045

Chapter 6. Interrupts . . . . . . . . . 10496.1 Overview. . . . . . . . . . . . . . . . . . . 10496.2 Interrupt Registers . . . . . . . . . . . 10496.2.1 Machine Status Save/Restore Regis-

ters . . . . . . . . . . . . . . . . . . . . . . . . . . 10496.2.2 Hypervisor Machine Status Save/

Restore Registers . . . . . . . . . . . . . . . 10496.2.3 Access Segment Descriptor Register

10496.2.4 Data Address Register. . . . . . . 10506.2.5 Hypervisor Data Address Register. .

10506.2.6 Data Storage Interrupt

Status Register . . . . . . . . . . . . . . . . . 10506.2.7 Hypervisor Data Storage Interrupt

Status Register . . . . . . . . . . . . . . . . . 10506.2.8 Hypervisor Emulation Instruction

Register. . . . . . . . . . . . . . . . . . . . . . . 10506.2.9 Hypervisor Maintenance Exception

Register. . . . . . . . . . . . . . . . . . . . . . . 10516.2.10 Hypervisor Maintenance Exception

Enable Register . . . . . . . . . . . . . . . . 10516.2.11 Facility Status and Control Register

10516.2.12 Hypervisor Facility Status and Con-

trol Register. . . . . . . . . . . . . . . . . . . . 10526.3 Interrupt Synchronization . . . . . . 10576.4 Interrupt Classes . . . . . . . . . . . . 10576.4.1 Precise Interrupt . . . . . . . . . . . 10576.4.2 Imprecise Interrupt. . . . . . . . . . 10576.4.3 Interrupt Processing . . . . . . . . 10596.4.4 Implicit alteration of HSRR0 and

HSRR1 . . . . . . . . . . . . . . . . . . . . . . . 10616.5 Interrupt Definitions . . . . . . . . . . 10636.5.1 System Reset Interrupt . . . . . . 10656.5.2 Machine Check Interrupt . . . . . 10676.5.3 Data Storage Interrupt . . . . . . . 10696.5.4 Data Segment Interrupt . . . . . 10716.5.5 Instruction Storage Interrupt . . 10716.5.6 Instruction Segment

Interrupt. . . . . . . . . . . . . . . . . . . . . . . 10726.5.7 External Interrupt . . . . . . . . . . . 10736.5.7.1 Direct External Interrupt . . . . 10736.5.7.2 Mediated External Interrupt . 10736.5.8 Alignment Interrupt . . . . . . . . . 10736.5.9 Program Interrupt . . . . . . . . . . 1074

6.5.10 Floating-Point Unavailable Interrupt . . . . . . . . . . . . . . . . . . . . . . . 1076

6.5.11 Decrementer Interrupt . . . . . . 10766.5.12 Hypervisor Decrementer

Interrupt . . . . . . . . . . . . . . . . . . . . . . . 10776.5.13 Directed Privileged Doorbell Inter-

rupt . . . . . . . . . . . . . . . . . . . . . . . . . . 10776.5.14 System Call Interrupt . . . . . . . 10776.5.15 Trace Interrupt . . . . . . . . . . . . 10776.5.16 Hypervisor Data Storage Interrupt .

10786.5.17 Hypervisor Instruction Storage

Interrupt . . . . . . . . . . . . . . . . . . . . . . . 10826.5.18 Hypervisor Emulation Assistance

Interrupt . . . . . . . . . . . . . . . . . . . . . . . 10836.5.19 Hypervisor Maintenance Interrupt .

10866.5.20 Directed Hypervisor Doorbell Inter-

rupt . . . . . . . . . . . . . . . . . . . . . . . . . . 10866.5.21 Hypervisor Virtualization Interrupt .

10876.5.22 Performance Monitor

Interrupt . . . . . . . . . . . . . . . . . . . . . . . 10876.5.23 Vector Unavailable Interrupt. . 10876.5.24 VSX Unavailable Interrupt . . . 10876.5.25 Facility Unavailable Interrupt . 10886.5.26 Hypervisor Facility Unavailable

Interrupt . . . . . . . . . . . . . . . . . . . . . . . 10886.5.27 System Call Vectored Interrupt10886.6 Partially Executed

Instructions . . . . . . . . . . . . . . . . . . . . 10906.7 Exception Ordering . . . . . . . . . . . 10916.7.1 Unordered Exceptions . . . . . . . 10916.7.2 Ordered Exceptions . . . . . . . . . 10916.8 Event-Based Branch Exception Order-

ing . . . . . . . . . . . . . . . . . . . . . . . . . . . 10926.9 Interrupt Priorities . . . . . . . . . . . . 10926.10 Relationship of Event-Based

Branches to Interrupts . . . . . . . . . . . . 10956.10.1 EBB Exception Priority . . . . . . 10956.10.2 EBB Synchronization . . . . . . . 10956.10.3 EBB Classes . . . . . . . . . . . . . 1095

Chapter 7. Timer Facilities . . . . . 10977.1 Overview . . . . . . . . . . . . . . . . . . . 10977.2 Time Base (TB) . . . . . . . . . . . . . . 10977.2.1 Writing the Time Base . . . . . . . 10987.3 Virtual Time Base . . . . . . . . . . . . 10987.4 Decrementer . . . . . . . . . . . . . . . . 10997.4.1 Writing and Reading the Decre-

menter . . . . . . . . . . . . . . . . . . . . . . . . 11007.5 Hypervisor Decrementer . . . . . . . 11007.6 Processor Utilization of Resources

Register (PURR) . . . . . . . . . . . . . . . . 11007.7 Scaled Processor Utilization of

Resources Register (SPURR) . . . . . . 1101

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7.8 Instruction Counter. . . . . . . . . . . . 1102

Chapter 8. Debug Facilities . . . . 11038.1 Overview . . . . . . . . . . . . . . . . . . . 11038.2 Come-From Address Register . . . 11038.3 Completed Instruction Address Break-

point . . . . . . . . . . . . . . . . . . . . . . . . . . 11038.4 Data Address Watchpoint. . . . . . . 1104

Chapter 9. Performance Monitor Facility . . . . . . . . . . . . . . . . . . . . . 1107

9.1 Overview . . . . . . . . . . . . . . . . . . . 11079.2 Performance Monitor Operation. . 11079.3 No-op Instructions Reserved for the

Performance Monitor . . . . . . . . . . . . . 11089.4 Performance Monitor Facility Registers

11089.4.1 Performance Monitor SPR Numbers.

11089.4.2 Performance Monitor Counters . 11099.4.2.1 Event Counting and Sampling 11099.4.3 Threshold Event Counter . . . . . 11109.4.4 Monitor Mode Control Register 0 . . .

11119.4.5 Monitor Mode Control Register 1 . . .

11169.4.6 Monitor Mode Control Register 2 . . .

11189.4.7 Monitor Mode Control Register A . . .

11199.4.8 Sampled Instruction Address Regis-

ter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11229.4.9 Sampled Data Address Register . . . .

11229.4.10 Sampled Instruction Event Register

11239.5 Branch History Rolling Buffer . . . . 11259.6 Interaction With Other Facilities . . 1125

Chapter 10. Processor Control . 112710.1 Overview . . . . . . . . . . . . . . . . . . 112710.2 Programming Model. . . . . . . . . . 112710.3 Processor Control Registers . . . 112710.3.1 Directed Privileged Doorbell Excep-

tion State . . . . . . . . . . . . . . . . . . . . . . 112710.4 Processor Control Instructions . . 1129

Chapter 11. Synchronization Requirements for Context Alterations1133

Power ISA Book I-III Appendices .1139

Appendix A. Illegal Instructions .1141

Appendix B. Reserved Instructions . 1143

Appendix C. Opcode Maps . . . . .1145

Appendix D. Power ISA Instruction Set Sorted by Opcode . . . . . . . . .1179

Appendix E. Power ISA Instruction Set Sorted by Version . . . . . . . . .1199

Appendix F. Power ISA Instruction Set Sorted by Mnemonic . . . . . . 1219

Last Page - End of Document . . . 1239

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Book I: Power ISA User Instruction Set Architecture 1

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Chapter 1. Introduction

1.1 OverviewThis chapter describes computation modes,documentconventions, a processor overview, instruction formats,storage addressing, and instruction fetching.

1.2 Instruction Mnemonics and OperandsThe description of each instruction includes the mne-monic and a formatted list of operands. Some exam-ples are the following.

stw RS,D(RA)addis RT,RA,SI

Power ISA-compliant Assemblers will support the mne-monics and operand lists exactly as shown. Theyshould also provide certain extended mnemonics, suchas the ones described in Appendix C of Book I.

1.3 Document Conventions

1.3.1 DefinitionsThe following definitions are used throughout this docu-ment.

programA sequence of related instructions.

application programA program that uses only the instructions andresources described in Books I and II.

processorThe hardware component that implements theinstruction set, storage model, and other facilitiesdefined in the Power ISA architecture, and exe-cutes the instructions specified in a program.

quadword, doubleword, word, halfword, and byte128 bits, 64 bits, 32 bits, 16 bits, and 8 bits,respectively.

positiveMeans greater than zero.

negativeMeans less than zero.

floating-point single format (or simply single format)Refers to the representation of a single-precisionbinary floating-point value in a register or storage.

floating-point double format (or simply double format)Refers to the representation of a double-precisionbinary floating-point value in a register or storage.

system library programA component of the system software that can becalled by an application program using a Branchinstruction.

system service programA component of the system software that can becalled by an application program using a SystemCall or System Call Vectored instruction.

system trap handlerA component of the system software that receivescontrol when the conditions specified in a Trapinstruction are satisfied.

system error handlerA component of the system software that receivescontrol when an error occurs. The system errorhandler includes a component for each of the vari-ous kinds of error. These error-specific compo-nents are referred to as the system alignment errorhandler, the system data storage error handler,etc.

latencyRefers to the interval from the time an instructionbegins execution until it produces a result that isavailable for use by a subsequent instruction.

unavailableRefers to a resource that cannot be used by theprogram. For example, storage is unavailable ifaccess to it is denied. See Book III.

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undefined valueMay vary between implementations, and betweendifferent executions on the same implementation,and similarly for register contents, storage con-tents, etc., that are specified as being undefined.

boundedly undefinedThe results of executing a given instruction aresaid to be boundedly undefined if they could havebeen achieved by executing an arbitrary finitesequence of instructions (none of which yieldsboundedly undefined results) in the state the pro-cessor was in before executing the given instruc-tion. Boundedly undefined results may include thepresentation of inconsistent state to the systemerror handler as described in Section 1.9.1 of BookII. Boundedly undefined results for a given instruc-tion may vary between implementations, andbetween different executions on the same imple-mentation.

“must”If software violates a rule that is stated using theword “must” (e.g., “this field must be set to 0”), theresults are boundedly undefined unless otherwisestated.

sequential execution modelThe model of program execution described inSection 2.2, “Instruction Execution Order” onpage 29.

1.3.2 NotationThe following notation is used throughout the PowerISA documents.

All numbers are decimal unless specified in somespecial way.

- 0bnnnn means a number expressed in binaryformat.

- 0xnnnn means a number expressed in hexa-decimal format.

Underscores may be used between digits.

RT, RA, R1, ... refer to General Purpose Registers.

FRT, FRA, FR1, ... refer to Floating-Point Regis-ters.

FRTp, FRAp, FRBp, ... refer to an even-odd pair ofFloating-Point Registers. Values must be even,otherwise the instruction form is invalid.

VRT, VRA, VR1, ... refer to Vector Registers.

(x) means the contents of register x, where x is thename of an instruction field. For example, (RA)means the contents of register RA, and (FRA)means the contents of register FRA, where RA andFRA are instruction fields. Names such as LR andCTR denote registers, not fields, so parentheses

are not used with them. Parentheses are alsoomitted when register x is the register into whichthe result of an operation is placed.

(RA|0) means the contents of register RA if the RAfield has the value 1-31, or the value 0 if the RAfield is 0.

Bytes in instructions, fields, and bit strings arenumbered from left to right, starting with byte 0(most significant).

Bits in registers, instructions, fields, and bit stringsare specified as follows. In the last three items(definition of Xp etc.), if X is a field that specifies aGPR, FPR, or VR (e.g., the RS field of an instruc-tion), the definitions apply to the register, not to thefield.

- Bits in instructions, fields, and bit strings arenumbered from left to right, starting with bit 0

- For all registers except the Vector registers,bits in registers that are less than 64 bits startwith bit number 64-L, where L is the registerlength; for the Vector registers, bits in regis-ters that are less than 128 bits start with bitnumber 128-L.

- The leftmost bit of a sequence of bits is themost significant bit of the sequence.

- Xp means bit p of register/instruction/field/bit_string X.

- Xp:q means bits p through q of register/instruc-tion/field/bit_string X.

- Xp q ... means bits p, q, ... of register/instruc-tion/field/bit_string X.

¬(RA) means the one’s complement of the con-tents of register RA.

A period (.) as the last character of an instructionmnemonic means that the instruction records sta-tus information in certain fields of the ConditionRegister as a side effect of execution.

The symbol || is used to describe the concatena-tion of two values. For example, 010 || 111 is thesame as 010111.

xn means x raised to the nth power.

nx means the replication of x, n times (i.e., x con-catenated to itself n-1 times). n0 and n1 are spe-cial cases:

- n0 means a field of n bits with each bit equal to0. Thus 50 is equivalent to 0b00000.

- n1 means a field of n bits with each bit equal to1. Thus 51 is equivalent to 0b11111.

Each bit and field in instructions, and in status andcontrol registers (e.g., XER, FPSCR) and SpecialPurpose Registers, is either defined or reserved.Some defined fields contain reserved values. Insuch cases when this document refers to the spe-cific field, it refers only to the defined values,unless otherwise specified.

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/, //, ///, ... denotes a reserved field, in a register,instruction, field, or bit string.

?, ??, ???, ... denotes an implementation-depen-dent field in a register, instruction, field or bit string.

1.3.3 Reserved Fields, Reserved Values, and Reserved SPRsReserved fields in instructions are ignored by the pro-cessor.

In some cases a defined field of an instruction has cer-tain values that are reserved. This includes cases inwhich the field is shown in the instruction layout as con-taining a particular value; in such cases all other valuesof the field are reserved. In general, if an instruction iscoded such that a defined field contains a reservedvalue the instruction form is invalid; see Section 1.9.2on page 23. The only exception to the preceding rule isthat it does not apply to Reserved and Illegal classes ofinstructions (see Section 1.8) or to portions of definedfields that are specified, in the instruction description,as being treated as reserved fields.

To maximize compatibility with future architectureextensions, software must ensure that reserved fieldsin instructions contain zero and that defined fields ofinstructions do not contain reserved values.

The handling of reserved bits in System Registers (e.g.,XER, FPSCR) depends on whether the processor is inproblem state. Unless otherwise stated, software is per-mitted to write any value to such a bit. In problem state,a subsequent reading of the bit returns 0 regardless ofthe value written; in privileged states, a subsequentreading of the bit returns 0 if the value last written to thebit was 0 and returns an undefined value (0 or 1) other-wise.

In some cases, a defined field of a System Registerhas certain values that are reserved. Software must notset a defined field of a System Register to a reservedvalue. References elsewhere in this document to adefined field (in an instruction or System Register) thathas reserved values assume the field does not containa reserved value, unless otherwise stated or obviousfrom context.

In some cases, a given bit of a System Register isspecified to be set to a constant value by a giveninstruction or event. Unless otherwise stated or obviousfrom context, software should not depend on this con-stant value because the bit may be assigned a mean-ing in a future version of the architecture.

The reserved SPRs include SPRs 808, 809, 810, and811. mtspr and mfspr instructions specifying theseSPRs are treated as no-ops. Reserved SPRs are pro-vided in the architecture to anticipate the eventualadoption of performance hint functionality that must becontrolled by SPRs. Control of these capabilities usingreserved SPRs will allow software to use these newcapabilities on new implementations that support themwhile remaining compatible with existing implementa-tions that may not support the new functionality.


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Reserved SPRs are not assigned names. There are noindividual descriptions of reserved SPRs in this docu-ment.

1.3.4 Description of Instruction OperationInstruction descriptions (including related material suchas the introduction to the section describing the instruc-tions) mention that the instruction may cause a systemerror handler to be invoked, under certain conditions, ifand only if the system error handler may treat the caseas a programming error. (An instruction may cause asystem error handler to be invoked under other condi-tions as well; see Chapter 6 of Book III).

A formal description is given of the operation of eachinstruction. In addition, the operation of most instruc-tions is described by a semiformal language at the reg-ister transfer level (RTL). This RTL uses the notationgiven below, in addition to the notation described inSection 1.3.2. Some of this notation is also used in theformal descriptions of instructions. RTL notation notsummarized here should be self-explanatory.

The RTL descriptions cover the normal execution of theinstruction, except that “standard” setting of status reg-isters, such as the Condition Register, is not shown.

(“Non-standard” setting of these registers, such as thesetting of the Condition Register by the Compareinstructions, is shown.) The RTL descriptions do notcover cases in which the system error handler isinvoked, or for which the results are boundedly unde-fined.

The RTL descriptions specify the architectural transfor-mation performed by the execution of an instruction.They do not imply any particular implementation.

Notation Meaning Assignmentiea Assignment of an instruction effective

address. In 32-bit mode the high-order 32bits of the 64-bit target address are set to0.

¬ NOT logical operator+ Two’s complement addition- Two’s complement subtraction, unary

minus Multiplicationsi Signed-integer multiplicationui Unsigned-integer multiplication/ Division Division, with result truncated to integer% Remainder of integer division Square root=, Equals, Not Equals relations, Signed comparison relationsu Unsigned comparison relations? Unordered comparison relation&, | AND, OR logical operators, Exclusive OR, Equivalence logical opera-

tors ((ab) = (a¬b))ABS(x) Absolute value of xBCD_TO_DPD(x)

The low-order 24 bits of x contain six, 4-bitBCD fields which are converted to twodeclets; each set of two declets is placedinto the low-order 20 bits of the result. SeeSection B.1, “BCD-to-DPD Translation”.

CEIL(x) Least integer xDOUBLE(x) Result of converting x from floating-point

single format to floating-point double for-mat, using the model shown on page 140

DPD_TO_BCD(x)The low-order 20 bits of x contain twodeclets which are converted to six, 4-bitBCD fields; each set of six, 4-bit BCDfields is placed into the low-order 24 bits ofthe result. See Section B.2, “DPD-to-BCDTranslation”.

EXTS(x) Result of extending x on the left with signbits

FLOOR(x) Greatest integer xGPR(x) General Purpose Register xMASK(x, y) Mask having 1s in positions x through y

(wrapping if x > y) and 0s elsewhere

Assemblers should report uses of reserved valuesof defined fields of instructions as errors.

It is the responsibility of software to preserve bitsthat are now reserved in System Registers,because they may be assigned a meaning in somefuture version of the architecture.

In order to accomplish this preservation in imple-mentation-independent fashion, software should dothe following.

Initialize each such register supplying zeros forall reserved bits.

Alter (defined) bit(s) in the register by readingthe register, altering only the desired bit(s),and then writing the new value back to the reg-ister.

The XER and FPSCR are partial exceptions to thisrecommendation. Software can alter the status bitsin these registers, preserving the reserved bits, byexecuting instructions that have the side effect ofaltering the status bits. Similarly, software can alterany defined bit in the FPSCR by executing a Float-ing-Point Status and Control Register instruction.Using such instructions is likely to yield better per-formance than using the method described in thesecond item above.

Assembler Note

Programming Note

Power ISA™ I6

Version 3.0 B

MEM(x, y) Contents of a sequence of y bytes of stor-age. The sequence depends on the byteordering used for storage access, as fol-lows.Big-Endian byte ordering:The sequence starts with the byte ataddress x and ends with the byte ataddress x+y-1.Little-Endian byte ordering: The sequence starts with the byte ataddress x+y-1 and ends with the byte ataddress x.

ROTL64(x, y)Result of rotating the 64-bit value x left ypositions

ROTL32(x, y)Result of rotating the 64-bit value x||x left ypositions, where x is 32 bits long

SINGLE(x) Result of converting x from floating-pointdouble format to floating-point single for-mat, using the model shown on page 144

SPR(x) Special Purpose Register xTRAP Invoke the system trap handlercharacterization

Reference to the setting of status bits, in astandard way that is explained in the text

undefined An undefined value.CIA Current Instruction Address, which is the

64-bit address of the instruction beingdescribed by a sequence of RTL. Used byrelative branches to set the Next Instruc-tion Address (NIA), and by Branch instruc-tions with LK=1 to set the Link Register.Does not correspond to any architectedregister. The CIA is sometimes referred toas the Program Counter (PC).

NIA Next Instruction Address, which is the64-bit address of the next instruction to beexecuted. For a successful branch, thenext instruction address is the branch tar-get address: in RTL, this is indicated byassigning a value to NIA. For other instruc-tions that cause non-sequential instructionfetching (see Book III), the RTL is similar.For instructions that do not branch, and donot otherwise cause instruction fetching tobe non-sequential, the next instructionaddress is CIA+4. Does not correspond toany architected register.

if... then... else... Conditional execution, indenting showsrange; else is optional.

do Do loop, indenting shows range. “To” and/or “by” clauses specify incrementing aniteration variable, and a “while” clausegives termination conditions.

leave Leave innermost do loop, or do loopdescribed in leave statement.

for For loop, indenting shows range. Clauseafter “for” specifies the entities for which toexecute the body of the loop.

switch/case/defaultswitch/case/default statement, indentingshows range. The clause after “switch”specifies the expression to evaluate. Theclause after “case” specifies individual val-ues for the expression, followed by acolon, followed by the actions that aretaken if the evaluated expression has anyof the specified values. “default” isoptional. If present, it must follow all the“case” clauses. The clause after “default”starts with a colon, and specifies theactions that are taken if the evaluatedexpression does not have any of the val-ues specified in the preceding case state-ments.


Version 3.0 B

The precedence rules for RTL operators are summa-rized in Table 1. Operators higher in the table areapplied before those lower in the table. Operators atthe same level in the table associate from left to right,from right to left, or not at all, as shown. (For example,- associates from left to right, so a-b-c = (a-b)-c.)Parentheses are used to override the evaluation orderimplied by the table or to increase clarity; parenthe-sized expressions are evaluated before serving asoperands.

1.3.5 Phased-Out Facilities Phased-Out Facilities

These are facilities and instructions that, in somefuture version of the architecture, will be droppedout of the architecture. System developers shoulddevelop a migration plan to eliminate use of themin new systems. These facilities are marked with a[Phased-Out] marker.

Phased-Out facilities and instructions must beimplemented.

Table 1: Operator precedenceOperators Associativitysubscript, function evaluation left to rightpre-superscript (replication),

post-superscript (exponentiation)right to left

unary -, ¬ right to left, left to right+, -, left to right|| left to right=, , , ,u,? left to right&, , left to right| left to right : (range) none,iea none

Warning: Instructions and facilities being phasedout of the architecture are likely to perform poorlyon future implementations. New programs shouldnot use them.

Programming Note

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Version 3.0 B

1.4 Processor OverviewThe basic classes of instructions are as follows:

branch instructions (Chapter 2) GPR-based scalar fixed-point instructions (Chap-

ter 3) FPR-based scalar floating-point instructions

(Chapter 4) FPR-based scalar decimal floating-point instruc-

tions (Chapter 5) VR-based vector fixed-point and floating-point

instructions (Chapter 6) VSR-based scalar and vector floating-point

instructions (Chapter 7)

Scalar fixed-point instructions operate on byte, half-word, word, doubleword, and quadword operands,where each operand contained in a GPR. Vectorfixed-point instructions operate on vectors of byte, half-word, and word operands, where each vector is con-tained in a VR. Scalar floating-point instructionsoperate on single-precision or double-precision float-ing-point operands, where each operand is containedin an FPR or VSR. Vector floating-point instructionsoperate on vectors of single-precision and double-pre-cision floating-point operands, where each vector iscontained in a VR or VSR.

The Power ISA uses instructions that are four byteslong and word-aligned. It provides for byte, halfword,word, doubleword, and quadword operand loads andstores between storage and a set of 32 General Pur-pose Registers (GPRs). It provides for word and dou-bleword operand loads and stores between storageand a set of 32 Floating-Point Registers (FPRs). It alsoprovides for byte, halfword, word, and quadword oper-and loads and stores between storage and a set of 32Vector Registers (VRs). It provides for doubleword andquadword operand loads and stores between storageand a set of 64 Vector-Scalar Registers (VSRs).

Signed integers are represented in two’s complementform.

There are no computational instructions that modifystorage; instructions that reference storage may refor-mat the data (e.g. load halfword algebraic). To use astorage operand in a computation and then modify thesame or another storage location, the contents of thestorage operand must be loaded into a register, modi-fied, and then stored back to the target location.Figure 1 is a logical representation of instruction pro-cessing. Figure 2 shows the registers that are definedin Book I. (A few additional registers that are availableto application programs are defined in other Books, andare not shown in the figure.)

Figure 1. Logical processing model

GPR-basedinstruction

instructions

data

instructions

processing

scalarfixed-point

branchinstructionprocessing

FPR-basedinstructionprocessing

scalarfloating-point

VR-basedinstructionprocessing

vectorfixed-pointfloating-pointpermute

VSR-basedinstructionprocessing

scalarfloating-point

vectorfloating-pointpermutescalar

integer (16B)BCD

crypto

storage


Version 3.0 B

“Condition Register” on page 30

“Link Register” on page 32

“Count Register” on page 32

“General Purpose Registers” on page 45

“Fixed-Point Exception Register” on page 45

“VR Save Register” on page 233

“Floating-Point Registers” on page 124

“Floating-Point Status and Control Register” onpage 124

“Vector Registers” on page 232

“Vector Status and Control Register” on page 232

“Vector-Scalar Registers” on page 364

Figure 2. Registers that are defined in Book I

1.5 Computation modes

Processors provide two execution modes, 64-bit modeand 32-bit mode. In both of these modes, instructionsthat set a 64-bit register affect all 64 bits. The computa-tional mode controls how the effective address is inter-preted, how Condition Register bits and XER bits areset, how the Link Register is set by Branch instructions

in which LK=1, and how the Count Register is tested byBranch Conditional instructions. Nearly all instructionsare available in both modes (the only exceptions are afew instructions that are defined in Book III). In bothmodes, effective address computations use all 64 bitsof the relevant registers (General Purpose Registers,

CR32 63

LR0 63

CTR0 63

GPR 0

GPR 1

. . .

. . .

GPR 30

GPR 310 63

XER0 63

VRSAVE32 63

FPR 0

FPR 1

. . .

. . .

FPR 30

FPR 310 63

FPSCR32 63

VR 0VR 1

...

...VR 30VR 31

0 127

VSCR96 127

VSR 0VSR 1

...

...VSR 62VSR 63

0 127

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Version 3.0 B

Link Register, Count Register, etc.) and produce a64-bit result. However, in 32-bit mode the high-order 32bits of the computed effective address are ignored forthe purpose of addressing storage; see Section 1.11.3for additional details.

1.6 Instruction FormatsAll instructions are four bytes long and word-aligned.Thus, whenever instruction addresses are presented tothe processor (as in Branch instructions) the low-ordertwo bits are ignored. Similarly, whenever the processordevelops an instruction address the low-order two bitsare zero.

Bits 0:5 always specify the primary opcode (PO,below). Many instructions also have an extendedopcode (XO, below). The remaining bits of the instruc-tion contain one or more fields as shown below for thedifferent instruction formats.

The format diagrams given below show horizontally allvalid combinations of instruction fields. The diagramsinclude instruction fields that are used only by instruc-tions defined in Book II or in Book III.

Split Field NotationIn some cases an instruction field occupies more thanone contiguous sequence of bits, or occupies one con-tiguous sequence of bits that are used in permutedorder. Such a field is called a split field. In the formatdiagrams given below and in the individual instructionlayouts, the name of a split field is shown in small let-ters, once for each of the contiguous sequences. In theRTL description of an instruction having a split field,and in certain other places where individual bits of asplit field are identified, the name of the field in smallletters represents the concatenation of the sequencesfrom left to right. In all other places, the name of thefield is capitalized and represents the concatenation ofthe sequences in some order, which need not be left toright, as described for each affected instruction.

Although instructions that set a 64-bit register affectall 64 bits in both 32-bit and 64-bit modes, operat-ing systems often do not preserve the upper 32-bitsof all registers across context swit

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Power ISA™ Version 3.0 B · 2070 Route 52, Bldg. 330 Hopewell Junction, NY 12533-6351 ... The Power ISA Version 3.0 B consists of three books and a set of appendices. Book I, Power