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7/29/2019 power integrity
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Power Integrity analysis techniques toget the best system performance at
the cheapest cost.
Power Integrity analysis techniques toget the best system performance at
the cheapest cost.
Sigrity, Inc.Sigrity, Inc.
EDAPS2009 Shenzhen, ChinaEDAPS2009 Shenzhen, China
Dec 2Dec 2ndnd, 2009, 2009
Tanit Virutchapunt
Power Integrity Specialist
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What is the best power plane performance?
What is bestDCpower plane performance? Devices see voltage closet to nominal voltage
Low IR dropWell balanced DC voltages among devices on the same rail
Low Temperature Rise on Metal Low Current Density
Power Efficiency Low Power Loss
What is bestDCpower plane performance? Devices see voltage closet to nominal voltage
Low IR dropWell balanced DC voltages among devices on the same rail
Low Temperature Rise on Metal Low Current Density
Power Efficiency Low Power Loss
What is best AC power plane performance? Low noise Low loop inductance Low and Flat impedance
What is best AC power plane performance? Low noise Low loop inductance Low and Flat impedance
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Best Performance VS Cost
$$
BESTBEST
Best power plane performance comes with a price. How to get the best powerplane without adding extra cost to the design is challenging to designer.
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What to look for in DC analysis?What to look for in DC analysis?
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IR drop target
Poor design
Total
margin
AC noise
margin
IR drop
AC noise margin
IR drop
Totalmargin
Good design
How to budget IR drop and AC noise margin?
IR drop margin should be less than AC noise margin since the AC
noise usually a lot harder to be controlled in the margin.
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6SIGRITY Confidential
Excessive IR drop due to narrow and long traces
criteria 66mV (2%)Voltage refdes Breif description Max current (A) IR drop (mV)
+3.3VCS U3_CP1 P6 0.250 -160U2_CP0 P6 0.250 -115
J23_GX1 GX CARD 0.218 -113
J24_GX2 GX CARD 0.218 -111J54_DASD DASD backplane 0.006 -29J49_RAID RAID card 0.006 -13U18_FSP1 FSP1 chip 0.51 -2.0J25_ENET0 ENET card 0.006 -1.4U31_HMC0 HMC chip 0.012 -1.2
U30_HMC0 HMC chip 0.012 -1.0
IR drop target is 66mVIR drop target is 66mV
159% over the target159% over the target
Functional problem can becaused by too much IRdrop
even in the low power .
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Excessive IR drop due to DC resistance on passive
components
There is no such thing as zero ohm resistor.
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Excessive IR drop on vias
10mV drop
2.4A flows into each via
5mV drop on each via
VRM
IC
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Understand Temperature Rise on coppercaused by current flow on the copper
Thickness = 0.5oz
Current VS AreaCurrent Density VS Width
IPC-2152 spec gives relationshipbetween Temperature Rise VS
Cross-session of copper.
Trace has an uniform cross-session thusIPC spec is straight forward.Shape has different cross-sessions atdifferent locations, IPC spec is no longerstraight forward.
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Same Current
5A 5A
100 sq.mil30c
500sq.mil
5c
With the same current flow on the plane, narrower plane will cause more heat.
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SameTemperature
5A 12A
100sq.mil
30c
500 sq.mil30c
To keep the same temperature rise on copper, wider plane can have more current.
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Same CurrentDensity
30mA/mil^
2
30mA/mil^
2
100 mil9c
500 mil32c
With the same current density flowing on the plane at different width,the wider plane will cause more heat on the copper since there is less
area heat can dissipate.
heat
heat
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Same Temperature
28mA/mil^2
100 mil
30c
500 mil
30c
56mA/mil^2
To keep the same temperature rise on copper, narrower plane can have highercurrent density.
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Smoke or Fire is number#1 concern,
what would happen if this design were built?
Temperature Rise = 300c
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Localize Heat in low power netThis low power rail can cause excessivecurrent density on the copper plane becauseof the narrow shape.
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Power Loss
High power loss area
Power Loss is important in all designsespecially products that use battery.
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Devices should see voltage closet to a nominal voltage
1A
2A
4A
5A
0.5A
10A1A
1A
1A 2A
4A
0.5A 0.5A 0.5A
0.5A 0.5A 0.5A 0.5A
VRM
With DC resistance on the plane that causes IR drop from power source to
devices, actual voltages at the devices will be less than the nominal voltage.
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Power Source location and voltage output setting
are important
1A200mV drop
1.5V1)
200mV drop
1A2)
1.7V
1A 1A
1A
52mV on each directionFrom regulator
1.552V
6)
1A
150mV drop 100mV
1A3)1.75V
3L/4 L/4
1A1A
75mV drop4)1.575V
75mV drop
L/2 L/2
Power Source
Device
60mV on each directionFrom regulator
1A 1A
2A
1.56V
7)
Current Flow
5) I2R1R2
L2 L1
I1
1.3V
1.5V
1.5V
1.5V 1.5V
VRM is at a location where R2*I2 = R1*I1
1.5V 1.5V
1.5V
1.5V 1.5V
1.5V
1.65V
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Impossible to place power source in the best
location for all devices
Mechanical requirement forcesconnectors to this place
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How to improve the power planeperformance without adding extra cost?
How to improve the power planeperformance without adding extra cost?
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How to identify copper areas that need to be
improved when DC voltage is failing?
Plane Current Density PlotPlane Current Density Plot
1st
2nd
3rd
VRM
Sink 1
Sink 0Sink 3
Sink 4Sink 5
Sink 2
5.25 V
4.75V
Plane Voltage Distribution PlotPlane Voltage Distribution Plot
Underflow color, Voltage below 4.75V
Improving high current density area can help three things:Improving high current density area can help three things:1. Reduce Resistance in this area2. Reduce current density which will make copper cooler
3. Cooler copper will make copper resistivity lower which will make evenless resistance in this area
Current density plot is used to identify areas
that should be used to add copper toimprove IRdrop.
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How to improve Power Efficiency?
Top L1 L2 Bottom Total %Trace 15.75 0 0 0 15.75 2Via 8.48 0.3 0 0 8.78 1Plane 73.94 45.78 666.06 47.67 833.45 97
Total power loss 857.98 mW
1A each
5A3A
RegulatorHigh Power Loss area
Identify high power loss areas in the design.Power Loss plot can be used to pinpoint high power loss area.
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How to find the via that will trigger field failure?
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Highest current vias from Thousand of vias
5A
Identify vias that have high current flow.Via Current plot can be used to pinpoint vias with high current flow.
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Optimize VRM sense line
to get the best DC voltage balance
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VRM
10A
Load sees 100mV belownominal voltage (1V)
Without feedback voltage sense to VRM
VR
M10A
Voltage Senselocation
Load now seesnominal voltage (1V)
With feedback voltage sense to VRM
Remote Sense Line is needed when the power
source cant be placed in the desired location
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VRM10A
Voltage Senselocation
1A
This device sees too highvoltage
This device sees perfect
voltage
1A
VRM
10A
Voltage Senselocation
This device sees too lowvoltage
This device sees perfectvoltage
Where to place the Sense Line when there are
more than one device on the power rail?
1V 1V1.08V
0.93V
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Chip1(10A)
Chip2(1A)
Chip1
Chip2
A typical way to find the optimal sense location
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A better way to find the optimal senselocations
[Patent Pending - U.S. Patent Application No. 12/468,807]
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Objective = minimizing voltage differences between actual voltage at devices and nominal voltage
With this example, Objective = min{ (Vdevice1 - Vnominal1)2+(Vdevice2 - Vnominal2)
2+(VdeviceN - VnominalN)2}
1) Start without any sense line
2) Determine the optimal output voltage level of VRM that meets the objective
3) With using the VRM output voltage level from (2) search meshes that have the nominal voltage.
4) The meshes that have the nominal voltage is the optimal sense locations.
5) Optimal Sense Location Tolerance maybe used to display sub-optimal sense locations.
Note that the rectangular meshes are used in the picture above to simplify the drawing and explanation.
Device1
VRM Device2
Vnominal
Vdevice1
Vdevice2
Vout_VRM
Optimal VRMOutput Voltage
Voltage Level
[Patent Pending - U.S. Patent Application No. 12/468,807]
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Optimal Sense Locations (Green)
1A10A
Voltage Senselocation
0.965V
1.035V
35mV
35mV
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Example
VRM connector 11 devices, 1A each
Where are the Optimal Sense Locations ?
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No sense line
Sense at U1
Optimal Sense Location
Sense here
Sense here
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34What to look for in AC analysis?What to look for in AC analysis?
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Flat and Low Power Plane Impedance
Regulator
BulkCapacitors
BoardDecaps
P
kgdecaps
Frequency (Log scale)PowerplaneImpedan
ce
On-chip capacitance
~1KHz