POWER and ENERGY OPTIMIZATION

POWER and ENERGY POWER and ENERGY OPTIMIZATIONOPTIMIZATION

Muhammed İ. KALKANMuhammed İ. KALKAN

20077043232007704323

Low Power Processor DesignLow Power Processor Design

Low power consumption is paramount in all types of processor-based embedded systems.

Battery-based portable systems require a low-power methodology.

Low power processor design includes gaining a Low power processor design includes gaining a thorough understanding of thorough understanding of How the application affects power,How the application affects power, Identifying power-hungry parts of the design and Identifying power-hungry parts of the design and

application, application, Comparing configuration optionsComparing configuration options


Processor power consumption as having two Processor power consumption as having two fundamental power components: fundamental power components: Static Static ActiveActive

Static power is consumed when there is no CPU activity Static power is consumed when there is no CPU activity on the digital signal processor (DSP) or microcontroller on the digital signal processor (DSP) or microcontroller (MCU). (MCU).

For the most part, static power is determined by For the most part, static power is determined by Semiconductor process technology,Semiconductor process technology, Processor core Processor core I/O voltages I/O voltages Device operating temperature. Device operating temperature.


Semiconductor vendors can minimize Semiconductor vendors can minimize static power with process-oriented static power with process-oriented adjustments such asadjustments such as Processes and transistors with low leakage Processes and transistors with low leakage

currentscurrents But there is a trade-offBut there is a trade-off

Lower frequency ,lower processor performance. Lower frequency ,lower processor performance.

Low Power Processor DesignLow Power Processor Design Major contributors to active powerMajor contributors to active power

CPU voltage, CPU voltage, Frequency, Frequency, Activity, Activity, Its peripherals activity Its peripherals activity Off chip memory activity. Off chip memory activity.

Various options on how a processor is used, system Various options on how a processor is used, system designers can optimize for low power operations by designers can optimize for low power operations by comparing different hardware and software comparing different hardware and software configurations. configurations.

The process starts with estimating active power The process starts with estimating active power consumption under various scenarios, module by consumption under various scenarios, module by module. module.

Low Power Processor DesignLow Power Processor Design The most common modules includeThe most common modules include

Clock generator Clock generator CPU CPU External memory interface (EMIF) External memory interface (EMIF) Direct memory access (DMA) interface or Host Processor Interface Direct memory access (DMA) interface or Host Processor Interface

(HPI) (HPI) Multi-channel Bufferes Serial Ports (McBSPs) Multi-channel Bufferes Serial Ports (McBSPs) Memory modules Memory modules SD card host controller SD card host controller I2C interface I2C interface Timers Timers USB ports USB ports Watchdog timer (WDT) Watchdog timer (WDT) Analog-to-digital converter (ADC) Analog-to-digital converter (ADC) Real-time clock (RTC) Real-time clock (RTC) General purpose IO interface. General purpose IO interface.


Utilizing Microcontroller Units to minimize Utilizing Microcontroller Units to minimize power consumption and extend battery life power consumption and extend battery life is accomplished through architectural is accomplished through architectural choices and software efficiency. choices and software efficiency.

Methods for Utilizing Power EfficiencyMethods for Utilizing Power Efficiency System designers should take full advantage System designers should take full advantage

of MCUs with clock systems that allow several of MCUs with clock systems that allow several low-power operating modes but is still based low-power operating modes but is still based on a single crystal. on a single crystal.


A low-frequency auxiliary clock will enable A low-frequency auxiliary clock will enable ultra-low-power standby mode with real time ultra-low-power standby mode with real time clock functionality. clock functionality.

A faster, internal digitally-controlled oscillator A faster, internal digitally-controlled oscillator (DCO) will allow the same crystal to source (DCO) will allow the same crystal to source the master clock used by the CPU and high-the master clock used by the CPU and high-speed peripherals, thus eliminating long start speed peripherals, thus eliminating long start ups required when the MCU architecture ups required when the MCU architecture includes two crystals or two-speed startup.includes two crystals or two-speed startup.


Using a faster clock while active allows Using a faster clock while active allows applications to minimize the time they spend applications to minimize the time they spend in an active mode, and can return to a lower in an active mode, and can return to a lower power standby most as quickly as the task power standby most as quickly as the task completes. completes.


Avoid polling as it keeps the MCU and the Avoid polling as it keeps the MCU and the system active more than is needed.system active more than is needed. SSystem designers should architect their ystem designers should architect their

products to be event-driven.products to be event-driven. Waking the MCU only when it needs to do Waking the MCU only when it needs to do

something is an important strategy in something is an important strategy in minimizing active power consumption. minimizing active power consumption.


Design the system with external devices Design the system with external devices that can be shut down or turned off. that can be shut down or turned off. With low duty cycle applications, this will With low duty cycle applications, this will

lower total system power consumption over lower total system power consumption over the operating life of an application compared the operating life of an application compared to using conventional low power devices that to using conventional low power devices that are always on. are always on.


Terminate unused pins because floating inputs Terminate unused pins because floating inputs are responsible for significant power loss are responsible for significant power loss

Integrating peripherals into the MCU is more Integrating peripherals into the MCU is more energy efficient than using discrete parts.energy efficient than using discrete parts. IIntelligent peripherals can offload the CPU so that it ntelligent peripherals can offload the CPU so that it

does not need to be over-clocked to deliver the does not need to be over-clocked to deliver the required system performance.required system performance.

Many MCUs allow the system to stay in a low power Many MCUs allow the system to stay in a low power mode with the CPU off but still allows system clocks mode with the CPU off but still allows system clocks to trigger integrated peripherals. to trigger integrated peripherals.


Another way to reduce energy Another way to reduce energy consumptionconsumption:: WWrite code that minimizes the number of clock rite code that minimizes the number of clock

cycles required for executing a command.cycles required for executing a command. Every instruction executed consumes a Every instruction executed consumes a

portion of the battery that will never come portion of the battery that will never come back. back.

CCode should be written to minimize the ode should be written to minimize the amount of memory in use at any time. amount of memory in use at any time.


RRandom memory location can be addressed and andom memory location can be addressed and operated on directlyoperated on directly

TThis approach requires both an additional his approach requires both an additional memory word and cycle. memory word and cycle.

WWrite instructions that use CPU registersrite instructions that use CPU registers TThey require only one clock cycle and one word of hey require only one clock cycle and one word of

code space.code space. Using CPU registers for dedicated variables will also Using CPU registers for dedicated variables will also

reduce code size and increase execution speed. reduce code size and increase execution speed.


On 16-bit architecturesOn 16-bit architectures:: AAddressing either words or bytes requires the ddressing either words or bytes requires the

same amount of code and cyclessame amount of code and cycles OOperate on words when possible to reduce perate on words when possible to reduce

code size and increase execution speed. code size and increase execution speed. If the MCU supports a constant generator, be If the MCU supports a constant generator, be

sure to utilize it.sure to utilize it.


Constant generators automatically Constant generators automatically generate the most frequently used generate the most frequently used immediate constants in hardware. immediate constants in hardware.

PPowerower reduction occures reduction occures if if a dedicated a dedicated CPU register is used automatically for CPU register is used automatically for constant generation. constant generation.

No operand is fetched from memory, No operand is fetched from memory, saving code and increasing speed. saving code and increasing speed.


Other ways to save powerOther ways to save power Use local variables as much as possible because the Use local variables as much as possible because the

CPU registers instead of the RAM used by global CPU registers instead of the RAM used by global variables variables

Use bit mask instead of bitfields for unsigned Use bit mask instead of bitfields for unsigned intint and and unsigned unsigned charchar

Use unsigned data types when possible Use unsigned data types when possible Use pointers to access structures and unions Use pointers to access structures and unions Use "static const" class to avoid run-time copying of Use "static const" class to avoid run-time copying of

structures, unions and arrays structures, unions and arrays Avoid modulo. Avoid modulo.


SSplit-rail designplit-rail design : : AAllowllowss lower voltages to be used in the lower voltages to be used in the processor processor

corecore while the external while the external Input/Output Input/Output ((I/OI/O) voltages ) voltages remain 3.3 volts for backwards compatibility.remain 3.3 volts for backwards compatibility.

Dual-voltage CPUs were introduced for performance Dual-voltage CPUs were introduced for performance gain when increasing clock speeds and finer gain when increasing clock speeds and finer semiconductor fabrication processes resulted in semiconductor fabrication processes resulted in excess heat generation and power supply concerns, excess heat generation and power supply concerns, especially regarding laptop computers.especially regarding laptop computers.

Using a voltage regulator, the external I/O voltage Using a voltage regulator, the external I/O voltage levels would be transformed to lower voltages in order levels would be transformed to lower voltages in order to reduce power usage, resulting in less heat being to reduce power usage, resulting in less heat being produced with the ability to operate at higher produced with the ability to operate at higher frequencies. frequencies.


Dynamic Voltage Scaling:Dynamic Voltage Scaling: Dynamic voltage scalingDynamic voltage scaling is a power management is a power management

technique in computer architecture.technique in computer architecture. The voltage used in a component is increased or The voltage used in a component is increased or

decreased, depending upon circumstancesdecreased, depending upon circumstances Dynamic voltage scaling to decrease voltage is known Dynamic voltage scaling to decrease voltage is known

as as undervoltingundervolting.. Undervolting is done in order to conserve power, Undervolting is done in order to conserve power,

particularly in laptops and other mobile devices, particularly in laptops and other mobile devices, where energy comes from a battery and thus is where energy comes from a battery and thus is limited. limited.

Overvolting is done in order to increase computer Overvolting is done in order to increase computer performance. performance.

Digital Voltage Digital Voltage Scaling LoopScaling Loop The feedback loop

for converting a desired operating frequency


Dynamic Frequency Scaling:Dynamic Frequency Scaling: Technique in computer architecture where a Technique in computer architecture where a

processor is run at a less-than-maximum processor is run at a less-than-maximum frequency in order to conserve power. frequency in order to conserve power.

As frequency changes, the dynamic power will As frequency changes, the dynamic power will change linearly with it. change linearly with it.

Dynamic power does not account the total power Dynamic power does not account the total power of the chipof the chip

There is also static power, which is primarily due There is also static power, which is primarily due to various leakage currents to various leakage currents


Leakage Current:Leakage Current: Gradual loss of energy from a charged Gradual loss of energy from a charged

capacitor. capacitor. It is primarily caused by electronic devices It is primarily caused by electronic devices

attached to the capacitors, such as transistors attached to the capacitors, such as transistors or diodes, which conduct a small amount of or diodes, which conduct a small amount of current even when they are turned off.current even when they are turned off.

Even though this off current is an order of Even though this off current is an order of magnitude less than the current through the magnitude less than the current through the device when it is on, the current still slowly device when it is on, the current still slowly discharges the capacitor. discharges the capacitor.


Clock Gating:Clock Gating: One of the power-saving techniques used on many One of the power-saving techniques used on many

synchronous circuits including the Pentium 4 synchronous circuits including the Pentium 4 processor. processor.

In order to save power, clock gating support adds In order to save power, clock gating support adds additional logic to a circuit to prune the clock tree,additional logic to a circuit to prune the clock tree,

Disabling portions of the circuitry so that its flip-flops Disabling portions of the circuitry so that its flip-flops do not change statedo not change state

Their switching power consumption goes to zero, and Their switching power consumption goes to zero, and only leakage currents are incurred. only leakage currents are incurred.


Prone the idle partsProne the idle parts


A Study for Low Power CPU Design (Briefly)A Study for Low Power CPU Design (Briefly) As clock frequency increases and feature size

decreases,clock distribution and wire delays present a growing challenge to the designers of singly-clocked, globally synchronous systems.

An alternative approach, which is called a Multiple Clock Domain (MCD) processor, in which the chip is divided into several (coarse-grained) clock domains, within which independent voltage and frequency scaling can be performed.


In an MCD microprocessor each functional block operates with a separately generated clock, and synchronizing circuits ensure reliable inter-domain communication.

An MCD microprocessor affords a number of potential advantages over a singly clocked design:


The global clock distribution network is greatly simplified,requiring only the distribution of the externally generated clock

The designers of each domain are no longer constrained by the speeds of critical paths in other domains,

Greater freedom in each domain to optimize the tradeoffs among clock speed, latency, and the exploitation of application parallelism via complex hardware structures.


Using separate voltage inputs, external voltage regulators, and controllable clock frequency circuits in each clock domain allows for finer grained dynamic voltage and frequency scaling,

Allows lower energy, than can be achieved with single clock, single-core-voltage systems.



Division of Chip into Clock Domains Design uses four domains, one of which

includes the L2 cache, so that domains may vary somewhat in size and still be covered by a single clock.

No energy savings from decoupling instruction fetch from rename/dispatch,

Combine these regions into a single fetch/rename/dispatch domain to eliminate their interdomain synchronization overhead.


Execution units of the same type (e.g., integer units) were combined into a single domain to avoid the high cost of synchronizing the bypass and register file datapaths among these units.

Inter Domain Synchronization Synchronizing the modules seperated


Work concludesWork concludes Multiple clock domain (MCD)

microarchitecture, which uses a globally asynchronous, locally-synchronous (GALS) clocking style

With dynamic voltage and frequency scaling in order to maximize performance and energy efficiency for a given application.


Scaling frequency and voltage in different domains dynamically and independently

Can achieve an average improvement in energy-delay product of nearly 20%

On the other hand, global voltage scaling to achieve comparable performance degradation in a singly clocked microprocessor achieves an average energy-delay improvement of only 3%.

ReferencesReferences

http://en.wikipedia.org/wiki/Dynamic_voltage_scaling Energy-Efficient Processor Design Using Multiple Clock

Domains with Dynamic Voltage and Frequency Scaling, Greg Semeraro, Grigorios Magklis, Rajeev Balasubramonian, David H. Albonesi, Sandhya Dwarkadas, and Michael L. Scott

http://en.wikipedia.org/wiki/Dual-voltage_CPU LOW-POWER PROCESSOR DESIGN,Ricardo E. Gonzalez http://en.wikipedia.org/wiki/Dynamic_frequency_scaling http://www.automotivedesignline.com/212200726?

cid=RSSfeed_automotivedesignline_adlRSS http://en.wikipedia.org/wiki/Dual-voltage_CPU http://www.powermanagementdesignline.com/howto/

batterymanagement/212100642

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POWER and ENERGY OPTIMIZATION